This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2585587, IEEE Journal
of Emerging and Selected Topics in Power Electronics

Fixed Frequency Sliding Mode (SM) Control

Scheme Based on Current Control Manifold for
Improved Dynamic Performance of Boost PFC
Converter
Pratap Ranjan Mohanty and Anup Kumar Panda, Senior Member, IEEE

Abstract—This paper deals with the switching regulation of +

Boost PFC converter under large and quick load fluctuation to
ensure tight output voltage regulation and unity power factor Line Bridge
DC
Bus vo
(UPF) at line side. In this sense, Sliding Mode Control (SMC) vin Input Rectifier
DC-DC L

technique based on current controlled manifold is proposed. vg Converter for O

A
PFC Stage D
Input current distortion is limited even during light loading -
condition. Also, the dead-zone issue related to light load near
to the crossover of input current is resolved in this paper. Control
Scheme
Gain
To execute the proposed SMC algorithm, equivalent control
approach is used for the selection of sliding coefficients, ensuring
the system stability. The control operation manipulates both inner Fig. 1. Basic block diagram of PFC system
SM current controller to frame input current and an outer
PI controller to maintain desired regulated output voltage. For
experimental validation, a 500W, 390V/DC boost PFC prototype,
controlled by dSPACE 1104 signal processor is framed. The high PF with enhanced dynamic performances is the recent
presented simulation and experimental results infer that the trend in engineering research [2].
proposed converter controller offers UPF, tight output voltage In general, the load value is uncertain in this kind of AC-DC
regulation and %THD (Total Harmonic Distortion) standard even systems [3]. This confusion develops a critical challenge for
under fluctuating load behaviour. In this paper, the performance
of the proposed control scheme is experimentally verified with
the researchers in achieving reliable performance under large
different load behaviour and external references, which explains and rapid load disturbances. Sense to this problem, a produc-
the robustness and effectiveness of the proposed system. tive solution is suggested in [4], however, it can be the superior
choice for the system where the chance of load deviation is
Keywords—current control manifold, sliding mode, fluctuating too narrow and high-quality current is not vital. Likewise,
load, dead-zone. an elementary solution with better dynamic performance is
anticipated in [5] but the performance of converter collapses
I. I NTRODUCTION in the light loading state specifically, close to the zero-crossing
zone [3]. On the other hand, the converter may operate in the

T HE user community of electronics utility is increasing

day by day. Invariably these electronic devices consists of
rectification circuit which acts as nonlinear load and introduces
discontinuous conduction mode (DCM) due to variation in on-
load parameter, which is discussed in [6], [7]. Due to this DCM
feature during reduced loading, dead-zone arises close to the
lower order harmonics. Also, some form of ac to dc power zero-current crossing and this results crossover distortion and
supply configuration are being used within the architecture of fast scale instability [8]. Furthermore, this restrains property
most modern electrical and electronics apparatus. However, execrably sluggish dynamic response in converter system.
due to this supply configuration, the rectified sine wave voltage Henceforth, many control techniques have been developed in
draws pulsating current with high amplitude from their source recent years to limit the dead-zone close to the zero-crossing
during each half cycle. Hence, PFC (Power Factor Correc- region, however, the dynamic performance of the converter
tion) converter as presented in Fig. 1 has been extensively under load fluctuation is not apparently deliberated. A time-
implemented in AC-DC system to comply with regulations varying compensation approach with the peak current control
of low-input current harmonic distortion. The focus of PFC scheme is suggested in [8] to resolve fast scale instability
is to obtain high power factor (PF) and lower percentage due to zero-current dead-zone, whereas, transient loading state
of THD [1]. Associated to this, The PFC system can be isnt considered in this to examine the dynamic performance
improved to obtain high quality of power which is more of the system. Again, Sliding Mode Control (SMC) scheme
essential for distribution system in order to satisfy IEEE Std. is implemented to interleaved boost PFC system in [9] and
519, IEC 61000-3-2 or EN 61000-3-2 [1, 2]. Henceforth, a better solution is achieved to resolve the issue concerned
development of switched-mode ac-dc PFC circuits to ensure to load variation, but the performance under light loading

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2585587, IEEE Journal
of Emerging and Selected Topics in Power Electronics

Reference a conventional boost converter is considered in this paper

vo - Voltage, Vref
Boost + for the implementation of proposed current controlled SMC
Converter
Voltage-Loop technique. The block diagram presented in Fig. 2 illustrates
d Controller
iL control operation of the boost PFC system. The control strategy
Current-Loop - of boost PFC system is more significant, since, it helps to
+
Controller iref Rectified
Multiplier Input obtain sinusoidal inphase current as well as maintains output
v
Voltage, g
voltage regulated [14]. Besides, the executed controller should
have a quick dynamic response to the load variation [15], [16].
Fig. 2. Basic block diagram of closed-loop boost PFC converter In general, the control scheme for boost PFC system consists
of two cascaded control loops [14], [17], termed as voltage
control loop and current control loop. The voltage control
vg
loop presents in the outer loop path and maintains regulated
Vg voltage at output bus, regardless of loading condition. Again,
the current control loop is the inner one which operates with
very fast control action and enforces the input current to trace
iref t the sinusoidal input voltage waveform [14].
I The ideal voltage and current waveforms of a typical PFC
converter system is presented in Fig. 3. Due to the squared
t
pi sinusoidal input power, the ripple of the output voltage is
Pi unavoidable for power balance. The storage capacitor has
significant effects of limiting the ripple at the modest level.
Hence, the dynamic response of the output regulation loop
depends on the size of the capacitor. Also, for each rectified
t line cycle the regulation of output voltage is vital. The outer
po
voltage regulation loop permits maximum bandwidth of line
Po
frequency under UPF condition [18]. It is essential to control
each cycle of input current at the switching frequency to
obtain a sinusoidal envelope of the source current. Henceforth,
t
T (One Cycle Period) this entails that the current control loop needs much higher
bandwidth than the voltage control loop. The cascaded multi-
loop control assembly validates the time scale separation of
Fig. 3. Ideal waveforms of PFC system system dynamic into two control loops [19], [20], such that
the current loop is the faster controlled whereas, the outer
loop is sluggish one. Hence, a high bandwidth control scheme,
scenario is not evaluated. In [10], a hysteresis modulation operating at high frequency has to be implemented in the inner
technique is executed to abolish the distortion due to dead- current loop of boost PFC converter.
zone however; uncertain load variation isnt considered here. For the modelling of PFC converter-controller system, first
?? In this paper, SMC technique based on the current - the operational system dynamics are required to be identified.
controlled manifold is applied for the switching regulation The unpredictable behaviour like variable supply voltage and
of boost PFC converter and the dynamic performance of the frequency inherently govern the system dynamics. At the
system under quick and large load fluctuation is enhanced. same time, the variable load behaviour with fixed frequency
Additionally, the implemented control technique is subjected operation [21] of converter system demands quick and per-
to resolve the deadzone issue related to light loading con- fect switching regulation, which is a difficult job with these
dition. To develop the current-controlled SMC algorithm, an operating trademarks. Concerned with this, linear controllers
additional term is added to the voltage error and current error like average current mode and peak current mode controllers
together to reduce the steady state error in both the output are much predominant but performance is important for high
voltage and inductor current. The auxiliary term is the integral power applications [22], [23], [24], [25]. The impact of
of both the voltage error and current error together. Explicitly, multipliers and large variation of the duty ratio restrain the
this paper is concerned to formulate a switching regulation conventional linear controllers. Certain dynamics like source
function which can monitor the system dynamic, even under impedance, nonlinearity in multiplier, deviation of input volt-
inexact time varying loading scenario and attain improved age from anticipated sinusoidal shape, attachment of filter,
dynamic performance. tolerance of passive component, limited bandwidth and nonlin-
Subject to the topological matter on PFC, researchers always earity in sensor circuits are ignored in mathematical modelling
suggest boost [11], [12] configuration due to its distinct integral of PFC converter and controller [26]. Although a linear control
features like simple gate drive circuit, natural gain feature, system offers satisfactory performance by utilizing a small-
step-up conversion ratio, the current smoothing attribute, etc. signal model [15] for linearization around a stable operating
Also, boost converter is the usually reasonable option for PFC point, the controller has an intrinsic constraint in terms of
system in medium and huge power utilization [13]. Hence, third harmonics in the input current. Notch filter is used in

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2585587, IEEE Journal
of Emerging and Selected Topics in Power Electronics

sluggish low band-width voltage control loop for improved trial-and-error regulation practice is required in fuzzy-logic
dynamic response of the converter to the load change [27]. systems, and furthermore, its design is purely heuristic [36].
Furthermore, the performance of a conventional controller is Again, the research on performance improvement of the PFC
reasonably pitiable, if the system is running apart from the converter system in the current decade [3], [8], [9], [10] is
linearized working point. Therefore, the desirable alternative most encouraging and motivating, which have been deliberated
is a nonlinear model which can capture the nonlinear singu- earlier.
larities and the system appearances over an extensive scale of The RHPZ characteristic of duty-ratio-to-output-voltage
operating points [28]. transfer functions for boost converters in CCM operation
To ensure improved dynamic performance many nonlinear forms the controlled dynamic response of the system lethargic,
controllers are implemented in PFC converter system by intro- specifically, if the controller is based on voltage-mode control
ducing intrinsic control action. In [29], a new nonlinear control action [37]. Irrespective of both linear and nonlinear type
technique is developed which eliminates the requirement of controllers [32], the RHPZ feature twists the controller design
sensing the input voltage, leading to oversimplification of the and bounds the bandwidth of the compensation circuit in
control strategy. But, this acts as weakness in terms of voltage the voltage-mode control action [38]. Author [39] suggests
regulation. A set of new nonlinear controllers is implemented current-mode control action as a familiar alternative to attain
in [25], where two different feedforward duty ratio signals are fast dynamic response in the RHPZ converter arrangement.
used to avoid instability, dead-zone at zero-crossing and input In general, tight output voltage regulation and sinusoidal
current distortion. A partial feedforward duty ratio signal is input current can be obtained easily, if a control scheme with
formulated in one of the control technique by ignoring the a high switching frequency is applied to regulate boost PFC
voltage across the boost-inductor, hence, least reliable. A very system. Again, this switching frequency varies when the output
simple alternative for boost PFC converter is proposed in [5] load and the supply voltage vary [40], [41], however, this is
but it is very sensitive to the converter parameters. In spe- the common feature of a power distribution network. As a
cific, at reduced load condition, poor performance is observed result, designing of PFC converter becomes difficult and the
exclusively near to the zero-crossings of input current. regulation properties of the converter deteriorate [42]. Besides,
So far, Sliding mode control technique based on current it is commonly known that switching converters act as sever
mode control is implemented in [30], [31] to enhance static noise generators and fixed-frequency switching is the best
and dynamic performances of PFC converter under large option to reduce noise containing irrespective of the operating
variation of output voltage reference and load. Selection of conditions [32].
gain parameters plays vital role in system stability when To counteract the variation of frequency in SMC, several
operates in SM. Henceforth, an optimization scheme is adopted methods have been discussed in [32], [43], [44]. The constant
additionally for the computation of sliding gain parameters. frequency approach can be realized by incorporating constant
Whereas, for switching regulation of DC-DC converter under ramp or timing function into the controller. In other way, any
current controlled SM,[32] suggests to consider the combine adaptive control algorithm can be included into the controller
integral of both the current and voltage errors additionally in to nullify the switching frequency variation. Furthermore,
sliding plane design. Along with, equivalent control approach PWM (Pulse-width Modulation) can be incorporated in the
is applied for the selection of sliding gains. Fuzzy-logic place of hysteresis modulation (HM) to execute fixed fre-
controller and SMC are implemented in [33], [34], [35]. The quency SMC scheme. The method of incorporating auxiliary
SMC based DC-DC converter [33] has inadequate operating ramp or adaptive control circuit may be easy, but the system
performance in saturation region; as optimal operation is viable suffers from a weakened transient response comparatively.
only in particular settings. On the contrary, a time-demolishing Hence, in this paper, the PWM technique is included in
current-controlled SMC scheme for the switching regulation
of boost PFC system.
Boost Converter
Henceforth, it is proposed to develop a SMC boost converter
D
focusing on current-controlled sliding manifold for achieving
iL L SW vo improved dynamic performance under inclusive variation of
Rectifier
u steady and transient operating circumstances, ensuring UPF at
io input and regulated output voltage, inherently. This paper is
vi PWM
specifically concerned with the evolution of a fixed-frequency
+
vC
- C RL SM current controller for boost PFC converters. In this paper,
Vramp(t) an inherent control action is introduced by adding an integral
SM Current
Controller
term of both the voltage error and current error together for
the designing of sliding surface which ensures the reduction of
steady state errors in both output voltage and inductor current.
β vo β The behavioral model of PFC boost converter, operating in
PI -

Controller
+
Vref continuous conduction mode (CCM) is used to obtain its
dynamic model. Ziegler Nichols tuning technique is adopted
to design the outer voltage-looped PI compensator. Fig. 4
Fig. 4. Boost PFC ac-dc regulator under current-controlled SM scheme illustrates the closed-loop operation of the boost PFC converter

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2585587, IEEE Journal
of Emerging and Selected Topics in Power Electronics

with an outer PI controller and proposed SM current controller A. Dynamic Model of Boost PFC Converter
in inner control loop. The simulation in MATLAB/Simulink Fig. 5 represents the basic boost PFC converter system,
of proposed control scheme and its execution in real-time where iL and vo are the instantaneous inductor current and
by dSPACE 1104 are examined to enhance the dynamic output voltage respectively. In this paper, the current error x1 ,
performances of boost PFC converter. the voltage error x2 and the combined integral of both voltage
This work is particularly to develop a current controlled error and current error x3 are taken as the controlled state
SMC scheme for boost PFC system, ensuring unity power variables for the designing of sliding surface. The linear com-
factor (UPF) at line side and inherent tight regulated voltage at bination of the state variables is considered for the selection
the output. Due to the implementation of the proposed control of sliding plane S, i.e.
approach, the performance of PFC system is improved in such
a way that the tracking of the input current to the desired S = α1 x1 + α2 x2 + α3 x3 (2)
sinusoidal shape is explored closely, with respect to load
transient. Also, the dynamic response of output voltage subject where, α1 , α2 and α3 are the sliding coefficients.
to load fluctuation is evaluated in this paper. Additionally, the
x = iref − iL

dead-zone issue, concerned to zero-crossing of input current at  1

x2 = vRref − βvo
light loading is significantly resolved in this paper. Moreover, (3)
the principal focus of this paper is to formulate a switching  x3 = R (x1 + x2 )dt
 R
= (iref − iL )dt + (Vref − βv0 )dt
regulation function which can monitor the system dynamic,
even under inexact time varying loading scenario. Moreover, The behavioral model of the boost PFC converter system
the dynamic performances of the proposed converter-control operating in CCM and the time differentiation of equ. 3 are
system is improved, ensuring almost UPF and also, it retains used to derive the dynamic model of boost PFC converter,
the input current harmonic within the tolerable limit. obtained as;
 d
II. SMC C URRENT C ONTROLLER 
 ẋ1 = dt [ihrefn− iL ]
 d β
R o i
= K Vref − C iC − iL


Generally, both current error and output voltage error are

 dt
vg −ũvo

employed as the state variables for the designing of the = −KβC iC − L (4)
SM current controller. Perfect output voltage regulation is d −β


 ẋ 2 = dt [V ref − βv 0 ] = C iC
possible by including the output voltage error. However, the

 ẋ = x1 + x2
 3


current error enforces the inductor current to track tightly the = (K + 1)(Vref − βv0 ) − iL
anticipated reference inductor current, which is vital to obtain
a quick dynamic response for converter system under RHPZ where, ũ = 1 − u is the inverse logic of u. vg is the instan-
feature. taneous rectified input voltage, vc denotes the instantaneous
Amplified output voltage error is used to generate instanta- capacitor current, C and L denote the output capacitor and
neous reference current iref , i.e. boost inductor of the converter, respectively.
The switching function, u = 12 (1 + sign(S)) signifies the
iref = K[Vref − βvo ] (1) logic state of the power switch SW for hitting condition of
state trajectory. By solving Ṡ = α1 ẋ1 + α2 ẋ2 + α3 ẋ3 = 0 the
Vref → Reference output voltage equivalent control signal, ueq is derived, i.e.
vo → Instantaneous output voltage
β → Feedback network ratio
K → Amplified gain of voltage error K2 vi K1 K3
ueq = 1 − iC − + [Vref − βvo ] − iL (5)
vo vo vo vo
In this paper, high value of K is taken for enhanced dynamic ueq is continuous and bounded by 0 to 1. Hence, the inequality
response and least steady state voltage error in the converter can be rewritten as; 0 < u < 1.
system.
h i
v
or, 0 < 1 − vo iC − vgo + K
K2 K3
vo [Vref − βvo ] − vo iL < 1
1

or, 0 < K1 [Vref − βvo ] − K2 iC − K3 iL + vo − vg < vo

iL L D
+
io
L
+ or, vC ∗ = Vref − βvo − K2 iC − K3 iL + vo − vg (6)
SW
+ O
Vg Co A Vo where K1 , K2 and K3 are the fixed gain parameters in the
- D - controller and mathematically,
 α3
-  K1 = α1 L(K + 1)

K2 = βL C K+αα1
2
(7)
 K = α3 L

Fig. 5. Basic boost PFC converter system 3 α1

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2585587, IEEE Journal
of Emerging and Selected Topics in Power Electronics

iC iL(t)
vc GsK1[Vref - βvo] - GsK2iC
u uPWM + - GsK3ig + Gs[vo - vg]
× PWM ig IL(max)
-
IL(min)
uCLK Vramp vg vo Vref
0
iC(t) t

Fig. 6. Block diagram illustrates implementation of SM current controller IC(max)

control function
0
t
Fig. 6 is the block diagram demonstration of the control IC(min)
function for the switching of device under current-controlled
SM method. The controller is resulted from the sliding surface u=1 u=0 u=1 u=0
(equ. 2) and comparing ueq = d, where d is the duty cycle
ratio of the controller. Mainly, the switching control function
comprises two signals, among which a control signal, vc and a Fig. 7. Current waveform of boost inductor (upper) and output capacitor
(lower)
ramp signal, Vramp are present. And the control law equation
is described as;
existence is obtained as;
    
vC = GS K1 [Vref − βvo ] − GS K2 iC − GS K3 iL + vo − vg vg(min) − K1 Vref − βvo(SS)

vramp = GS vo 0< 
+K2 iC(min) + K3 iL(max)



(8) (10)
   
Looking to the experimental validation a factor 0 < GS < 1 vg(max) − K1 Vref − βvo(SS)


< vo(SS)

has been introduced for scaling down the equation to a

+K2 iC(max) + K3 iL(min)
practical level, ensuring implementation of chip-levels voltage
standard. An impulse generator with a clock signal, uCLK and where, vg(min) and vg(max) represent the minimum and max-
a logic AND operator are added to the circuit for ensuring imum input voltage respectively; and vo(SS) symbolizes the
that the duty ratio of the controllers output is always under projected steady-state output voltage, which is mostly a con-
unity, which is more vital for protection [32]. Responding stant factor of a small error from the preferred reference
to the suggestion of [44], a duty ratio of 0.65 is selected voltage, Vref . Fig. 7 describes the physical significance of
in this paper for the implementation of proposed controller. inductor and capacitor current, where iL(min) , iL(max) , iC(min)
Additional current sensor is incorporated to sense the current and iC(max) individually denotes the respective minimum and
through output capacitor and this takes part as the key factor, maximum inductor and capacitor currents at full-load converter
comprising to a faster responding RHPZ converter structure. operation.
To end with, the controller gain parameters K1 , K2 and
K3 must obey the circumstances as in equ. 10. Hence, the
value of K1 , K2 and K3 are selected accordingly to ensure
B. Existence Condition the existence of SM operation at least in the small area for all
The sliding surface (S) equation and its time derivative dS operating conditions within the specified input and load range.


dt
together give the local reachability condition, limS→0 S.Ṡ < 0.
The mathematical simplification of the reachability condition C. Stability Condition
gives the existence condition for the proposed SMC system.
Hence, the existence condition is derived as; The sliding surface, S = 0 designed in this paper for
SM current controller comprises both the voltage and cur-
rent as state variables. Hence, it appears extremely nonlinear
" h
vg
i #  and obtaining an analytical solution becomes more complex.
α1 −βK i C − − α β
i
2C C Hence, the selection of sliding gains to attain the stability
C L <0



+α3 ((K + 1) [Vref − βvo ] − iL ) condition isnt inherently performed as in voltage controlled



(9) SMC system by designing the converter-controller system for
some anticipated dynamic features [43], [45]. Therefore, the
" h i #
−βK vg −vo β

α1 −
C iC − α2 C iC


L >0 

 equivalent control technique is considered as the fundamental
+α3 ((K + 1) [Vref − βvo ] − iL ) [35] in this paper and a dissimilar approach is adopted to
confirm the stability of the controller. This approach includes
Again, to attain the existence condition for steady-state identification of ideal sliding dynamics of the system, the
operation [5], static sliding surface is assumed in this paper. equilibrium point analysis, and finally derivation of stability
Therefore, by substituting equ. 7 in equ. 9, the simplified condition [46] in a sequential process.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2585587, IEEE Journal
of Emerging and Selected Topics in Power Electronics

1) Ideal Sliding Dynamics: Based on equivalent control

method, the converter description equation is modified by ũ s2 + (a11 + a12 )s + a11 a22 − a12 a21 = 0 (16)
is replacing as ũeq . Hence, the converter description equation
under CCM operation translates the discontinuous system into For the stability of the system, the considered conditions
an ideal SM continuous system: are; 
a11 + a22 < 0
 di v
 dtL = Lg − vLo ũeq (17)
a11 a22 − a12 a21 > 0
(11)
 dvo = iL ũ − vo Again, conditions (17) are generalized mathematically to
dt C eq rL C obtain simplified stability condition. The logics implemented
Subsequently, the substitution of equ. 5 into equ. 11 reforms: for the generalization are;
 diL • For the case a11 + a22 < 0, the stability condition is:
 hdt = h ii 
vg

vo K2 vi K1 K3 K 3 V g RL C V V R
− 1 − i − + [V − βv ] − i




 L L vo C vo vo ref o vo L

 LβVo + βVgo < K1 , when K2 > gVo L
(18)

dvo  K3 Vg RL C + Vg > K1 , when K2 < Vg RL
hdt =h

LβVo βVo Vo

 i i
 iL K2 vi K1 K3 vo
C 1− vo i C − + [Vref − βvo ] − vo i L −




 vo vo rL C • For the case a11 a22 −a12 a21 > 0, the stability condition
is:
(12)  
Equ. 12 represents ideal sliding dynamics of boost PFC 2K3 Vo3 (K2 − K1 βRL )
converter, operating under the SM current control scheme.  +Vg Vo2 K2 (K1 βRL − 2K2 )  > 0 (19)
2) Equilibrium Point Analysis: Assumption to this, the ideal +Vg2 Vo RL (3K2 − K1 βRL ) − Vg2 RL 3

sliding dynamics has ultimately settled on the sliding surface

The existence condition (10) and the stability conditions
where an equilibrium point is existing. Also, at equilibrium:
diL dvo (18) and (19) ensure the closed-loop stability of the system
dt = 0 and dt = 0 and concurrently, become vital to select and design the control
gains of the SM current controller for the specified boost PFC
Therefore, the steady-state equation is obtained as;
converter. As per the suggestion of the author [32], K1 , K2 are
Vo2 employed with very high value and K3 is arbitrarily chosen
IL = (13) with a low value at the nominal rating of the converter system.
Vg RL
Then, the control gain parameters are tuned with respect to
where, Vo , IL , Vg and RL denote the output voltage, inductor step load change to achieve the desired performance of the
current, rectified input voltage, and load resistance at steady- converter. Unlike a conventional controller, re-tuning of control
state equilibrium respectively. parameters to costume the new operating conditions is not
3) Linearization of Ideal Sliding Dynamics: For lineariza- required for the proposed SM current controller, which is an
tion, certain assumptions are considered with reference to the advantage.
steady-state operation of the system, i.e. vg = Vg , rL = RL ,
iref = IL , Vref = βVo , IL >> ĩL and Vo >> ṽo . III. O UTER PI C OMPENSATOR
Therefore, by linearizing the ideal sliding dynamics around
the equilibrium point, the equ. 12 becomes: To sustain the output voltage regulation, a PI controller is
implemented in the outer voltage loop. The comparison of
output voltage, vo and the reference, Vref is processed in

 ddt
ĩL
= a11 ĩL + a12 ṽo
(14) PI controller to obtain constant output voltage. The controller
 dṽo
= a ĩ + a ṽ gain values are found by the help of Ziegler-Nichols tuning
dt 21 L 22 o
method, which ensures sustained oscillations with the ultimate
where,  gain, Ku = 3.6 and ultimate period, Pu = 0.06s. Hence, the
K 3 V g RL

 a11 = K2 LVo −LVg RL
values for Kp = Ku /2 and Ki are suggested as 1.8 and
20 (Ti = Pu /1.2 , Ki = 1/Ti ) , respectively.




Vg2 RL


K1 βVg RL −2K2 Vg +

 Vo
 a12 =


 K2 LVo −LVg RL IV. S IMULATION S TUDY
(15) The proposed control scheme is developed in MAT-
V 2 RL
K2 Vg −K3 Vo − gVo LAB/SIMULINK for a single-phase AC-DC converter as


a21 =




 K2 CVo −CVg RL illustrated in Fig. 4. The outer loop is operating with a



 K2 V o
PI compensator whereas Current-controlled SM controller is
−K1 βVo
implemented to drive the inner current loop. And the whole
 RL 1
 a22 = −

K2 CVo −CVg RL RL C
system is simulated with consideration of specification pre-
This linear system is mathematically characterized in the sented in Table I and control parameters presented in Table
form; II.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2585587, IEEE Journal
of Emerging and Selected Topics in Power Electronics

In this paper, a load resistance of 300 is taken as 100% load

Source Current
5 1

Input Current (amp)

for the simulation study and the required result waveforms are PI Controller

(amp)
0
traced. The simulation waveforms presented in Fig. 8, Fig. 9 -5
and Fig. 10 describe the performance of the proposed scheme 0 0.2 0.4 0.6 0.8 1
Time (sec)
for the boost PFC converter. Subject to the loading behaviour, -1
0 0.01 0.02 0.03 0.04
Time (sec)

Output VOltage
420 Vo 1

Input Current (amp)

Vref SM Current Controller

(volt)
TABLE I. S PECIFICATION OF BOOST PFC CONVERTER WORKING ON 400

PROPOSED SMC SCHEME

0 0.2 0.4 0.6 0.8 1
Converter parameters Parameter specification Time (sec)
-1
0 0.01 0.02 0.03 0.04
Time (sec)
Supply voltage Vi (volt) 230 AC/RMS
Boost inductor L (mH) 1
Boost filter capacitor C (µF) 470 (a) (b)
Load Po (W) 500
Switching frequency fSW (kHz) 200 Dead-Zone at Zero-Crossing Point of Input Current

Standard reference Vref (volt) 400

(%age of Fundamental)

Current (amp)
SMC

Output voltage Vo (volt) 390 Fundamental (50Hz) = 3.1amp , THD= 2.40%

0

Magnitude
1.5

TABLE II. L IST OF CONTROL PARAMETERS 0.5

0 19.945 20 20.055
0 200 400 600 800 1000
Frequency (Hz) Time (ms)
Controller parameters Parameter specification
PI control Kp =1.8
Ki =20 (c) (d)
SMC parameters Gs = β=1
K1 =82 Fig. 9. Simulation waveforms illustrating performance of SMC in terms
K2 =3.34 change in output reference, %THD, and dead-zone (a) Input current response
K3 =2.79 and output voltage response to change in reference (b) Comparative analysis
of dead-zone at cross-over of input current during reduced load condition (c)
Harmonic spectrum of input current illustrating %THD (d) Close view of
dead-zone under current-controlled SMC
Source Voltage
Source Voltage

200 200
(volt)
(volt)

0 0

-200 -200

0 0.02 0.04 0.06 0.08 0.1

the steady-state response and transient-state response in terms
0 0.2 0.4 0.6 0.8 1
Time (sec) Time (sec) of sinusoidal input current, regulated output voltage are well
4
illustrated in Fig. 8. Additionally, the performance of the
Source Current

Source Current

10
2
proposed system under different external references and under
(amp)

(amp)

0 0
-2
-10
light loading as well as the harmonic distortion level of the
-4
0 0.2 0.4 0.6 0.8 1 0 0.0323
0.025 0.06 0.1 input current is described in Fig. 9. Besides, the proposed
Time (sec)
510
Time (sec)
system performances with respect to change in load and input
Output Voltage

Output Voltage

400 400 voltage are graphically described in Fig. 10.

(volt)
(volt)

200 200
A simulation period of one second (1s) is taken to obtain
the steady-state response by keeping both the load and external
0 0
0 0.2 0.4 0.6
Time (sec)
0.8 1 0 0.0323
0.025 0.06
Time (sec)
0.1 reference as constant. And the corresponding waveform is
presented in Fig. 8(a). Furthermore, the waveform is zoomed
(a) (b) upto a period of 0.1s and the steady state behaviour of source
current and output voltage which is characterised as in Fig.
8(c), where the sinusoidal behaviour of the source current is
Source Current

4 6
Source Current

viewed clearly. The presented waveforms illustrate that the

(amp)

2
0
(amp)

0 source current is sinusoidal and the obtained output voltage

-5
-2
0 0.2 0.4 0.5 0.6 0.8 1
maintains a constant level throughout the period.
-4
0 0.02 0.04 0.06
Time (sec)
0.08 0.1 Time (sec) Similarly, Fig. 8(b) and Fig. 8(d) illustrates the response
510 of source current and output voltage under transient loading
Output Voltage
Output Voltage

400
400 behaviour with constant reference voltage. Within a simulation
(volt)
(volt)

200 200 period of 0.1s, the transient responses of source current and
0 0
0 0.2 0.4 0.5 0.6 0.8 1
output voltage are examined by applying a step load variation
0 0.02 0.04 0.06 0.08 0.1
Time (sec) Time (sec) of +200%, +300% and +400% at 0.025s, 0.0323s and 0.06s
respectively. Subject to the applied load transients, the relevant
(c) (d) waveforms are presented in Fig. 8(b) and the corresponding
dynamic response of source current and output voltage in
Fig. 8. Simulation waveforms of SMC boost PFC converter (a) Steady state
behaviour of input current and output voltage (b) Closed view of dynamic
term of response time and settling time are illustrated in
response of input current and output voltage regulation to the quick change in Table-3 respectively. With reference to Fig. 8c and Table III,
load (c) Zoomed view of steady state behaviour of input current and output the dynamic performance of the proposed controller under
voltage (d) Input current and output voltage response to the change in load frequent and large load disturbances can be analysed very

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2585587, IEEE Journal
of Emerging and Selected Topics in Power Electronics

TABLE IV. P ERFORMANCE PARAMETERS FOR DIFFERENT EXTERNAL

1 REFERENCE VOLTAGE
pf 1

0.8 Vo Steady-

pf
0.8 Ii Vo
Duration Vref steady- state
0.6
Avg. Avg. pf
85 100 140 180 220 245
0.6 (s) (V) state error
15 25 50 70 100 120 150 (A) (V)
Input Voltage (volt) Load (%) (V) (%)
0-0.04 400 390 2.5 2.05 409 0.999
0.04-0.06 420 409 2.61 3.25 408 0.998
(a) (b) 0.06-0.1 400 390 2.5 2.05 404 0.999

Dead-Zone (ms)
4
0.1
THD (%)

3
2 current and comparative analysis of proposed controller in
0.05
1 term of dead-zone. The spectrum analysis presented in Fig.
0
15 25 50 70 100 120 150
0
5 10 20 10 60 80 100 120
9(c) entails that the %THD is 2.40%, within the tolerable
Load (%) Load (%) standard concerned to PFC topology. Fig. 9(b) describes about
the superiority of performance of the proposed controller
(c) (d) concerned to dead-zone at cross-over of input current during
light load condition. This is closely analysed in Fig. 9(d),
Fig. 10. Graphical representation of system performances under change in
input voltage and change in load (a) Input power factor vs Source voltage which illustrates that the dead-zone is significantly limited and
(RMS) (b) Input power factor vs Load change (c) %THD vs Load change does not affect the system in term of cross-over distortion.
(d) Dead-zone vs Load change Variation of performance parameters like power factor,
%THD and dead-zone at crossover of input current as a
function of load disturbances are depicted by the performance
closely. The quick response of source current and output curves presented in Fig. 10. Also, the behaviour of input power
voltage to that of the frequent and large load disturbances factor with respect to changes in input voltage (85VRM S to
entails about the robustness of the proposed system. Again, 235VRM S ) is analysed in Fig. 10(a), which illustrates that the
for a simulation period of 1s, an incremental step load change proposed scheme operates at almost UPF for wide range of
of 200% is applied at 0.5s to the proposed system and the input voltage. For a wider range of load variation, the system
performance of the system is verified as result presented in maintains almost UPF with the tolerate level of input current
Fig. 8(d). Moreover, tight voltage regulation and sinusoidal harmonics, as waveforms Fig. 10(b) and Fig. 10(c) illustrate.
input current shaping are ensured under current-controlled Also, negligible dead-zone at crossover of source current under
SM control algorithm, even operating on frequent load distur- light loading condition is observed, as illustrated in Fig. 10(d).
bances. The waveforms reveal that the output voltage quickly
attains the desired voltage level during load disturbances. This
explores the performance of formulated SM control function V. E XPERIMENTAL S TUDY
for the desired boost PFC converter. The proposed SM control scheme for boost PFC converter is
TABLE III. P ERFORMANCE PARAMETERS FOR DIFFERENT LOAD experimentally verified in the laboratory. The block diagram
BEHAVIOUR presented in Fig. 11 describes about the implementation of
proposed system which includes mainly a power circuit and a
control circuit. The power circuit incorporates a 1 − φ auto-
Load Step
Response
Settling transformer, a 1 − φ diode bridge rectifier followed by a boost
Ii time of Vo
transient Duration load
peak source Avg.
time of
pf
converter and DC load. Real-Time Interface (RTI) feature of
instant (s) change Vo dSPACE 1104 and MATLAB/Simulink are used to implement
(A) current (V)
(s) (%) (ms)
(ms) the proposed SM control scheme. And to process the control
0 0-0.025 100 3.25 0 413 7.55 0.999
0.025 0.025-0.0323 200 6.45 0 376 4.11 0.999
algorithm on boost PFC prototype, the RTI feature is enabled.
0.0323 0.0323-0.06 300 9.65 0 387 4.018 0.998 Further, the Analog to Digital Converters (ADCs) are used to
0.06 0.06-0.1 400 12.9 0 389 4.017 0.99 sense the voltages and current for feedback purpose. And the
essential driving pulse is generated by the master bit I/O.
Keeping the load at a fixed level, the dynamic response of For designing of experimental prototype same design pa-
input current and output voltage to that of the change in output rameter values are considered which are taken for simulation
reference is illustrated in Fig. 9(a). Within a simulation period modelling. The hardware implementation of the proposed SM
of 0.1s, the outer reference is changed to 420V for a duration current control scheme is displayed in Fig. 14. The high-speed
from 0.4s to 0.6s and remaining duration the reference is 400V. multivariable digital control signal processor board, DS1104
The figure reveals that the load voltage is mutually coordinated is plugged PIC slot of the PC. To sense the inductor current,
to the change in reference under the proposed control scheme. capacitor current and the output voltage signals Hall Effect
However, a small steady-state error is observed as presented current and voltage sensors are arranged in the experimental
in Table IV. Additionally, the presented characteristic confirms set up. These signals are acting as feedback to the controller
the UPF behaviour of the proposed system at different external and are given through the ADC channels of the dSPACE. For
references. the signal conditioning these signals are rescaled to reduce
Furthermore, Fig. 9 reveals about the %THD of source before given as feedback. The proposed SM current controller

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2585587, IEEE Journal
of Emerging and Selected Topics in Power Electronics

POWER
reference variation; when the PFC system is operated under
Auto-
Transformer CIRCUIT
Load
the proposed SM current control algorithm. Along with, UPF
Boost
Rectifier Boost
inductor diode operation at the line side and tight output voltage regulation
1-F Power are remarked from the result waveforms. The output voltage

Capacitor
Supply

O/P
waveforms presented in Fig. 12(a) infers that the converter
MOSFET
gets back its desired output voltage within 4-6ms for 100%
step increase in load. Here, 300 load resistance is considered
CONTROL Current Controlled
as 100% load. The dynamic response of input current to
DC
voltage sensors
Current
sensor
CIRCUIT SM Control
Scheme for Boost
that of load change is well revealed in Fig. 12(a) and Table
vg vo iL iC u PFC System
III. Furthermore, input current response and output voltage
PWM ADC DAC
Digital I/O
Bits Generator
4 ch. 16-bit
4 ch. 12-bit 8 ch. 16-bit response to that of external reference voltage variation is
TMS320F240 DSP
clearly inferred in Fig. 12(b) and Table IV. The dotted marked
24-bit I/O Bus
arrows pointed in experimental waveforms entails about the
enhanced dynamic performances of proposed SMC scheme.

Host PC
Serial Incremental Controller
Interface Encoder Algorithm
Power PC
PCI
Interface
It is inferred from the experimental result waveforms that the
dSPACE DS1104 Controller Board
603e input current attains its desired sinusoidal shape very quickly at
Real-Time Interface
the particular instance of any disturbances in terms of change
in load or change in external output reference.
The study of pf, %THD of source current with harmonic
Fig. 11. Block diagram describing implementation of proposed current- spectrums and power consumption relevant to both closed-loop
controlled SM scheme for boost PFC operation
control and open-loop control are illustrated in Fig. 13. The re-
sults are captured by the help of YOKOGAWA WT500 power
Input Voltage (100V/div) Input Voltage (100V/div) analyser preceded to the hardware prototype. The closed-loop
Input Current (5A/div) Input Current (5A/div)
control using proposed controller administers the shape of
source current to track the sinusoidal shaping of source voltage
more efficiently which is furthermore evidenced by observing
the harmonic spectrum of input current, presented in Fig.
13. The source current THD is within 5%. Simultaneously,
time : 0.01s/div time : 0.01s/div power factor is preserved around 0.99 regardless of the load
Output Voltage (100V/div) Output Voltage (100V/div)
alternation and concurrently, the output voltage is upheld at
390 V/DC for any load which confirmations the effectiveness
of the SM current control algorithm.

VI. DISCUSSION
time : 0.01s/div time : 0.01s/div
It is recommended to build a SM current controller-based
single-stage boost converter in modular system to obtain PFC
(a) (b)

Fig. 12. Experimental waveforms of SMC boost PFC converter (a) Input
current response and output voltage response to change in load, Input voltage:
100V/div, input current: 5A/div, output voltage: 100V/div, time: 0.01s/div
(b) Input current response and output voltage response to change in output
reference, Input voltage: 150V/div, input current: 2A/div, output voltage:
100V/div, time: 0.01s/div

Ithd1 Ithd1
76.835 % 4.853 %
is modelled in MATLAB/Simulink and downloaded to the
dSPACE, which delivers the required regulating signals to the
driver section. In this work, ferrite core type inductor and
plain polyester type inductor capacitor are used. Also, power
MOSFET IRF540N and IN 4007 are used as a switch and
diode respectively. Driver IR 2110 is used to drive the power
MOSFET. Sensor LEM LA 55-P and sensor LEM LV 25-P
are used as current and voltage transducer respectively. For
the sensing of feedback signals a measured resistance of 150
(a) (b)
and an input resistance for voltage sensor of 56k are connected
to the corresponding transducer. Fig. 13. Power analyzer results illustrating power consumption, input power
The source current waveforms presented in Fig. 12 reveals factor and %THD with harmonics spectrum (a) Boost PFC with Open-loop
its inherent sinusoidal characteristic under load transient and control (without proposed controller) (b) Boost PFC with proposed SMC

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2585587, IEEE Journal
of Emerging and Selected Topics in Power Electronics

10

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power factor corrector,” IEEE Transactions on Power Electronics, National Institute of Technology Rourkela, Rourkela,
vol. 52, pp. 638–643, 2013. India, in 2014, where he is currently working toward
[32] S.-C. Tan, Y.-M. Lai, and C. K. Tse, Sliding Mode Control of Switching the Ph.D. degree.
Power Converters, Techniques and Implementation, 2nd ed. Boca
Raton London New York: CRC Press, Taylor and Francis Group, 2011.
[33] J. B. Cao and B. G. Cao, “Fuzzy-logic-based sliding-mode controller
design for position-sensorless electric vehicle,” IEEE Transactions on
Power Electronics, vol. 24, no. 10, pp. 2368–2378, Oct 2009.
[34] S.-C. Tan, Y. M. Lai, C. K. Tse, and M. K. H. Cheung, “A fixed-
frequency pulsewidth modulation based quasi-sliding-mode controller
for buck converters,” IEEE Transactions on Power Electronics, vol. 20, Anup Kumar Panda received the B.Tech in Elec-
no. 6, pp. 1379–1392, Nov 2005. trical Engineering from Sambalpur University, India,
[35] S. C. Tan, Y. M. Lai, C. K. Tse, L. Martinez-Salamero, and C. K. Wu, M.Tech in Power Electronics and Drives from In-
“A fast-response sliding-mode controller for boost-type converters with dian Institute of Technology, Kharagpur, India and
a wide range of operating conditions,” IEEE Transactions on Industrial Ph.D.from Utkal University in 1987, 1993 and 2001
Electronics, vol. 54, no. 6, pp. 3276–3286, Dec 2007. respectively. In 1990 he joined as a lecturer in
IGIT, Sarang, served there for eleven years and
[36] M. G. Umamaheswari, G. Uma, and K. M. Vijayalakshmi, “Analysis then in January 2001 joined National Institute of
and design of reduced-order sliding-mode controller for three-phase Technology, Rourkela as an Assistant Professor and
power factor correction using cuk rectifiers,” IET Power Electronics, currently continuing as a Professor in the Depart-
vol. 6, no. 5, pp. 935–945, May 2013. ment of Electrical Engineering, National Institute of
[37] F. A. Himmelstoss, J. W. Kolar, and F. C. Zach, “Analysis of a smith- Technology Rourkela. He has published over hundred articles in journals and
predictor-based-control concept eliminating the right-half plane zero of conferences. He has completed two MHRD projects and one NaMPET project.
continuous mode boost and buck-boost dc/dc converters,” in Industrial Guided seven Ph.D. scholars and presently guiding ten scholars in the area of
Electronics, Control and Instrumentation, 1991. Proceedings. IECON Power Electronics and Drives. He is a Fellow of Institute of Engineering and
’91., 1991 International Conference on, Oct 1991, pp. 423–428 vol.1. Technology UK, Insttitute of Engineers India and Institute of Electronics and
[38] R. Ridley, Current mode or voltage mode?, Switching Power Magazine, Telecommunication Engineering. He is also a senior member of IEEE USA.
Oct 2000. His research interest includes Design of high frequency power conversion
circuits and Applications of Soft Computing Techniques, improvement in
[39] R. Mammano, Switching power supply topology: voltage mode vs. Multilevel Converter Topology, Power Factor Improvement, Power quality
current mode, Unitrode Design Note, Jun 1994. Improvement in power system and Electric drives.
[40] P. Mattavelli, L. Rossetto, G. Spiazzi, and P. Tenti, “General-purpose
sliding-mode controller for dc/dc converter applications,” in Power

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