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P4 Language: Other Concerns

The document discusses several technologies related to programmable networking including P4, Netronome SmartNICs, Barefoot Tofino switches, and Cisco's approach to disaggregated programmable switching. It provides details on P4 support and capabilities of these technologies.

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65 views17 pages

P4 Language: Other Concerns

The document discusses several technologies related to programmable networking including P4, Netronome SmartNICs, Barefoot Tofino switches, and Cisco's approach to disaggregated programmable switching. It provides details on P4 support and capabilities of these technologies.

Uploaded by

thanh liêm lê
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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P4

Language
Other Concerns
P4.org Members
100G In-band Telemetry With NP4 – FPGA
• INT: Real-time reporting of network
status
• P4: Enabling Truly Programmable
Network Dataplane
• Netcope - Read whitepaper on In-
band Network Telemetry on 100G
with P4
Xilinx P4-SDNet

P4-NetFPGA Hands-on Labs Xilinx P4-SDNet


NetFPGA
Netronome SmartnNIC and Xilinx NetFPGA
Netronome - Agilio™ CX SmartNIC Family
• Optimized for standard server based cloud data centers
• Low profile half length PCIe form factor, power < 25W
• Based on Netronome’s Network Flow Processor 4xxx silicon (72 cores
x 8 threads each)
• 2GB DRAM for lookup tables / state tables (millions of entries)
Netronome - Agilio™ LX SmartNIC Family
• Optimized for higher throughput requirements - middlebox, gateway, appliance,
service node…
• Full height half length PCIe form factor
• Based on Netronome’s Network Flow Processor 6xxx silicon (120 cores x 8
threads)
• Memory: 8GB of DDR3 DRAM @ 1866Mhz w/ECC
• Dual PCIe Gen3x8
Netronome - P4 Tool Chain Components
Netronome - P4 Telemetry
Netronome - P4/C Stateful Firewall
Barefoot - Programmable Data Plane at Terabit
Speeds - 6.5Tb/s TofinoTM
• State of the art design
• Single Shared Packet Buffer
• TSMC 16nm FinFET+
• Four Match+Action Pipelines
• Fully programmable PISA Embodiment
• All compiled programs run at line-rate.
• Up to 1.3 million IPv4 routes
• Port Configurations
• 65 x 100GE/40GE
• 130 x 50GE
• 260 x 25GE/10GE
• CPU Interfaces
• PCIe: Gen3 x4/x2/x1
• Dedicated 100GE port
How Tofino Supports Parallel Processing
• Multiple tables mean multiple parallel lookups
• All actions from all active tables are combined
• More Info
Cisco – Disaggregated Programmable Switching
Case for Disaggregation
Mellanox - Future P4 use in SAI - flexibility
open-nfp
• Portal for research in data plane acceleration, 40+ organizations
• PS/SDK, Lots of P4 code at https://github.com/open-nfpsw

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