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Verilog HDL Moore & Mealy FSM Design

The document describes an experiment to design Moore and Mealy finite state machines (FSMs) in Verilog HDL. It defines Moore and Mealy FSMs, with Moore FSMs having outputs depend on current states and Mealy FSMs having outputs depend on current inputs and states. The experiment involves coding Moore and Mealy FSM examples, simulating their behavior, and analyzing area usage. Results show the FSM designs were implemented correctly and simulated properly, with the Mealy FSM using less area than the Moore FSM.

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122 views8 pages

Verilog HDL Moore & Mealy FSM Design

The document describes an experiment to design Moore and Mealy finite state machines (FSMs) in Verilog HDL. It defines Moore and Mealy FSMs, with Moore FSMs having outputs depend on current states and Mealy FSMs having outputs depend on current inputs and states. The experiment involves coding Moore and Mealy FSM examples, simulating their behavior, and analyzing area usage. Results show the FSM designs were implemented correctly and simulated properly, with the Mealy FSM using less area than the Moore FSM.

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uday
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Experiment 12

Aim: - Verilog HDL Design examples of Moore machine and Mealy machine.
Important Concepts/Theory: -
Finite State Machine:
A Finite State Machine is an abstract mathematical model of a sequential logic function. It
has finite inputs, outputs and number of states. FSMs are implemented in real-life circuits
through the use of flip flops
The finite state machines are classified into two types such as Mealy state
machine and Moore state machine
1. Mealy State Machine:
When the outputs depend on the current inputs as well as states, then the FSM can be named
to be a mealy state machine. The following diagram is the mealy state machine block
diagram. The mealy state machine block diagram consists of two parts namely combinational
logic as well as memory.

Figure
Fig.11:Block
Blockdiagram of
diagram ofMealy
Mealystate
state Figure
Fig.22:
State diagram of
State Mealy
diagram of state
Mealy state
machine machine machine machine

The memory in the machine can be used to provide some of the previous outputs as
combinational logic inputs. So, based on the present inputs and present states, the Mealy
state machine produces outputs. Therefore, the outputs will be valid only at positive or
negative transition of the clock signal. In the above figure, there are three states, namely A, B
& C. These states are labelled inside the circles & each circle corresponds to one state.
Transitions between these states are represented with directed lines. Here, 0 / 0, 1 / 0 & 1 / 1
denotes input / output. In the above figure, there are two transitions from each state based on
the value of input, x. The number of states required in Mealy state machine is less than or
equal to the number of states required in Moore state machine.

2. Moore State Machine:


When the outputs depend on current states then the FSM can be named as Moore state
machine. The block diagram of Moore state machine is shown in the following figure. As
shown in figure, there are two parts present in Moore state machine. Those are combinational
logic and memory. In this case, the present inputs and present states determine the next states.
So, based on next states, Moore state machine produces the outputs. Therefore, the outputs
will be valid only after transition of the state.
Fig. 3: Block diagram of Mealy state machine
Design Analysis: Fig. 4: State diagram of Moore state machine

Codes:

1. Mealy FSM:

2. Moore FSM:
Results/Discussion: -

Simulation (Waveform):

1. Mealy FSM: -

Fig. 5: Mealy FSM simulation

2. Moore FSM: -

Fig. 6: Moore FSM simulation

Report Results: -
RTL Schematic: -

1. Mealy FSM: -

Fig. 7: Mealy FSM

2. Moore FSM: -

Fig. 8: Moore FSM

Tech Schematic: -
1. Mealy FSM: -

2. Moore FSM: - Fig. 9: Mealy FSM


Fig. 10: Moore FSM

Area Report: -

1. Mealy FSM: -

2. Moore FSM: - Fig. 11: Mealy FSM Area Report


Fig. 12: Mealy FSM Area Report

Conclusion:
Verilog HDL code for mealy and moore FSM has been implemented and their simulation
with signals has been tested.
Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6

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