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Fun Work (Bonus Points - Group Assignment) : GM GM

1. The small research group designed a new operational amplifier requiring 0.25mm2 of area in a CMOS process node below 350nm. 2. After reviewing pricing from three chip brokers (MOSIS, CMP France, Euro Practice), the 65nm process from ST Microelectronics was determined to be most cost effective for a minimum order of their design. 3. Packaging the operational amplifier in a QFN package was selected due to its low pin count, heat dissipation, speed, and cost effectiveness. The total estimated cost for prototyping 3 dozen chips including foundry processing and packaging is approximately 5500 Euros.

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uzair ahmad
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49 views2 pages

Fun Work (Bonus Points - Group Assignment) : GM GM

1. The small research group designed a new operational amplifier requiring 0.25mm2 of area in a CMOS process node below 350nm. 2. After reviewing pricing from three chip brokers (MOSIS, CMP France, Euro Practice), the 65nm process from ST Microelectronics was determined to be most cost effective for a minimum order of their design. 3. Packaging the operational amplifier in a QFN package was selected due to its low pin count, heat dissipation, speed, and cost effectiveness. The total estimated cost for prototyping 3 dozen chips including foundry processing and packaging is approximately 5500 Euros.

Uploaded by

uzair ahmad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Fun Work (Bonus Points – Group Assignment)

Q2: In the university we do the manufacturing through chip brokers. MOSIS, CMP France, and Euro Practice
are three well-known brokers. Here is the Problem, you are a small research group in the company and you have
designed a new kind of the operational amplifier such has the better GBW product and noise performance
compared to all the existing designs.
You want to manufacture few dozen ICs to test your design. Since this is an op-amp and ft of all the
technologies nodes below 350 nm are enough to support this design. You need the ¼ mm 2 of the area for this
CMOS opamp.
 Please go through the above three websites and find out that what is the most low cost CMOS technology
node to test this circuit. Please be careful about the minimum area you can order.
 What type of the package you will select for this operational amplifier and why? Please also add the cost of
10 packaged dies.
 Calculate the total cost you need to tapeout the designed opamp?

{Learning Outcome: Types and Details of the Technologies uses and different coding attached to the process}

Per opamp will require 0.25mm2 .So, for prototying and will be delivered 40 pieces

Foundary Price Minmum area Packaging CostGrand Total


(Euro) (Euro)
Price for Area ≤ Minimum Cost 4500+750=5250
CMP ST Microelectronics ST 65nm 4,500 3 22,500+
5mm2 with minimum
[(Area-5) x 250 + (10 x 49)
CMOS065 charge of 1.25mm2
3,750] 6 including seal-ring. = 740
~1 million pkr

For simplicity I am using 65nm process.


Package:
 As in opamp the pin count is low that why QFN is a preferable packaging for IC’s.
 QFN is also better for heat due to its metal contacts.
 Speed is also a prominent factor in opamp and QFN packaging can handle the speed we require.
 QFN is very cost effective and reliable for long use.
 It is available in Surface Mount topology.
Total Cost:
Approximately 5500 Euros including shipping cost for 3 dozen IC’s

Q3: We will use the 65nm CMOS from TSMC for your future tape out? What is the ft and fmax of the 65nm
CMOS and what is the Vdd value? Also what is the gm of the minimum size transistor for certain Id.

TSMC 65nm process parameters

Vdd rated =1.2V

gmn= 0.93mA/v for Id=1mA, kn=440uA/V for 65nmos

gmp= 0.53uA/v for Id=1mA, kp=140uA/V for 65nmos


ft =360GHZ fmax=420GHZ

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