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HW1 Sol

- The document is the solution to homework problems for a digital integrated circuit design course. - Problem 1 involves calculating drain junction capacitances for an NMOS transistor given physical parameters when the voltage changes. - Problem 2 calculates the drain current of a CMOS inverter given transistor bias configurations and parameters. - Problem 3 examines how energy-delay product scales with technology assuming supply voltage and dimensions scale by factors alpha and beta. - Problem 4 analyzes how the ratio of metal-to-metal coupling capacitance to metal-to-ground capacitance scales for three parallel wires when dimensions scale. - Problem 5 uses the Elmore delay model to calculate the propagation delay of a signal through a

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uzair ahmad
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108 views4 pages

HW1 Sol

- The document is the solution to homework problems for a digital integrated circuit design course. - Problem 1 involves calculating drain junction capacitances for an NMOS transistor given physical parameters when the voltage changes. - Problem 2 calculates the drain current of a CMOS inverter given transistor bias configurations and parameters. - Problem 3 examines how energy-delay product scales with technology assuming supply voltage and dimensions scale by factors alpha and beta. - Problem 4 analyzes how the ratio of metal-to-metal coupling capacitance to metal-to-ground capacitance scales for three parallel wires when dimensions scale. - Problem 5 uses the Elmore delay model to calculate the propagation delay of a signal through a

Uploaded by

uzair ahmad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE537- Spring 2020

Digital Integrated Circuit Design


Instructor: Dr. Nasir Mohyuddin
Homework # 1 Solution

Due Date: 24/02/2020 at the beginning of the class

Problem 1
An NMOS transistor is fabricated with the following physical parameters:
NA(substrate)=1016cm-3, NA+(channel stop)=1019cm-3, ND=1020cm-3, W=10m, L=1.5m,
Y=5m, LD=0.25m, Xj=0.5m. Determine the drain junction capacitances when VDB
changes from 5V to 2V and the grading coefficient of the junctions m=0.5.
Problem 2
Determine the drain current of a CMOS inverter for the biasing configuration given below.
VGS VDS
NMOS 2.5 V 3.5 V
Assume that long-channel MOSFET model is valid for these devices. Use the following
transistor bias data, assuming VDD=5 V and VSB is 0:
NMOS PMOS
2
k 115A/V 30A/V2
VT,0 0.45V -0.40V
 0.05 V-1
-0.10 V-1

Solution
The “drain current” here means the current of the NMOS transistor. Notice that the NMOS
transistor is in saturation region, because
VDS=3.5≥VGS-VT,0=2.5-0.45
so,
ID = Kn/2 (VGS – Vth)2 (1 + VDS)
= 115/2 (2.5 – 0.45)2 (1 + 0.05(3.5)) = 283.93 

Problem 3
How does the Energy-Delay product scale with the CMOS process technology, assuming
a generalized scaling procedure whereby the supply voltage is scaled down by a factor α
whereas all horizontal and vertical dimensions are scaled down by a factor β. Ignore the
effect of interconnect capacitances.

Solution
Energy V  I  Delay
1
Vnew  Vold

Cox W 
I  kn / 2 (VGS  Vth ) 2  (VGS  Vth ) 2  I new  I old
2 L 2
CL new  WLCox new   Cox W L   1 CL old
   old 
 C V   C /  V /   
Delay   L    L   Delaynew 
 Delayold
 I  new   /  I old 2
2
1    1
Energy new     Energyold 
 Energyold
     2
2 2

Energy  Delay new  1 3  Energy  Delay old



Problem 4
Consider the configuration of three metal1 wires situated above an infinite ground plane.
The three wires are running adjacent to each other and going into the page. Use a parallel–
plate capacitance to model describing metal-to-ground capacitance including both area and
fringe capacitances, Cground, and the metal-to-metal coupling capacitances, Ccouple. Suppose
as a result of technology scaling, H, S and W dimensions are scaled down by a factor,  ,
Ccouple
whereas T is scaled down by  . In addition     1 . Precisely describe how
C ground
of the middle line scales. Does it increase or decrease?

S W
Ccouple/2
T
Ccouple/2 Cground H

Solution:

First note that,


TL
Ccouple 
 S  HT
C ground W L SW .

H
Now after scaling the ratio will be
HT
Ccouple new  HT 
new
 
   
C ground  SW  SW  .
2
The ratio of coupling capacitance to ground capacitance obviously increases.

Problem 5
A polysilicon interconnect that is 200μm long and 1μm wide is driving 3 uniformly spaced
capacitive loads as shown in the figure below. Using the Elmore delay model, calculate the
propagation delay of a signal from point A to point B in this interconnect bus. The
polysilicon resistivity is 10 Ω/square and its capacitance to ground is 150fF/mm. Model
each interconnect segment with a RC section ( not RC-π).
A B

50fF 100fF
1 20fF

200u
R R R

C1 C2
200
m
R 3 10 / square  666
1 m
C  150 fF / mm  200 / 3 m  10 fF
C1=10fF+20fF=30fF
C2=10fF+50fF=60fF
C3=10fF+100fF=110fF
Elmore Delay=0.69(R.C1+2R.C2+3R.C3)=0.69666(30+120+330)fsec=220.58psec

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