Proc.

of the 1st International Conference on Electrical, Communication and Computer Engineering (ICECCE)
24-25 July 2019, Swat, Pakistan

A High Gain Amplifier Design for Neural Signal

Acquisition
Usman Zafar Zehra Haider
Sana Moin
Department of Electronics Engineering Department of Electronics Engineering
Department of Electronics Engineering
NED University NED University
NED University
Karachi, Pakisatn Karachi, Pakisatn
Karachi, Pakisatn
usmanzafar82@gmail.com zehrahaider117@gmail.com
sana_ned@hotmail.com
Anum Khan Hashim Raza Khan
Saman Khan
Department of Electronics Engineering Department of Electronics Engineering
Department of Electronics Engineering
NED University NED University
NED University
Karachi, Pakisatn Karachi, Pakisatn
Karachi, Pakisatn
anumkhan083@yahoo.com hashim@neduet.edu.pk
saman.khan2412@gmail.com

Abstract—This paper delineates a simulated neural signal and a very high gain for the desired range of frequency. When
amplifier with a very high gain and enhanced supply rejection the electrode interacts with the tissue, an electrochemical
along with low noise operation. We describe a micro-power phenomena takes place and hence as a consequence DC offset
complementary metal-oxide-semiconductor (CMOS) design. of 1–2 V (offset amplitude that is larger than the amplitude of
The amplifier comprises of two stages and at the input juncture, neural signal) is produced and is usually added into the
the differential pair is used to attain an optimum input-referred informative brain signals and hence should be nullified by
noise. The amplifier is outlined in a typical 180–nm CMOS filtering high-pass signals at very low cutoff frequencies. In
process using cadence tool. The design yields a midband gain of this neural signal amplifier, we use off-chip capacitors to
70.0 dB with an input-referred noise of 4.33 μVrms and
evacuate dc offsets with large amplitude and to pass
frequency from 320 mHz to 9.0 kHz is selected as – 3 dB
bandwidth while it consumes 6.16 μW from a 1.8 V supply,
significant low frequency LFP signals. The high cutoff
resulting in a noise efficiency factor of 3.25. The power supply frequency has been set by the use of compensation capacitor.
rejection ratio of 133.5 dB has been recorded in the passband. This paper demonstrates a two stage neural signal front-
end amplifier to provide high gain over the bandwidth which
Keywords—neural signal amplifier, high gain, power supply includes the complete electrical activity of the brain and
rejection ratio (PSRR), input-referred noise, micro-power, noise rejects the undesired frequency components outside this band.
efficiency factor (NEF). The proposed design also achieves a good power noise trade
off along with high power supply rejection ratio (PSRR). This
I. INTRODUCTION
paper is arranged as follows. Section II demonstrates the
Electroencephalogram examinations are prone to the complete working of the design. Section III presents the noise
commotion and interferences that may veil the brain signals efficiency factor (NEF) computation. Section IV displays the
and may result in a wrong medicinal assessment. The simulated outcomes. At last this paper is concluded through
investigation of very confined neural actions require a refined Section V.
electronic hardware for precisely amplifying the recognized
signals, beside microelectrodes. Such systems are used in the
II. OVERALL AMPLIFIER DESIGN
treatment of disabilities such as paralysis, epilepsy and
parkinson disease [1], [2]. A portion of the difficulties in the Figure 1 illustrates the complete design of the proposed
plan of analog front-end circuits for monitoring and recording neural signal amplifier, comprises of two stage CMOS
the electrical movement of neural signs are related to the topology [6]. The main characteristic for the neural signal
characteristics of the neural signals. front-end amplifier is to produce the gain for the appropriate
neural signal frequencies. A bias current Ibias is generated
The extracellular neural action potentials (APs), or spikes, using transistors M8 and M9 and the power consumption of
have amplitudes up to 500 μV typically, with frequency in the such biasing circuit is excluded generally in power
range of 100 Hz–7 kHz band [3], while neural electrical measurement [7], [14] since all the front-end neural signal
activities having amplitudes up to 5 mV with frequencies amplifier placed closer to their respective electrode can share
underneath 1 Hz are known as local field potentials (LFPs) the generated voltage. The differential pair M1 and M2
[4]. Reasonably, the input referred noise of the amplifier ought constitutes the input stage, which is a low noise amplifier. The
to be between 5–10 μVrms [5] to cancel out the effect of noise current source formed by M5 and M10 is used to bias the
at the sensing site. An inverse relation exists between the differential pair. The W/L ratio of M5 and M10 is carefully
squared input referred noise voltage and amplifier power [14], chosen to produce the desired value of bias current for the
this noise and power inverse relation needs special attention input stage and this current is then divides equally between
in the design of brain signal amplifier. External commotion M1 and M2. The fully differential amplifier is used at the first
signals can effectively influence the low intensity neural stage as they have a higher common mode rejection ratio
signals, so it is extremely important that at the monitoring site (CMRR) and power supply rejection ratio (PSRR) than single-
in the neural recording system, for example an analog input ended. The differential pair placed at the input is actively
stage ought to be organized to have a low input-referred noise loaded with the current mirror created by M3 and M4. For a

978-1-7281-3825-1/19/$31.00 ©2019 IEEE

 TABLE I. DEVICE PARAMETERS AND OPERATING POINT OF NEURAL
SIGNAL AMPLIFIER

Devices W/L (μm) ID (μA) Operating Region

M1, M2 800.0/1.0 0.94 Subthreshold
M3, M4 100.0/50.0 0.94 Saturation
M5, M10 0.3/0.2 1.87 Saturation
M6 3.2/0.2 1.55 Subthreshold
M7 0.3/0.2 1.55 Saturation
M8, M9 0.3/0.2 1.90 Saturation
M11 1/0.2 1.55 Saturation

Equation (1) is used to calculate NEF. Where Vni,rms is the

total input-referred rms noise voltage, Itot is the total amplifier
supply current, k is the Boltzmann’s constant, T is the absolute
temperature, UT is the thermal voltage, and BW is the −3 dB
bandwidth of the amplifier. The offered design provides much
Fig. 1. Overall schematic of neural amplifier high gain and PSRR than any other design presented till date.
The power consumption and NEF of the simulated circuit are
low-noise and low-frequency circuit the flicker noise is a also adequate.
critical matter of concern as flicker noise has inverse
dependence on frequency [7]. We have diminished the IV. SIMULATED RESULTS
inclusion of flicker noise by utilizing PMOS transistors M1
and M2 as PMOS transistor typically produces the low flicker Figure 1 displays the complete schematic of the offered
noise than the flicker noise in NMOS [8]. In our circuit, we neural amplifier, which is outlined utilizing 180–nm CMOS
have selected input devices M1 and M2 with large gate area process. The amplifier is operated by 1.8V supply, which
by considering the inverse relation between flicker noise and provides a total 3.42 μA current. This total current is
interface area [7]. In the second gain stage, the current source distributed as follows: The first stage consumes 1.87 μA and
transistors M7 and M11 together work as an active load for the second stage consumes 1.55 μA. Ibias in Figure 1 is set to
the common-source transistor M6. A compensation capacitor 1.9 μA and as it can be shared by numerous amplifiers in the
CF is placed in the negative feedback path of the second stage. cluster consequently it is excluded in the power measurement.
CF improves the miller effect already present in M6. As CF Figure 2 displays the simulated transfer function of the
introduces a dominant pole in the design and its value is amplifier. The overall midband gain of the amplifier is 70.0
selected in such a way to achieve the desired higher cut-off dB. The first stage gain is 47.1 dB and gain of second stage is
frequency. This negative feedback also enhances the stability 22.9 dB. The −3 dB frequencies are adjusted to be at 0.32 Hz
of our design. Two off chip capacitors C1 and C2 are placed to and 9.0 kHz as appeared in Figure 2 and this bandwidth is
select the preferred lower cutoff frequency. Although the achieved by setting C1= C2=10 μF and CF = 5 fF.
offered design is appropriate to work for the capacitive loads,
the dimensions of all the transistors are carefully selected to Figure 3 demonstrates the input-referred voltage noise
achieve low noise along with better power efficiency. The spectrum of the amplifier. The consolidated input-referred rms
circuit has been simulated in which all the transistors are either noise is 4.33 μVrms, for the frequency ranges from 320 mHz
in saturation or sub-threshold region. to 9.0 kHz. NEF calculated through Equation 1 is found to be
3.25.
The product of the gain of first stage and gain of the second
stage forms the overall transfer function of the amplifier . The
high output resistance of second stage is the output resistance
of the entire circuit. This high output resistance is very much
suitable for driving the capacitive load of this neural signal
amplifier. In our design parameters of all the transistors used
as a core are summarized in the Table I.

III. NOISE EFFICIENCY FACTOR

The Noise efficiency factor (NEF) reported in [13]
measures the performance of an amplifier by finding the
adjustment between noise and power.

2. I
NEF V , 1
4. π. k. T. U . BW
Fig. 2. Transfer function of the proposed amplifier
 TABLE II. PERFORMANCE COMPARSION OF NEURAL AMPLIFIER

Parameters TBioCAS TBioCAS TCAS-I SSCL This

2007[10] 2011[11] 2013[12] 2019[9] Work
Supply voltage (V) 1.8 1.8 1.8 1 1.8
Total Current (µA) 4.7 4.4 6.1 5.5 3.42
Gain (dB) 49.5 39.4 48/60 30/60 70.0
Bandwidth (Hz) 98-9.1k 10-7.2k 1-9k 1-8k 0.32-9.0k
Vni,rms (µVrms) 5.6 3.5 5 2.3/3.4 4.33
NEF 4.9 3.35 4.6 2.2/3.1 3.25
CMRR (dB) 52.7 70.1 48 >70 ≥40
PSRR (dB) 52 63.8 55 >70 ≥133.5
Process (µm) 0.18 0.18 0.18 0.18 0.18

amplifiers.

V. CONCLUSION
In this paper, a design technique for intensifying the electrical
activity of the neurons has been demonstrated. From a 1.8 V
voltage source, the circuit draws a current of 3.42 µA and is
particularly based on two stage CMOS architecture. The
analog front-end stage is a differential amplifier and the
second stage is structured to further amplify the neural
signals. The design has been constructed to reduce the
involvement of noise along with low power consumption.
Our amplifier provides a gain of 70.0 dB with input referred
noise of 4.33 µVrms, consequently has a NEF of 3.25.Our
amplifier offers a high gain and PSRR. The overall design
Fig. 3. Input-referred voltage noise spectrum of the proposed amplifier
strategy is also worthy for comparison in all critical
The CMRR is calculated in order to determine the noise parameters with other neural amplifiers and thus can be very
rejection capability of the input stage of the amplifier and is useful in curing patients with brain related diseases.
computed by dividing the differential gain with the common
mode gain. CMRR ≥ 40 has been set for the presented
amplifier. The PSRR describes the impact of power supply ACKNOWLEDGMENT
variations in the performance of a designed system and is The authors would like to thank Dr. Arsalan Jawed - Professor
determined mathematically by dividing the differential gain to (PAF-Karachi Institute of Economics and Technology,
the gain from the power supply to the output. Figure 4 Karachi, Pakistan) for all the valuable discussions and
demonstrates the simulated PSRR, which is ≥ 133.5 dB in the support.
bandwidth.
In TABLE II, our amplifier design is compared with the REFERENCES
few previously reported neural amplifiers. Our proposed
amplifier exhibits high gain and high PSRR than all other [1] Ivan Osorio, “Epilepsy the intersection of neurosciences, biology,
mathematics, engineering and physics,”CRC Press, Boca Raton, FL,
2011.
[2] T. W. Berger, A. Ahuja, S. H. Courellis, S. A. Deadwyler, G.
Erinjippurath, G. A. Gerhardt, G. Gholmieh, J. J. Granacki, R.
Hampson, M. C. Hsaio, J. Lacoss, V. Z. Marmarelis, P. Nasiatka, V.
Srinivasan, D. Song, A. R. Tanguay, and J. Wills, “Restoring lost
cognitive function: Hippocampalcortical neural prostheses,” IEEE
Eng. Med. Biol. Mag., vol. 24, pp. 30–44, Sep./Oct. 2005.
[3] K. Najafi and K. D. Wise, “An implantable multielectrode array with
on-chip signal processing,” IEEE J. Solid-State Circuits, vol. SC-21,
pp. 1035–1044, Dec. 1986.
[4] A. C. Metting van Rijn, A. Peper, and C. A. Grimbergen, “High-quality
recording of bioelectric events,” Med. Biol. Eng. Comput., vol. 29, pp.
1035–1044, 1986.
[5] K. Guillory and R. A. Normann, “A 100-channel system for real time
detection and storage of extracellular spike waveforms,” J.Neurosci.
Meth., vol. 91, pp. 21–29, 1999.
[6] A.S.Sedra and K.C.Smith, “Microelectronics Circuits”,7th edition,
Oxford University press,2015.
Fig. 4. PSRR calculation of the neural amplifier
[7] Reid R. Harrison, Member and Cameron Charles, “A Low-Power Low- [11] V. Majidzadeh, A. Schmid, and Y. Leblebici, “Energy efficient low-
Noise CMOS Amplifier for Neural Recording Applications.” IEEE noise neural recording amplifier with enhanced noise efficiency
journal of solid-state circuits, vol. 38, no. 6, June 2003. factor,” IEEE Trans. Biomed. Circuits Syst., vol. 5, no. 3, pp. 262–271,
[8] C. Jakobson, I. Bloom, and Y. Nemirovsky, “1/f noise in CMOS Jun. 2011.
transistors for analog applications from subthreshold to saturation,” [12] P. Kmon and P.Grybos, “Energy efficient low-noise multichannel
Solid-State Electron,vol. 42, no. 10, pp. 1807–1817, 1998. neural amplifier in submicron CMOS process,” IEEE Trans.Circuits
[9] Taekwang Jang, Jongyup Lim, Kyojin Choo,Samuel Nason, Jeongsup Syst. I, Reg. Papers, vol. 60, no. 7, pp. 1764–1775, Jul. 2013.
Lee,Sechang Oh,Cynthia Chestek, Dennis Sylvester, and David
Blaauw,“A Noise-Efficient Neural Recording Amplifier Using [13] M. S. J. Steyaert, W. M. C. Sansen, and Z. Chang, “A micropower
Discrete-Time Parametric Amplification,” IEEE Solid-State Circuits lownoise monolithic instrumentation amplifier for medical purposes,”
Letter,vol.1,no.1,Jan 2019. IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 1163–1168, Dec.
1987.
[10] B. Gosselin, M. Sawan, and C. A. Chapman, “A low-power integrated
bioamplifier with active low-frequency suppression,” IEEE Trans. [14] W. Wattanapanitch, M. Fee, and R. Sarpeshkar,“An energy-efficient
Biomed. Circuits Syst., vol. 1, no. 3, pp. 184–192, Sep. 2007. micropower neural recording amplifier,” IEEE Trans.Biomed. Circuits
Syst., vol. 1, no. 2, pp. 136–147, Jun. 2007.