IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 20, NO.

2, APRIL 2005 1157

Algorithms for the Accounting of Multiple

Switching Events in Digital Simulation of
Power-Electronic Systems
M. O. Faruque, Student Member, IEEE, Venkata Dinavahi, Member, IEEE, and Wilsun Xu, Senior Member, IEEE

Abstract—Digital simulation of power systems containing power switching event is not known a priori (since it is controlled by
electronics apparatus is challenging due to the need to account processes external to the simulator) and it seldom coincides
multiple switching events within one simulation time-step. This exactly with thereby creating a switching delay which
paper describes a family of algorithms, with varying levels of
computational complexity, for accounting such switching events produces erroneous simulation results.
in digital simulations. The proposed algorithms are applicable Various techniques are available in literature to deal with
for both off-line and real-time simulations. A comparative study single inter-step switching events in digital simulation under
on their performance such as harmonic content, errors in funda- both off-line and real-time conditions. State-space methods
mental component and simulation time requirement is presented. [4], [5] have been effectively used to simulate thyristor based
A Pulse Width Modulated (PWM) Voltage Source Converter
(VSC) based D-STATCOM system is used as a case study for circuits. Fixed time-step methods based on nodal analysis have
simulations. Simulation results indicate excellent performance been used for traditional power system transient simulation
(accuracy and efficiency) in comparison with a fixed time-step [6], [7] as well as power-electronic circuit simulation [8], [9]
algorithm using a small step-size. under both off-line and real-time conditions. The advantage of
Index Terms—Digital control, discrete event simulation, extrap- such methods is that the admittance matrix of the simulated
olation, interpolation, power electronics. network remains unchanged. Combined with a fixed time-step
nodal method, linear interpolation has proved to be a very
effective technique in estimating the circuit variables at the
I. INTRODUCTION
switching instant. Some of the pioneering research in this area

R EAL-TIME digital simulation of power systems is be-

coming increasingly commonplace for testing of new
FACTS and HVDC controllers and protection systems [1]–[3]
has been reported in [10]–[14]. PSCAD/EMTDC uses a double
interpolation technique to allow correction for switching delays
[15], [16]. Details of this technique is given in Section III.A.1.
before they are commissioned. When a digital controller for Real-time simulator ARENE uses linear interpolation to bring
a power-electronic apparatus such as a unified power-flow the solution to the switching point, however, the interpolated
controller (UPFC) needs to be tested, it is interfaced with a values are used as the value of next time-step so that equal
real-time simulator modeling the UPFC and the surrounding spacing between data points are maintained. An extrapola-
power system into which the UPFC is embedded. The outputs tion is then used to bring back the solution to the original
of the digital controller are predominantly discrete switching time-grid [15]. In [17] a fixed time-step technique is described
signals which are used to control the switches in the UPFC. The in which states are linearly interpolated assuming instantaneous
real-time simulator, solving the system differential equations switching. Then a method for calculating the initial conditions
at a certain discrete time step , is therefore required to following a discontinuity or switching is presented. The algo-
account multiple inter-step switching events which arrive at its rithm is applied using both nodal and state-space approaches.
input between two calculation cycles. The number of switching An interpolation method using instantaneous solution is also
events within any given time-step of the simulator depends on described in [18]. HYPERSIM [19] is a parallel processor based
two factors: 1) the switching frequency of the power-electronic real-time simulator which implements a backward-forward in-
system (i.e., its digital controller sampling rate); and 2) the terpolation technique to simulate switching phenomenon in
complexity of the power-electronic system (i.e., the number of power-electronic simulation. In [20] a structure changing con-
switches in the system). The higher the switching frequency cept is discussed, which can be used to simulate the changes at
or the larger the system, the higher is the number of inter-step arbitrary time instants. Variable time-step nodal methods using
switching events. Furthermore, the timing of an incoming linear interpolation to account for single interstep switching
event have also been reported in [21], [22]. A method based
on re-initialization through interpolation and extrapolation for
Manuscript received December 4, 2003; revised June 15, 2004. This work was treatment of discontinuities in simulating power-electronic
supported in part by the Natural Sciences and Engineering Research Council
(NSERC) of Canada and in part by the University of Alberta. Paper no. TPWRD- circuits has been proposed in [23].
00613-2003. This paper presents algorithms designed to take into account
The authors are with the University of Alberta, Edmonton, AB T6G multiple switching events in digital simulation of power-elec-
2V4, Canada (e-mail: faruque@ece.ualberta.ca; dinavahi@ece.ualberta.ca;
wxu@ece.ualberta.ca). tronic systems employing forced-commutated devices. A full
Digital Object Identifier 10.1109/TPWRD.2004.834672 comparison of the algorithms is presented under both open-loop
0885-8977/$20.00 © 2005 IEEE
1158 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 20, NO. 2, APRIL 2005

In a fixed time-step algorithm, at the beginning of every

time-step the simulator looks for the switching event and
its timing information. With this knowledge it updates the
power-electronic model in the system. Depending on the type
of switches, the circuit variables , for example voltages at
the point of common coupling, may be functions of the firing
signals and/or the network state

(1)

Then, the simulator proceeds to obtain the numerical solution

of the network state equations for the given time-step. The state
Fig. 1. Multiple interstep switching events in digital simulation. equations for a linear time-invariant network can be written in
general as

and closed-loop control operation. The proposed algorithms are (2)

not limited to fixed time-step schemes but also employ variable
time-step schemes along with linear interpolation/extrapolation subject to the initial conditions and ,
where is the network state vector and is
to meet simulation accuracy and efficiency constraints. Sec-
the input vector. and are constant matrices dependent on
tion II briefly describes the fixed time-step approach in digital
simulation and Section III presents the algorithms. Section IV the network constants such as R, L, and C. With a time-step of
describes the test system, a six-pulse PWM D-STATCOM integration , the solution at time can be expressed in terms
of the solution at time
system, and its digital controller. Section V provides results
showing full comparison of the performance of the proposed
algorithms. Section VI presents the conclusions. (3)

where is a variable of integration. Numerical solution of (3)

II. MULTIPLE SWITCHING EVENTS IN FIXED TIME-STEP
can be obtained by approximating the integral in (3) using a
DIGITAL SIMULATION
numerical integration algorithm. Let the subscript denote
When a real-time digital simulator modeling a power-elec- quantities at time and quantities at time . Then
tronic system is interfaced with a digital controller for that
system, the discrete firing pulses coming from the controller are (4)
rarely in synchronism with the time-step chosen for the sim- (4) forms the discrete time solution of (2). The number of history
ulator. Unlike a physical system, the digital simulator cannot terms of and in the integral approximation will depend on
respond instantaneously to a switching event; it can respond the type of the chosen numerical method. A difference equation
only after it has completed its current task (calculating states can be obtained by using the Trapezoidal Rule (assuming the
for thereby creating a switching delay. Furthermore, since integrand to be piecewise linear) on (3)
a switching event does not always come in at the same time
instant the switching delay introduced is not constant; the delay (5)
can range from a fraction of a time-step up to a full time-step.
Fig. 1 illustrates the fixed time-step simulation approach which gives us
with two switching events occurring within one time-step.
represent the states of the system computed (6)
by the simulator at every time step and
where
represent the true states of the physical system.
In the context of the paper, Time-Step refers to the discrete-
time interval with which the system differential equations are (7)
numerically integrated by the simulator; the term step-size is and
used interchangeably with time-step. In contrast, the term Time-
Grid is chosen to represent the interval at which output data (8)
points are generated by the simulator. In Fig. 1 the simulation
time-grid is the same as the time-step . The switching events Recursive solution of (6) starting with will yield the de-
and which occur at times and respectively are ac- sired approximate solution of (3). Equation (6) can be rewritten
counted at time when the real-time simulator has already cal- as
culated and emitted the incorrect state . Real-time operation
does not permit recalling and changing state . The physical (9)
system, on the other hand, would respond to the events with where
states and at times and respectively and would
be the true state of the system at time . (10)
FARUQUE et al.: ALGORITHMS FOR THE ACCOUNTING OF MULTIPLE SWITCHING EVENTS 1159

represents the history of the network since depends on the A. Fixed Time-Grid Algorithms
state and input at the previous time-step. This formulation is Once the exact instant of switching event is detected, these
identical to that of Dommel’s method [6] using trapezoidal rule. algorithms implement post-event corrections. For all the algo-
and can be interpreted as the discrete time equivalent net- rithms, the interpolated variables include the state variables,
work parameters dependent not only on the original network (inductor currents and capacitor voltages) and the inputs (AC
parameters and but also on the time-step . Therefore, system voltages). These variables are interpolated to the point
a change in the time-step would necessitate a recalculation of switching and then the power-electronic converter model (1)
of and . is updated in accordance with the switching changes. The up-
dating procedure depends on the model used to simulate the
switches. Using the switching function models, the switch status
III. ALGORITHMS FOR THE ACCOUNTING OF MULTIPLE
are flipped and the voltage levels are decided.
SWITCHING EVENTS
1) Algorithm I: This algorithm is similar to the Double in-
As shown in Fig. 1, two switching events and arrive in terpolation technique that has been used by PSCAD/EMTDC
the time interval while the simulator computes and [15].
emits state at time . Although, real-time operation does After calculating state , when the simulator has acknowl-
not allow changing state , it does allow the simulator to take edged that two events have arrived in the previous simulation
certain corrective action before proceeding to calculate the next interval at times and , the following steps can be taken to
state at time provided that the simulator has the timing correct the subsequent state calculation:
information of the switching events relative to the simulation 1) Based on states and , state at time is
time-grid. The earliest time at which this information can be linearly interpolated as
made available to the simulator is at the instant an event occurs
(i.e., and , and the latest is at the end of time . The al- (11)
gorithms described in this section can be broadly classified into
two categories). 2) Once the interpolation is performed, the power-elec-
1) Fixed Time-Grid Algorithms: In these algorithms the tronic model (1) is updated according to switching
output data of the simulation is obtained at equal in- event . This will yield which is different from
tervals of time thereby fixing the time-grid. If is .
varied internally, then a re-synchronization is performed 3) State at time is calculated using (6).
to get the simulation back on the original time-grid. 4) Now, based on and , state is interpo-
Therefore, these algorithms can have a fixed or a vari- lated as
able simulation time-step. Algorithms I through VII in
Fig. 2 belong to this category. For the sake of clarity (12)
these algorithms are illustrated with only two switching
events.
5) The power-electronic model (1) is again updated using
2) Variable Time-Grid Algorithms: In these algorithms, the
switching event and state is calculated in accor-
real-time simulator is interrupted in its normal opera-
dance with the switching changes at .
tion at the instant a switching event occurs, effectively
6) State at time is calculated using (6).
varying the external simulation time-grid. However, the
7) The corrected state at time is now interpolated
internal time-step of the simulation is always fixed.
Algorithm VIII belongs to this category. based on states and as
At the beginning of each time-step, the simulator takes one of
the two operational paths based on the information it receives (13)
about any switching events:
1) Normal Operation described in Section II is executed This step puts the simulation on the original time-grid.
in case of no switching event has been detected in the 8) Finally, state is calculated from using (6).
previous time-step. There are 3 interpolations and 3 full-state calculations and
2) In case of one or more switching events in the previous two model updates involved in going from time to time ,
time step, Post-event Correction Operation is executed. with no change in , after the simulator receives the informa-
Depending on the algorithm, correction involves linear tion about the switching events. Step 7 is solely an internal cal-
interpolation, linear extrapolation or a change of time- culation since it is not possible to change in real-time. This
step. The correction variables include the state variables step may be used in off-line simulations to produce more accu-
of the system and the inputs (voltage or current sources). rate results.
After correction to the point of switching, the system is 2) Algorithm II: After Step 6 in Algorithm I:
updated before proceeding to the next time-step. During 7. Using and , state is linearly extrapo-
the updates, inductor currents and capacitor voltages are lated.
kept unchanged. The following algorithms explain more For this step, states and have been chosen, in par-
details of this mode of operation. ticular, because they are fully corrected states. Note that state
1160 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 20, NO. 2, APRIL 2005

Fig. 2. Digital simulation algorithms for multiple switching events based on a fixed time-grid. : Full-state calculation, : Linear
Interpolation, : Linear Extrapolation.

is left uncorrected, however, for off-line simulator state 4. The power-electronic model (1) is updated to obtain
can be corrected to have more accurate results. Thus, in this al- using switching event .
gorithm there are 2 interpolations, 2 full-state calculations and 5. at time is calculated using (6).
1 extrapolation with a fixed . 6. Based on and state is extrapolated as
3) Algorithm III: After Step 5 in Algorithm I (i.e., once
has been determined)
(15)
6. The step-size of the simulation is changed from to
and is calculated.
7. State is calculated using (6). This algorithm is a variation of Algorithm II in which 1 inter-
Therefore, there are 2 interpolations, 2 full-state calculations polation and 1 full-state calculation has been substituted by one
and 1 recalculation in this algorithm. additional extrapolation with remaining fixed.
4) Algorithm IV: After Step 2 in Algorithm I, i.e., after 5) Algorithm V: After Step 4 in Algorithm IV (i.e., after ob-
has been obtained, this algorithm uses the following steps: taining by extrapolation from and and updating
switching at ), this algorithm uses the following steps:
3. is extrapolated based on and
5. The step-size of the simulation is changed from to
and is calculated.
(14)
6. is calculated using (6).
FARUQUE et al.: ALGORITHMS FOR THE ACCOUNTING OF MULTIPLE SWITCHING EVENTS 1161

This algorithm requires 1 interpolation, 1 full state calculation,

1 extrapolation, and 1 recalculation. It is a variation of
Algorithm III where 1 interpolation and 1 full-state calculation
has been replaced by 1 extrapolation.
6) Algorithm VI: Once the simulator obtains the informa-
tion of the two switching events then:
1) The system state at , the average loca-
tion of the two events at and , is interpolated based on
the states and

(16)

The power-electronic model (1) is updated using both

switching events and .
Fig. 3. Variable time-grid Algorithm VIII for two switching
2) State is calculated using (6).
events. : Full-state calculation, : Switching
3) is now extrapolated using and update, : Linear extrapolation.

(17) B. Variable Time-Grid Algorithms

1) Algorithm VIII: This algorithm is event-driven and varies
Thus, in this algorithm we have 1 interpolation, 1 full state cal- its external time-grid whenever it is interrupted by a switching
culation and 1 extrapolation with a fixed . event. However, the internal time-step of the simulation is fixed.
7) Algorithm VII: After Step 1 in Algorithm VI, this algo- Whenever a switching event is encountered, the simulator is
rithm uses the following steps: stopped at that instant and the time difference between
the initial point of that particular time step and the switching
2. The step-size of the simulation is changed from to
instant is calculated. Based on the value of , one of the fol-
and is calculated.
lowing four cases is executed.
3. State is calculated using (6).
• Case I If , an extrapolation using the two
Therefore, we have 1 interpolation, 1 full state calculation and
previously known states is performed to find the state at
1 recalculation.
the point of switching.
If the simulation time-step is changed internally as in algo-
• Case II If but , Backward Euler’s
rithms III, V, and VII, the recalculation of may become
integration is adopted for time-step and then an ex-
a significant computational bottleneck if the network is large.
trapolation is performed to the point of switching.
An efficient way to circumvent on-line calculation of for
• Case III If but , Trapezoidal inte-
a large network is to store pre-computed values for several
gration is adopted for time-step and then an extrap-
sub-multiples of ( integer), in a look-up table
olation is performed to the point of switching.
and apply them when required. For example, if
• Case IV If , Trapezoidal integration
can be computed off-line 10 times for 10 values of time
is adopted for time-step, Backward Euler’s in-
. Such an approach may not be
tegration is adopted for time-step and then an
precise as to the location of a switching event, however, it is
extrapolation is performed to the point of switching.
sufficiently accurate compared with calculation based on
Once the simulation reaches to the switching point then, the
a single large time-step . This pre-calculation of is
switching change is updated and the simulation proceeds with
feasible if the network condition prior to the switching events
original time-step but moves to a new time-grid. In case of two
is known. During a transient, this condition is generally unpre-
switching events, similar procedure is adopted and the simula-
dictable. Another approach to accommodate a large network
tion follows any of the four ways to reach the switching instant.
could be to interface the power-electronic circuit simulation
For each switching event the external time-grid is changed even
using algorithms III, V, or VII, with a fixed step-size network
though the internal simulation time step remains unchanged.
simulation, as reported in [4].
The only additional requirement for this algorithm is to save
The above algorithms are indeed capable of correcting three
for a time-step of .
switchings in one time-step. In such a case, the first two switch-
Fig. 3 illustrates this algorithm for both single and two
ings are corrected initially, followed by the correction of the
switching events. The simulation starts at the time on
third switching event. Further extension for accounting more
than three events is straight forward. The cost for having more Time-Grid 1. State at time is computed from state
switching events in one time-step is an increase in complexity of with a fixed time-step using (6). At time the sim-
the algorithms and they become extremely cumbersome. An ef- ulator begins calculating the state for time , however, it
ficient trade-off in handling multiple switching events would be is interrupted by a switching event at time . The time
to reduce the time-step such that at most two or three events difference between and is less than but greater
occur within one . than . Therefore, Case II is followed where Backward
1162 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 20, NO. 2, APRIL 2005

Fig. 4. D-STATCOM system and its digital controller.

Euler yields at a step of . Then, the system state IV. CASE STUDY: D-STATCOM SYSTEM
at time is extrapolated from the state and . The state A. System Model
at is then updated with the switching events. Now, with the
updated state , the simulation is transferred to Time-Grid 2 Fig. 4 illustrates a generic experimental set-up of the
and proceeds with a fixed time-step from time onward D-STATCOM power system and its digital controller. The
system consists of a three-phase insulated-gate bipolar tran-
and expected to reach at time . However, the simulation is
sistor (IGBT) bridge (switching frequency kHz)
interrupted again by a second switching event at time . connected via a series impedance ( and
As the distance between and is less than (Case mH) to the ac bus assumed to be a balanced voltage source
I), a single extrapolation is performed based on the state at ( V rms Hz). represents the filter induc-
at and at to find the state at . The state tance and the leakage inductance of the converter transformer.
at is then updated with the switching changes and the accounts for the converter and transformer conduction
simulation moves to Time-Grid 3 and starts from . From losses. The dc side capacitor is F. The switches
we assume that there is no switching event in the next time step in the voltage-source converter (VSC) are modeled as ideal
and a full time-step calculation is performed to reach the state bi-directional switches with gate turn-on and turn-off controls.
at time . From the time the simulation starts for a The VSC model is based on discrete switching functions. Three
full step but is interrupted by an event at time . Since switching signals control the upper switches
the distance between the time and is greater than in each leg of the converter. The lower switches in each leg
but less than (Case III), first a trapezoidal integration is of the converter are switched in a complementary manner.
performed to calculate the state at . Thereafter, Accordingly, the output voltages of the converter with respect
linear extrapolation between and is performed to reach to the negative dc bus are given as
the state at . The simulator then updates the switching
(18)
changes and moves to a new time-grid (not shown in the
figure). The simulation follows the similar approach for all the Under balanced conditions the converter output voltages with
future switching events and the states are recorded. Clearly, the respect to the AC system neutral are given as
output data of the simulation will be unevenly spaced due to the
changes in the original time-grid. Linear interpolation is used
(19)
to get an evenly spaced data set.
The benefits of implementing this variable time grid algo-
rithm are as follows:
Taking , and as the states, the time-domain model of
• No post event correction is necessary as the algorithm al- the system can be represented by three differential equations
ways uses the corrected states.
• The algorithm is suitable for implementing in real-time as (20)
it always advances with correct state values needed for the
controller to produce gating signals. (21)
• The internal simulation time step remains always un-
changed and recalculation of is obviated. (22)
FARUQUE et al.: ALGORITHMS FOR THE ACCOUNTING OF MULTIPLE SWITCHING EVENTS 1163

The current in phase , can be expressed as a linear combination

of and . The DC side current is given as

(23)

The above equations are solved by the simulator at every time-

step .

B. Digital Controller
The control design [25] has been carried out in the syn-
chronous frame. The control algorithm is executed every
which is the controller sampling period. First a coordinate
transformation from frame to frame is performed on the
system signals. Then a decoupled control of the currents and
Fig. 5. Illustration of multiple switchings through a detailed view of one
is performed using P-I compensator’s for each of the current complete cycle of PWM for D-STATCOM system.
loops. The DC-link voltage is regulated through an external
feedback loop. The resulting control quantities- modulation
TABLE I
index and phase angle of the control signal -are then sent to the VARIATION OF SWITCHING EVENTS WITH SIMULATION STEP-SIZE FOR A
pulsewidth modulator (PWM) for the generation of switching SIMULATION PERIOD OF 2 S WITH CARRIER FREQUENCY OF 1 kHz
signals based on the sampling technique approach [26]. A
delay of one sampling period is introduced in the controller
implementation in order to account for the finite execution time
taken by the DSP.

V. RESULTS AND DISCUSSION

All of the algorithms, I through VIII, have been used to sim-
ulate the D-STATCOM system and their performance was com- A. Open-Loop Control
pared with that of a fixed time-step algorithm (Fig. 1). Results
were obtained through off-line simulation of programs written Under open-loop conditions, the output of the VSC was
in C. It was observed that as the computational complexity of the varied by varying the modulation index
algorithms decreased, their execution speed increased, however, and the phase angle of the control signal. The value
at the cost of a small inaccuracy. Both open-loop and closed- and were chosen in order to get high fundamental
loop control studies were performed. In the modulator, sinu- error and THD using fixed time-step algorithm so that the
soidal PWM scheme with 1-kHz switching frequency was used improvements due to the corrected algorithms can be clearly
in which only half of the carrier signal was implemented in one demonstrated. To calculate the fundamental error, the ref-
sampling period of the digital controller (i.e., erence is chosen as a case of time-step, s. This
or, where kHz). Such an approach was is 1000 times smaller than the switching time period
taken in order to limit the number of discrete switching events ( s) and it has been selected to serve as a benchmark
to a maximum of three in one simulation time-step . Fig. 5 against which the results obtained with limited step-sizes
illustrates the multiple switching phenomenon using one pe- s) were compared. Results for the fixed
riod of the triangular carrier used in PWM. The snapshot of time-step approach were also verified against simulations on
PWM produced here starts at time s and ends at PSCAD/EMTDC Version 3. The two major effects observed
s with s. The control signals com- due to the changes in were
puted for the three phases intersect with the first leg of the car- 1) A significant change in the fundamental component of
rier signal at s (phase c), s (phase b) and the phase current.
s (phase a). The switching signals are 2) A marked crowding of the frequency spectrum with
also shown in Fig. 5. Evidently, the switching of phase is the noncharacteristic harmonics and, hence, a degradation
only event during the time interval s to s, in THD.
whereas switching of phase and phase constitute two events The change in fundamental component is expressed in terms of
in the time interval s to s. Similar be- percentage absolute error which is defined as
havior can be seen during the second leg of the carrier signal. It
can also be observed that the case of two switching events oc-
(24)
curs when two control values are close in their magnitude. As
the time-step is increased, multiple switchings occur more
often. This fact is corroborated in Table I which records the fre- where is the fundamental component of current at a par-
quency of time-steps with no events, one event and two events. ticular time-step and is the fundamental component
1164 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 20, NO. 2, APRIL 2005

TABLE II
FUNDAMENTAL ERROR " AND THD OF I FOR VARYING 1t AND THE TOTAL SIMULATOR OPERATIONS. (A) FULL-STATE COMPUTATION, (B)
LINEAR INTERPOLATION, (C) LINEAR EXTRAPOLATION, (D) [;  ] RE-CALCULATION

of current with 1 s time-step. The percentage THD for the cur- algorithm. Even at a smaller time-step such as
rent waveform simulated using a certain time-step is defined as s, the error is less than 0.8% for all the proposed
algorithms, whereas fixed time-step algorithm shows an
error of 2.4%. The decreases to a range of 0.5%–9%
% (25) from 38.2% for the fixed time-step algorithm when
s.
• Algorithms II through VII are less accurate in comparison
For the fixed time-step algorithm A and the with Algorithm I, and therefore produce significant har-
%. The and THD for different algorithms monic current at higher time-steps. However, they are still
with step-sizes of 10, 50, 100, and 150 s are also presented in able to compensate for the fundamental current and keep
Table II. The table also summarizes the number of operations its value low. Therefore, the percentage rms error is small
required by each of the proposed algorithms. Algorithm I and but the THD for these algorithms remains high at higher
II are the most rigorous and accurate while other algorithms time-steps. Furthermore, Algorithms II to VII do not use
bear relatively less computational burden and are therefore less the corrected state as the the output at time in order
accurate in comparison. The accuracy of these algorithms (III to conform to the real-time condition that it would not be
through VII) can be further improved through a correction of possible to send the corrected value to the controller.
state by interpolation. A remarkable improvement in per- • If state is allowed to be corrected, a significant im-
formance especially in THD was observed when state was provement in THD is observed. The results in Table II
corrected (as seen from Table II). The following conclusions for a 150- s time-step reveal that all algorithms (except
can be drawn from the results: Algorithm VIII) show THD in the range of 18% to 24%,
• In the fixed time-step algorithm, as the time-step is in- whereas fixed time-step algorithm shows a THD of 46%.
creased from s to s, we find that the Offline simulators can exploit the benefit of correcting
fundamental current increases drastically (from 17.1 A to state .
24.7 A), due to not accounting the switching events at their For any given , the accuracy of all the algorithms was found
right instants, hence the percentage fundamental error to be similar to that of the fixed time-step algorithm using one-
increases from 2.4% to 33.66%. The harmonic current tenth . Using similar simulation parameters and environment,
also increases at almost the same rate. Therefore, THD re- the algorithm used in HYPERSIM [19] has been extended for
mains almost unchanged (around 16%). However, at much multiple switching events. A comparative study revealed that all
higher time-steps e.g., s, the harmonic cur- the proposed algorithms produce results that are in close agree-
rent increases at a faster rate than the fundamental current, ment with the results obtained using the HYPERSIM algorithm
which is why we get a higher THD (46%) at that time-step. until s. At 10-, 50-, and 100- s time-steps, the HY-
• A time-step of over 50 s (for the study system with a PERSIM algorithm yielded an error of 0.34, 0.98, and 4.6 (%)
switching frequency of 1 kHz) is inadequate for simulation respectively, however, at 150 s or higher it produced an in-
using the fixed time-step approach due to a high error (the creasing error (higher than 30%).
error increases to 38.25% for s. A comparison of steady-state current for fixed time-step algo-
• As the time-step varies from s to s, rithm and Algorithm VII is shown in Fig. 6. The current wave-
Algorithm I treats the switching events accurately, thereby form with fixed time-step algorithm differs significantly when
reducing both the fundamental and the harmonic currents. the time-step is changed from 10 s to 150 s. However Al-
Therefore, both the percentage rms error and THD remain gorithm VII with 150 s is in close conformity with the 10- s
small (close to their values at s. case of fixed time-step algorithm. The difference is more ob-
• For Algorithms II through VII, both THD and increase, vious from the Fig. 7, where the frequency spectrum is plotted.
with the increase of time-step, however, the increase in Fixed time-step algorithm with s shows a substan-
is less pronounced compared to that for the fixed time-step tial difference in fundamental component in comparison with
FARUQUE et al.: ALGORITHMS FOR THE ACCOUNTING OF MULTIPLE SWITCHING EVENTS 1165

Fig. 6. Detailed view of the steady–state current I . Curve 1: Fixed time-step "
4
algorithm with t = 10 s, Curve 2: Fixed time-step algorithm with t = 4 Fig. 8. Plot of percentage fundamental error with respect to simulation
4
150 s, Curve 3: Algorithm VII with t = 150 s.
time-step.

Fig. 7. Frequency spectrum of I . Data 1: Fixed time-step algorithm with

4t = 10 s, Data 2: Algorithm VII with 4t = 150 s, Data 3: Fixed time-step
algorithm with 4t = 150 s.
Fig. 9. Plot of THD with respect to simulation time-step.

the other two cases. It also induces noncharacteristic harmonics

which eventually result in higher THD. algorithms for a large time-step of 150 s or higher. The reason
The behavior of various algorithms with the increase in is that the algorithm resorts to frequent application of backward
can be further understood from Fig. 8 where the has been Euler and linear extrapolation (due to an increased step-size re-
plotted with respect to . It is clear that for any value of time- sulting in more switching events within a time-step) which is
step, all the algorithms produce significantly less error than that less accurate than the trapezoidal technique. However, it pro-
of fixed time-step. Some algorithms show a little increase in duces results as good as or even better than other algorithms at
error at a time-step of 100 s. Algorithms I and III produce the smaller time-steps ( s).
best result for a time-step of 150 s and as expected the error
becomes high for other algorithms, however, it is much less than B. Closed-Loop Control
that of fixed time-step algorithm. Therefore, it can be concluded Fig. 10 shows the D-STATCOM closed-loop response. A step
that all the algorithms substantially improve the simulation ac- response in was simulated. The simulations were carried out
curacy. The variation of THD as a function of time-step for for all the algorithms using various step-sizes, however, results
various algorithms using corrected state is shown in Fig. 9. are shown for the fixed step-size algorithm for s and
Fixed time-step algorithm shows almost same THD until for s and Algorithm VII for s. The
s after which it increases dramatically. On the other hand, predominant effect observed due to an increase in the time step
most of the algorithms (except Algorithm VIII) show a lower was the appearance of noise in the control quantities. As seen
THD than the case of fixed time-step algorithm. Algorithm VIII from Fig. 10, the traces of for s are smooth whereas
produces a higher and THD compared to the fixed time-grid those for s contain a noise superimposed on the
1166 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 20, NO. 2, APRIL 2005

Fig. 11. Execution time for the time-step involving multiple switching events,
4
for various algorithms with t = 100 s.

low-pass anti-aliasing filters on the system signals before they

are sampled. In an off-line simulation program the noise in the
control quantities may also be substantially reduced by using
linear interpolation in the control algorithm [12].
Fig. 10. Step response in i simulated using the (A) Fixed time-step
4 4
algorithm with t = 10 s, (B) Fixed time-step algorithm with t = 100 s,
4
(C) Algorithm VII with t = 100 s, and (D) Algorithm VII with C. Execution Time
4 t = 100 s but x corrected.
The execution time required for the off-line simulation of
TABLE III
these algorithms depends on several factors such as the pro-
COMPARISON OF MEAN ABSOLUTE DEVIATION (MAD) AND cessor speed, hardware [such as random-access memory (RAM)
SIGNAL-TO-NOISE RATIO (SNR) (dB) OF i PRODUCED BY
4
DIFFERENT ALGORITHMS FOR t = 100 S
and bus speed], and the operating system. Notwithstanding
the minor variations in processor time due to multi-tasking,
the testing conditions for all the algorithms were maintained
the same. The simulation programs were coded in C and all
the programs were executed on the same hardware using a
1.5-GHz Pentium IV processor running Windows 2000. The
CPU time required to simulate the test system for the worst case
of multiple switching (two switching events in one time-step)
is shown in Fig. 11. The increased complexity in correcting the
switching events using different algorithms increases the exe-
cution time by a maximum of only 9% (Algorithm I), compared
to the fixed time-step approach. However, the improvement in
the simulation accuracy is significant.
average value. A Fourier analysis proved that the noise is mainly Using the proposed algorithms, an accurate simulation is pos-
white with unlimited bandwidth. Table III compares the mean sible even with a larger step-size, which makes these algorithms
absolute deviation (MAD) and the signal-to-noise ratio suitable for real-time application. Even though the difference
dB, where is the signal power and is in CPU execution time among different algorithms is not very
the noise power) of for all the algorithms. Algorithm I shows large, it has been found that algorithms that do not involve rig-
the best signal quality as it always uses the true state results. orous calculations (II through VII) as compared to Algorithm
Results in Table III reveal that the signal quality deteriorates I, requires less CPU time; for example, the CPU time require-
slightly as we move from Algorithm II to Algorithm VII. It can ment for Algorithm VII is 7.84% lower than that of Algorithm
be seen that [Fig. 10(C)] for Algorithm VII using s, I. Algorithm VIII takes the least amount of time of all the pro-
the output shows a MAD of 1.6 around its reference value posed algorithms. The D-STATCOM system, due to its mod-
(10 A), however, the fixed time-step algorithm shows a MAD eling simplicity is not able to show a larger CPU time difference
of 1.79. The SNR for Algorithm VII is 33.54 dB and it is 29.32 between algorithms, however, a larger system with more mod-
dB for the fixed time-step algorithm. Table III reveals that if eling complexity such as multi-pulse HVDC system would be
corrected states are used for control, MAD would be reduced able to show definite computational advantages in favor of Al-
to 0.64 and SNR would be increased to 49.56 dB. In a practical gorithm II through VII. And there lies the motivation of using
set-up of the digital controller the noise may be reduced by using the proposed algorithms even with uncorrected states.
FARUQUE et al.: ALGORITHMS FOR THE ACCOUNTING OF MULTIPLE SWITCHING EVENTS 1167

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