2017 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE)

18-19 December 2017, WIT, Dehradun, India

Airborne Radar Signal Processor Realisation

Reena Mamgain and Rashi Jain
Defence Research & Development Organisation
Bangalore, India 560093
Email: { reenamamgain@lrde.drdo.in , ras hi25@yahoo.com}

Abstract—Signal processor for airborne Active Electronically

Scanned Array (AESA) radar has stringent requirement in
terms of dynamic load handling, latency and throughput require-
ment. In this paper, Radar Signal Processor(RSP) realisation
for airborne radar is discussed with specific emphasis on S/W
architecture for its deployment on multiprocessor based H/W
platform using Commercial Off The Shelf(COTS) board. The
S/W architecture is based on master slave configuration which
leverages parallelism. This architecture is termed as Cluster Of
Processors(CoPs). Sizing analysis and benchmarking of com-
putational resources is also done to ascertain the number of
processors required to meet realtime performance. In addition Fig. 1. Radar input data matrix
to it, a case study for RSP is also carried to outline the realisation
of optimised RSP.
Keywords:AESA, radar signal processor, Control Node, Compute
Element, SIMD, Sizing analysis,Cluster Of Processors II. H/W REALISATION
AESA radar dwell timings vary within coverage volume
I. I NTRODUCTION
scan with dynamic beam scheduling for dynamic mode han-
Airborne radar employing Active Electronically Scanned dling and for compensating scanning loss. AESA radar dwell
Array (AESA) technology imposes stringent constraints on timings are higher at off-boresight scan angle compared to
Signal Processor (SP) [1]. Radar with multifunction, multi- boresight angle because the beam gets broadened and radar
mode and interleaved mode capability requires beams to be has to transmit more number of pulses at offboresight to
scheduled instantly within the coverage sector. This leads to compensate the scan loss. The occurrence of short and long
dynamic load handling requirement for RSP. In addition, RSP dwell is randomly time multiplexed; which leads to dynamic
H/W realisation shall be airworthy with SWaP (Space, Weight nature of processing load on RSP. Programmable RSP with
and Power) and reliability constraints. A literature survey for real time processing and high number crunching capability is
signal processor architecture [2] shows that multiprocessor important enabling factor for phased array radars. Computa-
RSP is based on multicore digital signal Processors(DSPs) tionally efficient multiple processor boards with high speed
with Serial rapidIO(SRIO) as high speed serial interconnect serial interconnect for data transfer and high speed data ac-
fabric. In literature [3], the computational requirement for quisition interface is considered for RSP H/W realisation. The
RSP algorithms of pulse doppler radar is estimated using multiprocessor based H/W platform is realised with PowerPC
mathematical operations. Quantitative approach for sizing processor based COTS boards with high speed serial interface
analysis is discussed in [4] for design of General Purpose over optical link for acquiring input data. The PowerPC with
Processor(GPP) based architectures. In this paper multipro- Altivec engine efficiently utilizes vector libraries which ex-
cessor based H/W using GPP enhanced with vector libraries ploits data parallelism for achieving computational efficiency.
and SRIO as high speed interconnect is considered for RSP. The S/W architecture is implemented on this multiprocessor
This paper describes the realisation of airborne radar signal based H/W platform in a master slave configuration. The
processor along with S/W architecture implementation for real sizing analysis is discussed in section VCase Studysection.5
time execution on multiprocessor based H/W platform. Section in details.
IIH/W realisationsection.2 describes H/W realisation based on
quantitative analysis of suitable data architecture for RSP [5]. III. S/W REALISATION
Section IIIS/W realisationsection.3 describes the S/W archi- Generally, radar data consists of a batch of pulses called
tecture to meet high throughput requirement with dynamic bursts which are transmitted in a direction and processed to
load handling. Section IVSizing analysissection.4 describes extract the target information. Multiple such bursts transmitted
the S/W optimisation carried out to achieve computational in a given direction constitute a dwell. Typically in case of
requirements. In section VCase Studysection.5 the case study Medium PRF (MPRF), multiple bursts are used to avoid range
of airborne RSP is discussed along with optimisation of SP and doppler ambiguity. In case of a MPRF radar, the typical
algorithms on H/W platform with timing constraints. Section value of burst time varies from 1ms to 100ms. Radar data is
VIConclusionsection.6 draws the conclusion. organised as a matrix wherein the two dimensions are pulse

978-1-5386-2621-4/17/$31.00 ©2017 IEEE 279

2017 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE)
18-19 December 2017, WIT, Dehradun, India

TABLE I
SIGNAL PROCESSOR ALGORITHM LIST ILLUSTRATING PROCESSING
DIMENSION AND DATA PARALLELISM

Sl.no. SP algorithm Processing Data par-

dimension allelism
1. Fixed to floating Both range yes
point data for- and pulse
matting
2. Digital pulse range yes
compression
3. Sum & differ- range yes
ence channel for-
mation
4. Platform motion range yes
compensation
with MTI
5. Doppler filtering pulse yes
6. Magnituding Both range yes
and pulse
Fig. 2. Data driven master-slave architecture for effective utilization of 7. Dual cfar Both range yes
processing resource and pulse
8. Monopulse pulse yes
9. Sidelobe range yes
blanking
10. Ambiguity range yes
and range. This data organisation is brought out in fig. 1Radar resolver
input data matrixfigure.1.
For a typical burst in one of the mode, this data may vary
from as low as 10 to as high as 1000 pulses and 50 to 500 other available CEs. Thus this architecture also helps fault
range samples. To meet the throughput, the average execution tolerance. Generally, the numbers of computational resources
time shall not exceeed the corresponding data collection time are designed with 20% margin.
of dwell, also called as dwell time. To achieve this, high level
of parallelism of computational resources, Single Instruction IV. S IZING ANALYSIS
Multiple Data(SIMD) [6] based master slave architecture, is The requirement specification of radar impacts the computa-
implemented as shown in fig.2Data driven master-slave archi- tional resource requirement for RSP. This in turn decides the
tecture for effective utilization of processing resourcefigure.2. number of processors required given a particular processor
The two nodes, Control Node (CN) as master and Compute type. The recent trend shows that the RSP is realised using
Element (CE) as slave are the basic entities in this architecture COTS boards. Typical airborne radar operates on Medium PRF
and each is deployed onto different processor. The function of mode to handle clutter and enable range and doppler ambiguity
CN is to acquire complex I/Q data along with header serially resolution. Typical PRF for an airborne radar range between
over high speed interface for all the channels. The interface 5-15 KHz with a range of 200km with a coverage of 120
for acquiring input is selected as Serial Front Panel Data degrees. The radar signal processing chain mainly includes the
Port (sFPDP) [7]. Each burst data is transferred to one of following algorithms in table Isignal processor algorithm list
the CE for signal processing using SRIO as high speed serial illustrating processing dimension and data parallelismtable.1
interconnection fabric. The final output reports are sent to radar to be executed in orderly fashion [9]. The table Isignal pro-
data processor for further processing over high speed (1 Gbps) cessor algorithm list illustrating processing dimension and data
ethernet interface. The CN has additional job of keeping a parallelismtable.1 shows the different algorithms with process-
track of free CEs in a queue and assigns the data to free ing dimension and data parallelism possibility. Algorithms are
CE based on processing mode. There is no interdependency used in sizing analysis for processors. This approach is similar
between CEs for carrying out the entire processing for a to quantitative analysis of data flow architecture for general
particular burst. The processing carried out by a CE depends purpose processors [4], [5]. The approximate execution time
upon the mode of radar operation. Since each of CE perform for above algorithms is determined using optimized Altivec
execute same set of mathematical functions for a particular library function for PowerPC. The computational resource
mode with different data sets, it is termed as SIMD parallelism. requirement with PRF and beam angle is used in conjunction
This results in advantage of SIMD architecture with respect with above executive time to determine required number of
to graceful degradation. This architecture is termed as Cluster processors as shown in the table IIthe number of processor
Of Processors (COPs) [8] architecture and is advantageous to requirement with PRF and beam pointing angletable.2.
cater for increased processing requirement with addition of Approximate estimate of number of processor is used for
another CE without redefining of S/W architecture. Similarly, realisation of multiprocessor based H/W platform using COTS
even if one or two CEs are not available for processing owing board. The advantages of the proposed H/W and S/W archi-
to H/W or S/W failure, load can be distributed by CN to tecture include fault tolerance, scalability of H/W & S/W,

978-1-5386-2621-4/17/$31.00 ©2017 IEEE 280

2017 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE)
18-19 December 2017, WIT, Dehradun, India

TABLE II sizing analysis can be done using Cluster Of Processor archi-

THE NUMBER OF PROCESSOR REQUIREMENT WITH PRF AND BEAM tecture. The time of execution reduces with advancement of
POINTING ANGLE .
processor technology whereas the approach for sizing analysis
Sl.no. Beam PRF PRF PRF remains the same. This architecture has the advantage of
angle in 5KHz 10KHz 15KHz scalability, reliability and fault tolerance and can be extended
deg
1. 0 8 7 8 for future H/W with little modification based on interface
2. 30 9 8 9 available at data and control plane.
3. 45 10 10 9
4. 60 10 11 10 R EFERENCES
[1] Zain Ul-Abdin and Mingkun Yang ,”Dataflow Programming of Real-
TABLE III time Radar Signal Processing on Manycores”,IEEE Global conference
CFAR EXECUTION TIME COMPAISION WITH OPTIMISATION on signal and Information processing (GlobalSIP), Dec 2014
[2] Abdessamad Klilou1*, Said Belkouch1, Philippe Elleaume2, Philippe
CFAR execution time before 6.7 boresight angle Le Gall2, Franois Bourzeix3 and Moha M’Rabet Hassani1 “ Real-
optimisation (in millisec) 70.02 offboresight angle time parallel implementation of Pulse-Doppler radar signal processing
CFAR execution time after 3.4 boresight angle chain on a massively parallel machine based on multi-core DSP and
optimisation (in millisec) 35.0 offboresight angle Serial RapidIO interconnect”, EURASIP Journal on Advances in Signal
Processing November 2014
[3] R. Broichy and H. Grobler,”Analysis of the Computational Requirements
of a Pulse-Doppler Radar Signal Processor”IEEE Radar Conference,
deployment of additional/enhanced algorithms at later stage May 2012
without significant modification on H/W or S/W. [4] B. Kienhuis, E. Deprettere, K. Vissers, and P. Van DerWolf,An approach
for quantitative analysis of application-specific dataflow architectures,’
in Application-Specific Systems, Architectures and Processors, IEEE
V. C ASE S TUDY Int.Conf July 1997, pp. 338 349
The above mentioned architecture is realised on H/W with [5] J. L. Hennessy and D. A. Patterson Computer Architecture: A Quanti-
tative Approach, 3rd ed. Morgan Kaufmann, 2002
multiple processors based on PowerPC 8640 (1 Ghz clock ) [6] Anders Astrom, Mattias Johannesson, Anders Edman ,”An Implementa-
as compute node for an airborne surveillance radar application tion Study of Airborne Medium PRF Doppler Radar Signal Processing
[10]. The vxWorks is used as real time operating system. on a Massively Parallel SIMD processor Architecture”IEEE Radar
Conference, May 1995
The s/w is coded in high level c language. A case study is [7] SFPDP Draft standard vita 17.1-200x.
mentioned for the same. Using data simulator, benchmarking [8] Deepak Kumar, Debasish Deb, Reena Mamgain, ”Analysis of different
was done for processor utilization in different modes and multiprocessor architectures for radar signal processing with perfor-
mance metrics”,IEEE Radar Conference, Oct 2015
varying burst timings. Fig.?? shows that worst case processors [9] Mark A. Richards, Fundamentals of radar signal processing,Georgia
requirement as 11 which is matching with sizing analysis Institute of Technology ,2005
shown in the tableIIthe number of processor requirement with [10] Peter Joseph,Saikat Roy Chowdhury,Debasish Deb,An Efficent Method-
ology for Realization of Parallel FFT for Large Data Set, Advances in
PRF and beam pointing angletable.2. Computing Communication ACC2011,Vol 191.Springer, Berlin, Heidel-
In addition to it, during field trials, the algorithms are berg.
refined for performance improvement which leads to increased
processing load. Towards this, optimisation was done on few
algorithms like Constant False Alarm Rate (CFAR) which is
implemented using vector library to achieve better execution
time as shown in the table IIICFAR execution time compaision
with optimisationtable.3. The CFAR algorithm was earlier im-
plemented using running sum average as conventional CFAR
processing.The fast convolution based CFAR processing is
implemented to take advantage of vector library for better
execution time. Linear operation like data formatting, DPC and
Sum and difference beam formation were combined for better
execution time [8]. Thus S/W optimisation with a trade off in
S/W modularity achieves efficient execution time without any
change in H/W.
VI. C ONCLUSION
RSP system is deployed in airborne radar and is extensively
tested at different terrains with different type of aerial targets.
The H/W realisation using quantitative approach along with
COPs architecture and S/W optimisation in algorithm imple-
mentation has resulted in robust radar signal processor system.
For future work, where the next generation processors with
multicores and high processing power are available, similar

978-1-5386-2621-4/17/$31.00 ©2017 IEEE 281