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Report about:

82C54 Programmable Interval Timer

Microprocessors Applications
‫تطبيقات المعالجات الدقيقة‬

‫ علي سليم صاحب علي‬: ‫اسم الطالب‬

‫ فرع تكنولوجيا المعلومات‬/ ‫ هندسة الحاسوب‬: ‫االختصاص‬
‫ الثالثة‬: ‫المرحلة‬
‫ الصباحية‬: ‫الدراسة‬
2020 / 7 / 4 : ‫تاريخ التسليم‬

2019-2020
Introduction

The Intel 82C54 are Programmable Interval Timers (PTIs) designed for microprocessors to
perform timing and counting functions. The 82C54 solves one of most common problem in
any microcomputer system, the generation of accurate time delays under software control.
Instead of setting up timing loops in system software, the programmer configures the 82C54
to match his requirements, initializes one of the counters of the 82C54 with the desired
quantity, then upon command the 82C54 will count out the delay and interrupt the CPU when
it has completed its tasks. It is easy to see that the software overhead is minimum and that
multiple delays can be easily be maintained by assignment of priority levels.
The 82C54 includes three identical 16 bit counters that can operate independently. To operate
a counter, a 16-bit count is loaded in its register and, on command, it begins to decrement the
count until it reaches 0. At the end of the count, it generates a pulse that can be used to interrupt
the CPU. The counter can count either in binary or BCD. In addition, a count can be read by
the CPU while the counter is decrementing.

Features of 82C54
1) Three independent 16-bit down counters.
2) 8254 can handle inputs from DC to 10 MHz (5MHz 8254-5 8MHz 8254 10MHz 8254-2) .
3) Three counters are identical presentable, and can be programmed for either binary or BCD
count.
4) Counter can be programmed in six different modes.
5) Compatible with all Intel and most other microprocessors.
6) 8254 has powerful command called READ BACK command, which allows the user to check
the count value, programmed mode and current mode and current status of the counter.
 Pin diagram of 8254

Figure shows the block diagram of 8254. It includes three counters, a data bus buffer,
Read/Write control logic, and a control register. Each counter has two input signals CLOCK
and GATE and one output signal OUT.
We will explain each part individually:
Data Bus Buffer:
This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to the system data
bus , The Data bus buffer has three basic functions.
 Programming the modes of 8253/54.
 Loading the count registers.
 Reading the count values.

Read/Write Control Logic:

The Read/Write Logic accepts inputs from the system bus and generates control signals for
the other functional blocks of the 82C54. A1 and A0 select one of the three counters or the
Control Word Register to be read from/written into. A ‘‘low’’ on the RD input tells the
82C54 that the CPU is reading one of the counters. A ‘‘low’’ on the WR input tells the
82C54 that the CPU is writing either a Control Word or an initial count. Both RD and WR
are qualified by CS; RD and WR are ignored unless the 82C54 has been selected by holding
CS low.
The control word register and counters are selected according to the signals on lines A0 and
A1, as shown below:

Control Word Register:

The Control Word Register is selected by the Read/Write Logic when A1, A0 = 11. If the CPU
then does a write operation to the 82C54, the data is stored in the Control Word Register and
is interpreted as a Control Word used to define the Counter operation
This register is accessed when lines A0 and A1 are at logic 1. It is used to write a command
word which specifies the counter to be used (binary or BCD), its mode, and either a read or
write operation. Following table shows the result for various control inputs.

Counters (Counter 0, Counter 1, Counter 2):

These three functional blocks are identical in operation. Each counter consists of a single, 16
bit, pre-settable, down counter. The counter can operate in either binary or BCD and its input,
gate and output are configured by the selection of modes stored in the control word register.
The counters are fully independent. The programmer can read the contents of any of the three
counters without disturbing the actual count in process.
The Counters are fully independent. Each Counter may operate in a different Mode. The
Control Word Register is shown in the figure below; it is not part of the Counter itself, but its
contents determine how the Counter operates.

82C54 System Interface

The 82C54 is treated by the systems software as an array of peripheral I/O ports; three are
counters and the fourth is a control register for MODE programming. Basically, the select
inputs A0, A1 connect to the A0, A1 address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method. Or it can be connected to the
output of a decoder, such as an Intel 8205 for larger systems.
Operational Description
After power-up, the state of the 82C54 is undefined. The Mode, count value, and output of all
Counters are undefined. How each Counter operates is determined when it is programmed.
Each Counter must be programmed before it can be used. Unused counters need not be
programmed.

Programming the 82C54

Each counter of the 8253/54 is individually programmed by writing a control word into the
control word register (A0 - A1 = 11). The Fig. below shows the control word format. Bits SC1
and SC0 select the counter, bits RW1 and RW0 select the read, write or latch command, bits
M2, M1 and M0 select the mode of operation and bit BCD decides whether it is a BCD counter
or binary counter.

Write Operations
The programming procedure for the 82C54 is very flexible. Only two conventions need to be
remembered:
1) For each Counter, the Control Word must be written before the initial count is written.
2) The initial count must follow the count format specified in the Control Word (least
significant byte only, most significant byte only, or least significant byte and then most
significant byte).
With a clock and an appropriate gate signal to one of the counters, the above steps should start
the counter and provide appropriate output according to the control word.
Read Operations
There are three possible methods for reading the Counters. The first is through the Read-Back
command, which is explained later. The second is a simple read operation of the Counter, which
is selected with the A1, A0 inputs. The only requirement is that the CLK input of the selected
Counter must be inhibited by using either the GATE input or external logic. Otherwise, the
count may be in process of changing when it is read, giving an undefined result.
 Simple Read: It involves reading a count after inhibiting the counter by controlling the
gate input or the clock input of the selected counter, and two I/O read operations are
performed by the CPU. The first I/O operation reads the low-order byte, and the
second I/O operation reads the high order byte ,the first I/O operation reads the low-
order byte, and the second I/O operation reads the high order byte.
 Counter Latch Command The other method for reading the Counters involves a
special software command called the “Counter Latch Command”. Like a Control
Word, this command is written to the Control Word Register, which is selected when
A1, A0 = 1,1. Also, like a Control Word, the SC0, SC1 bits select one of the three
Counters, but two other bits, D5 and D4, distinguish this command from a Control
Word.

 READ-BACK Command: the third method uses the Read-Back command. This
command allows the user to check the count value, programmed Mode, and current state
of the OUT pin and Null Count flag of the selected counter(s). The command is written
into the Control Word Register and has the format shown in Figure below. The command
applies to the counters selected by setting their corresponding bits D3,D2,D1 e 1.
This command is used to read several counters at a time. It eliminates the need of writing
separate counter-latch commands for different counters. It allows the user to check the count
value, programmed Mode, and current states of the OUT pin and Null Count flag of the
selected counter/ counters. The read-back command may also be used to latch status
information of selected counter(s) by setting STATUS bit D4 = 0. Status must be latched to
be read; status of a counter is accessed by a read from that counter.
The counter status format is shown in Figure below
Read/Write Summery
Modes of Operation
Mode Definitions: The following are defined for use in describing the operation of the
82C54.
 CLK PULSE - A rising edge, then a falling edge, in that order, of a Counter’s CLK
input.
 TRIGGER - A rising edge of a Counter’s Gate input.
 COUNTER LOADING - The transfer of a count from the CR to the CE (See
“Functional Description”)

Mode 0: Interrupt on terminal count

It is used to generate an interrupt to the microprocessor after a certain interval.
Normal Operation :
 The output will be initially low after the mode set operation.
 After the count is loaded into the selected count Register the output will remain
low and the counter will count.
 When the terminal count is reached the output will go high and remain high until
the selected count is reloaded.
 Gate Disable:
 Gate = 1 enables counting.
 Gate = 0 disables counting
. Note : Gate has no effect on OUT If G becomes a logic 0 in the middle of the count, the
counter will remain stop until G again becomes a logic 1.

New Count:
 If a new count is written to the counter, it will be loaded on the next CLK pulse
and counting will continue from the new count.
 In case of two byte count :
 Writing the first byte disables counting.
 Writing the second byte loads the new count on the next CLK pulse and counting
will continue from the new count.
Mode 1 : Hardware Retriggerable One-Shot
It can be used as a mono stable multi-vibrator.
Normal operation:
 The output will be initially high
 The output will go low on the CLK pulse following the rising edge at the gate
input.
 The output will go high on the terminal count and remain high until the next rising
edge at the gate input.

Retriggering:
 The one shot is retriggerable, hence the output will remain low for the full count
after any rising edge of the gate input.

New count :
 If the counter is loaded during one shot pulse, the current one shot is not affected
unless the counter is retriggered. If retriggered, the counter is loaded with the new
count and the one-shot pulse continues until the new count expires.
Mode 2 : Rate generator
This Mode functions like a divide-by-N counter. It is typically used to generate a Real Time
Clock Interrupt.
Normal Operation
 The output will be initially high.
 The output will go low for one clock pulse before the terminal count.
 The output then goes high, the counter reloads the initial count and the process is
repeated.
 The period from one output pulse to the next equals the number of input counts in
the count register.

Gate Disable
 If Gate = 1 it enables a counting otherwise it disables counting (Gate = 0)
 If Gate goes low during an low output pulse, output is set immediately high. A
trigger reloads the count and the normal sequence is repeated.

New count
 The current counting sequence does not affect when the new count is written. If a
trigger is received after writing a new count but before the end of the current period,
the new count will be loaded with the new count on the next CLK pulse and
counting will continue from the new count. Otherwise, the new count will be loaded
at the end of the current counting cycle. Note : In mode 2, a count of 1 is illegal.
MODE 3 : Square Wave Rate Generator
Mode 3 is typically used for Baud rate generation. It is mean Generates a continuous square
wave at the out connection. Mode 3 is similar to Mode 2 except for the duty cycle of OUT.

Normal operation
 Initially output is high.
 For even count, counter is decremented by 2 on the falling edge of each clock
pulse. When the counter reaches terminal count, the state of the output is changed
and the counter is reloaded with the full count and the whole process is repeated.
 If the count is odd and the output is high the first clock pulse (after the count is
loaded) decrements the count by 1. Subsequent clock pulses decrement the clock
by 2. After timeout, the output goes low and the full count is reloaded. The first
clock pulse (following the reload) decrements the count by 3 and subsequent clock
pulse decrement the count by two. Then the whole process is repeated. In this way,
if the count is odd, the output will be high for (n+1)/2 counts and low for (n-1)/2
counts.

Gate Disable
 If Gate is 1 counting is enabled otherwise it is disabled. If Gate goes low while
output is low, output is set high immediately. After this, When Gate goes high, the
counter is loaded with the initial count on the next clock pulse and the sequence is
repeated.
New Count
 The current counting sequence does not affect when the new count is written. If a
trigger is received after writing a new count but before the end of the current half-
cycle of the square wave, the counter will be loaded with the new count on the next
CLK pulse and counting will continue from the new count. otherwise, the new count
will be loaded at end of the current half-cycle.
Mode 4 : Software Triggered Strobe
Allows the counter to produce a single pulse at the output.
Normal operation
 The output will be initially high
 The output will go low for one CLK pulse after the terminal count (TC).

Gate Disable
 If Gate is one the counting is enabled otherwise it is disabled. The Gate has no effect
on the output.

New count
If a new count is written during counting, it will be loaded on the next CLK pulse and
counting will continue from the new count. If the count is two byte then 1) Writing the first
byte has no effect on counting. 2) Writing the second byte allows the new count to be loaded
on the next CLK pulse.
Mode 5 : Hardware triggered strobe (Retriggerable).
Normal operation
 The output will be initially high.
 The counting is triggered by the rising edge of the Gate.
 The output will go low for one CLK pulse after the terminal count (TC).

Retriggering
 If the triggering occurs on the Gate input during the counting, the initial count is
loaded on the next CLK pulse and the counting will be continued until the terminal
count is reached.

New count
 If a new count is written during counting, the current counting sequence will not be
affected. If the trigger occurs after the new count is written but before the terminal
count, the counter will be loaded with the new count on the next CLK pulse and
counting will continue from there.
References:
1. "Intel 82C54 CHMOS Programmable Interval Timer" (PDF) (datasheet).

2. D.A. Godse; A.P. Godse (2007). Advanced Microprocessors. Technical

Publications. p. 74. ISBN 81-89411-33-0.
3. "8254/82C54: Introduction to Programmable Interval Timer". Intel Corporation.

External links:

 https://www.intel.com/
 https://www.tutorialspoint.com/