Outlines
Digital Logic Design (DLD) Preleminaries
Lecture 1 My Intro.
Class Norms
Dr. Jamshed Iqbal Words of Motivation
Associate Professor @ DLD
Department of Electrical Engineering
Policies
Book & Course Contents
Intro.
Fundamentals @ DLD
National University of Computer &
Emerging Sciences
My Intro
Academics:
PhD – Rob. (Italian Inst. of Tech., Italy)
MSc – Rob.& Automation (Helsinki U. of Tech., Fin.)
MSc – Space Rob. (Luleå Univ. of Tech., Sweden)
Preleminaries MSc – Elect. Engg. (UET, Taxila)
BSc – Elect. Engg. (UET, Lahore)
Professional Experience:
Teaching – 8 Yrs. (Italy, Pakistan)
R & D – 6 Yrs. (UK, Finland, Italy, Pakistan)
Publications: 1 Book, 2 Chap., 40 Journal, 28 Conf.
Class Norms Class Norms
Questions
Should be relevant to the topic of discussion, Use of comm. Resources
NOT from the topics which have been discussed
in previous lectures or to be discussed in future
Discipline Feedback
Strong disciplinary action will be
taken in case of any violation
Extreme cases to be reported in
Disciplinary Committee Fairness in grading
You have been well informed !!!
Punctuality & Attendance
Attendance can be called at ANY time in Lect. Respect and get respected!
Please do NOT come to me for attendance
compensation, whatsoever the reason is.
Words of Motivation Words of Motivation
Truth Table:
Strengths (I can)
Motivation (I will)
Be clear about aims and objectives
Ask yourself “WHY“???
Motivation for education?
Era of competition!
Input Gain Output
Output = Gain * Input
Words of Motivation
@ DLD
Course Policies Course Policies
Theory Marks Distribution:
Lecture Methodology:
Assignments: min (~5%)
Hybrid (Slides + W/Board)
Remaining: 45% Concept – Mostly from Slides
Final: 50% Calculation – Mostly on W/Board
PDF of Slides will be shared through SLATE
You are allowed to attend Lect ONLY in your Section
@ Quizzes & Assignments:
Quizzes will be surprised as well as announced
Late submission of Assignments – NOT allowed
Queries/Errors regarding Attendance/Marks:
Entertained ONLY within 2 weeks of uploading
What is New?
Hardware Description Language (HDL)
Project in Lab. (To be announced)
Sequence of topics may slightly vary w.r.t.
Text Book
Book (for perfect synch. with the Lab.)
Course Objectives
This course covers:
Basics of digital logic circuits and design
Understanding of Boolean algebra and number
systems
Fundamentals of combinational logic design and
Ref. Book sequential circuits
Intro. To Hardware Description Language (HDL)
This course serves as foundation for:
STRONG recommendation: Microprocessor Interfacing & Programming (MIP)
Buy hard copy of Text Book !!! Computer Architecture
Should be cheaper than one burger at Mcdonalds VLSI Design
You can use e-book ONLY for Ref. book Computer Organization
…
Why Learn DLD?
It‘s a Digital Age
ABC @ DLD
Communications
Multi-media
Manufacturing
Consumer electronics
Health care
Defense and security
Software
Automotive, etc
Life Changers
What is DLD?
Deals with building blocks of digital
systems
Of these 30 innovations , 10 are ?
directly related to advances in
Digital Logic and Solid State
(Intel)
Circuits;
Another 8 are the indirect
results of ICs.
Ref: http://knowledge.wharton.upenn.edu/article.cfm?articleid=2163
Three Levels
What logic gates are built from? Circuit level
The transistor is the workhorse of every Logic level
electronic device Chip level
Cct. Level (EDC, Physics)
5 layers of interconnections
Transistor
Physics, EDC
Digital building blocks
Chip level (VLSI, …)
Logic Level (DLD)
Advantages of Digital Systems Digital Systems
Cheap electronic circuitry Digital V/S Analog
Easier to calibrate and adjust
Immunity to noise
Noise added
Sender Receiver
Signal Signal Digital: Analog:
Only assumes discrete values Values vary over a broad range
continuously
Binary Number System
Only ‘0’ and ‘1’ digits
Binary Number System
Understanding Examp.
‘Yes’ or ‘No’
‘True’ or ‘False’
‘Presence’ or ‘absence’
Can be easily implemented in electronic cct.
How?
Transistor: ‘ON’ or ‘OFF’
Digital Systems
Concept of 'Discrete'
THANKS
JAMSHED.IQBAL@NU.EDU.PK
A digital system is a system that ROOM G-06 - EE DEPTT.
manipulates discrete elements information
represented internally in binary form
