Question Bank
1- Convert the following binary number to Decimal?
(a) 1100 (b) 1011 (c) 11100 (d) 110011.11 (e) 1011100.1010
2- Convert the following Decimal number to binary?
(a) 19 (b) 45 (c) 48 (d) 125 (e) 34 (f) 65 (g) 0.246 (h) 0.928
3- Convert each octal number to binary.
(a) (13)8 (b) (101)8 (c) (45600)8
4- Convert each decimal number to octal by repeated division by 8.
(a) (15)10 (b) (100)10 (c) (435)10
5- Convert each octal number to decimal.
(a) (12)8 (b) (27)8 (c) (103)8
6- Convert each hexadecimal number to binary.
(a) FAC1 (b) 53AD
7- Convert each binary number to Hexadecimal.
(a) 11010010110 (b) 111101110
8- Convert each decimal number to Hexadecimal by repeated division by 16.
(a) (100)16 (b) (600)16 (c) (268)16
9- Perform the Subtraction using the 1’s complement method.
(a) 1100110-1011001 (b) 0110101-1011001
10- Perform the Subtraction using the 2’s complement method.
(a) 0110101-1011001 (b) 1100110-1011001
11- Perform the addition using the 1’s complement method.
(a) 1101100+0100100 (b) 1011011+0010011
12- Perform the following octal addition
(a) (727)8+(137)8 (b) (472)8+(371)8
13. Write the output expression for each circuit in Figure.
14. Write the output expression for each circuit as it appears in Figure.
15. Apply DeMorgan’s theorems to each expression:
16. Apply DeMorgan’s theorems to the following:
17. Determine the output, X, for a 2-input AND gate with the input waveforms shown in Figure. Show the
proper relationship of output to inputs with a timing diagram.
18. The waveforms in Figure are applied to points A and B of a 2-input AND gate followed by an inverter.
Draw the output waveform.
19. The input waveforms applied to a 3-input AND gate are as indicated in Figure. Show the output waveform
in proper relation to the inputs with a timing diagram.
20. The input waveforms applied to a 4-input AND gate are as indicated in Figure. The output of the AND gate
is fed to an inverter. Draw the net output waveform of this system.
21. The input waveform at A is given for the two-input AND gates shown in Figure. Sketch the input waveform
at B that will produce the output at X.
22. Determine the logic level at W, X, Y and Z in Figure.
23. Draw the output waveform for the OR gate of Figure.
24. For the set of input waveforms in Figure, determine the output for the gate shown and draw the timing
diagram.
25. Determine the gate output for the input waveforms in Figure and draw the timing diagram.
26. Show that each gate will produce the same output for the given inputs.
27. Use a Karnaugh map to find the minimum SOP form for each expression:
28. Use a Karnaugh map to simplify each expression to a minimum SOP form:
29. Expand each expression to a standard SOP form:
30. Develop a truth table for each of the following standard SOP expressions:
31. Develop a truth table for each of the SOP expressions:
32. Develop a truth table for each of the standard POS expressions:
33. Develop a truth table for each of the standard POS expressions:
34. Use a Karnaugh map to reduce each expression to a minimum SOP form:
35. For the multiplexer in shown Figure, determine the output
for the following input states: D0 = 1, D1 = 0, D2 = 0, D3 = 1,
S0 = 0, S1 = 1.
36. If the data-select inputs to the multiplexer in Figure Problem (4) are sequenced as shown by the waveforms
in Figure, determine the output waveform with the data inputs specified in Problem (4).
37. The waveforms in Figure are observed on the inputs of a 74HC151 8-input multiplexer. Sketch the Y output
waveform.
The 74HC151 eight-input data selector/multiplexer
38. The waveforms in Figure are applied to the 4-bit parity logic. Determine the output waveform in proper
relation to the inputs. For how many bit times does even parity occur, and how is it indicated? The timing
diagram includes eight bit times.
39. For the parallel adder in Figure, determine the complete sum by analysis of the logical operation of the
circuit. Verify your result by longhand addition of the two input numbers.
40. Repeat Problem 39 for the circuit and input conditions in Figure.
41. The circuit shown in Figure is a 4-bit circuit that can add or subtract numbers in a form used in computers
(positive numbers in true form; negative numbers in complement form). (a) Explain what happens when the
Add/Subt. input is HIGH. (b) What happens when Add/Subt. is LOW?
42. Reduce the function specified in shown truth table to its minimum SOP form by using a Karnaugh map.
43. Use the Karnaugh map method to implement the minimum SOP expression for the logic function specified
in truth Table.
Problem 42
Problem 43
44. For the full-adder of, determine the outputs for each of the following inputs
(a) A = 0, B = 1, Cin = 0 (b) A = 1, B = 0, Cin = 1 (c) A = 0, B = 0, Cin = 0
45. What are the half-adder inputs that will produce the following outputs:
(a) = 0, Cout = 0 (b) = 1, Cout = 0 (c) = 0, Cout = 1
46. Determine the outputs of a full-adder for each of the following inputs:
(a) A = 1, B = 0, Cin = 0 (b) A = 0, B = 0, Cin = 1 (c) A = 0, B = 1, Cin = 1 (d) A = 1, B = 1, Cin = 1
47. The input waveforms in shown Figure are applied to a 2-bit adder. Determine the waveforms for the sum
and the output carry in relation to the inputs by constructing a timing diagram.
48. The following sequences of bits (right-most bit first) appear on the inputs to a 4-bit parallel adder.
Determine the resulting sequence of bits on each sum output.
A1 1010 B1 1001
A2 1100 B2 1011
A3 0101 B3 0000
A4 1101 B4 0001
49. Each of the eight full-adders in an 8-bit parallel ripple carry adder exhibits the following propagation delay:
A to and Cout: 20 ns B to and Cout: 20 ns Cin to : 30 ns Cin to Cout: 25 ns
Determine the maximum total time for the addition of two 8-bit numbers.
50. The waveforms in Figure are applied to the comparator as shown. Determine the output (A = B) waveform.
