Report #11

FET/MOSFET Characteristics
OBJECTIVE
1. Understating the structures and characteristics of JFETs.
2. Plotting the characteristics curves of a JFET.
3. Understating the structures and characteristics of MOSFETs.
4. Plotting the transfer characteristics curves of a MOSFET.
5. Implementing and measuring a MOSFET motor-speed circuit control.

DISCUSSION

Field-Effect Transistors (FETs)

The field-effect transistor (FET) is a semiconductor device which depends for its operation on
the control of current by an electric field and conducts the current with a single carrier, hole or
electron. According to the structure, there are two types of FETs, the Junction Field Effect
Transistor (JFET) and Metal Oxide Semiconductor FET (MOSFET). The FET differs from the BJT in
the following characteristics:

A. It is a unipolar device similar to vacuum tube.

B. It is immune from radiation.
C. It has an extremely high impedance, typically in mega ohms.
D. It is less noisy than a BJT or a vacuum tube.
E. It has no offset voltage at zero drain current, and makes an excellent signal chopper.
F. It provides great thermal stability than BJT.
G. Its key disadvantage is the relativity small GBP of the device compared to the BJT.
The structure and operation of the FET are different to those of the BJT. The current of the BJT
contains majority and minority carriers which flow through two p-n junctions, while the current
of the FET is only the majority carrier flowing in drifting. For the FET, its channel width can be
controlled by external electric field so that the magnitude of channel current is determined by
electric field. The magnitude of BJT collector current is controlled by ejected base current.

Either JFET or MOSFET, there are n-channel and p-channel FETs according to the channel type.
Basically the operating principles of the JFET and MOSFET are very similar; however, the input
resistance of the JFET is smaller than the MOSFET (up to 10 14) due to 8 pn-juction between the
gate and channel. Furthermore the MOSFET has many advantages in manufacturing so that the
MOSFET is more important than the JFET in microelectronics and circuits of JFET and MOSFET
devices.

The FET is a semiconductor device which delivers the current with a single carrier. The charge
carrier is a p-channel FET is hole, which in an n-channel FET is electron. Compared to the BJT,
the MOSFET which features smaller Gain-Bandwidth Product (GBP), higher input impedance,
and lower manufacturing complication, is suited for manufacturing the Large-Scale Integrated
(LSI) and Very Large-Scale Integrated (VLS) circuits.

Junction Field-Effect Transistors (JFETs)

The JFET device can be divided into p-channel and n-channel JFET. Fig shows the cross section
of a typical n-channel JFET structure. The JFET is a three-terminal device containing the source
(9) gate (G) and drain (D) terminals. The circuit symbol shown is the n-channel JFET. For p
channel JFET, the arrow at the gate points in the opposite direction. Generally a JFET can be
constructed as a gate-voltage-controlled variable resistor. Either end of the channel may be
used as a source or drain.

Fig. 26-1 N-Channel JFET structure, circuit symbol, and output characteristics

The voltage across drain source Vds, which results in drain current Id from drain to source. The
drain current passes through the channel surrounded by the p-type gate. Since the Gate-source
voltage VGs will reverse bias the gate-source junction, no gate current will result. The effect of
the gate-source voltage will be to create depletion region in the channel and therefore reduce
the channel width to increase the drain-source resistance resulting in less drain current.

We first consider the n-channel JFET operation with VGs=O V, the drain current l D Increases
linearly with the drain-source voltage V DS. The drain current through the n-material of the drain
source produces a voltage drop along the channel, which is more positive at the drain-gate
junction than at the source-gate junction. The reverse-bias potential across the p-n junction
causes a depletion region to form as shown in Fig. 26-1. When the V DS is increased, the Id
increases, resulting in a larger depletion region. As the voltage VDs is increased, the depletion
region is fully formed across the channel. Any further Increase in V DS, greater than the VDS(SAT) ,
will result in no Increase in the drain current , the current I d then remaining constant or
saturation and designated as lDSS. This is described in V GS=0 characteristic curve of Fig. 26-1.
With the reverse-bias voltage VGS Increased, the depletion region fully forms at a lower level of
drain current. If the gate-source voltage VGS is increased to the pinch-off value Vp or V GS(OFF), the
drain current reduces to 0, and the JFET is completely turned off. The pinch off voltage Vp, and
the saturation drain-source current ldss are two important parameters of the JFET device and
they are Indicated In the transfer characteristic curve of figure below.

Fig. 26-2 Transfer Characteristics of N-Channel JFET (VDS > VDS(sat))

JFET Drain Characteristics

The drain characteristics is a set of the curves for different values of V GS from OV to the pinch-off
voltage, Vp or VGS(OFF), the voltage at which the depletion region is formed without any drain
current and at which no drain current can occur. Figure below shows the typical n-channel JFET
drain characteristic curves plotted the actual drain current Id at different values of drain-source
voltage VDS for a range of gate –source voltage values VGS. The drain characteristics contains the
ohmic region, saturation region, avalanche region and cutoff region.
 Fig 26-3 Drain Characteristics Curve of N-Channel JFET

For VGS =O V, the curve plotted shows that the drain current increases as V DS is increased until a
point (VDS= 4 V) at which the current reaches saturation and I DSS= 10 mA. From the previous
discussion we know that the internal depletion region acts to limit the drain current. If the gate-
source voltage is set at VGS= -1V, the current increases as VDS is increased until a saturation
level is reached this time at a lower level than for VGs = 0 V, since the depletion region, starting
partly formed due to VGS = -1 V, fully forms at a lower level of drain-source current. If the gate-
source voltage is Increased beyond the pinch-off value (-5 V), the drain current reduces to and
the

JFET device is completely turned off. Since the drain current is a single carrier, each
characteristic curve therefore passes through the origin.

JFET Transfer Characteristics Curve

The transfer characteristic curve also called the transconductance curve is a plot of drain
current ID as a function of gate-source voltage V GS, for the constant value of drain source voltage
VDS. The transfer curve of an n-channel JFET is shown in the figure is plotted from drain
characteristic curves of figure above and mathematically expressed by the parabolic
approximation:
Metal-Oxide-Semiconductor FETs (MOSFETs)
A field-effect transistor can be constructed with the gate terminal insulated from the channel.
The popular Metal-Oxide semiconductor FET (MOSFET), or sometimes called the insulated Gate
Field Transistor (GFET), is constructed d as either a depletion MOSFET or Enhancement
MOSFET. In the depletion –mode construction a channel is physically constructed and current
between drain and source will result from a voltage connected across the drain-source
terminals. The EMOS structure has no channel formed when the device is constructed .Voltage
must be applied at the gate to develop a channel of charge carriers so that a current results
when a voltage is applied across the drain-source terminals.

Since the MOSFET device has the feature of low noise and good stability it is widely used in high
input impedance and high voltage amplification circuits. The very thin Insulating layer between
the gate and substrate of a MOSFET can easily be punctured if an excessive voltage is applied
.Human body can build up extremely large electrostatic charges due to electrostatic discharge
would occur, resulting in a possible arc across the thin insulating layer causing permanent
damage. To avoid this damage, the MOSFET terminals are usually shorted with a conductive
ring or conductive foam in shipping and the conductive ring must be removed after soldering.
Fig.26-5 shows the structure and characteristics of an n-Channel MOSFET. Similar to the JFET, It
can be considered as a gate-voltage controlled variable resistor and it is a three-terminal device
contain the source (S), gate (G) and drain (D) terminals. The main difference Between the
MOSFET and JFET is an oxide layer between the gate and p-substrate (not a p-n Junction) of a
NMOSFET. Therefore the MOSFET’s input resistance is much higher than the JFET.

Fig.26-6 shows the transfer characteristics of depletion and enhancement NMOSFETs. The
depletion MOSFET of figure 26-6(a) is shown to operate with either positive or negative gate-
source voltage negative values of VGS reducing the drain current until the pinch off voltage Vp
,after which no drain current occurs,. The transfer Characteristics is the same for negative gate-
source voltages, but it continues for positive values of V GS. Since the gate is isolated from the
channel for both negative and positive values of V GS, the device can be operated with either
polarity of VGS or no gate current resulting in either case.

1. Depletion MOSFET
Fig, 26-7 shows the structure and circuit symbol of n- channel depletion MOSFET.
Source and drain are made by the higher doped n- type semiconductor material and the
channel is a lower-doped n-type region. A metal layer is deposited above the n-channel on a
layer of silicon dioxide (SiO2) which is an insulating layer. This combination of a metal gate on
an oxide layer over a semiconductor forms the depletion MOSFET device. The gate source
voltage is either positive or negative. For the n-channel depletion

MOSFET negative gate-source voltages push electrons out of channel to deplete the channel
and a large enough negative gate-source voltage will pinch channel. Positive gate-source
voltage on the other hand will result in increase in the channel size allowing more charge
carriers and therefore granter channel current to result.
The circuit symbol in Fig. 26-7 shows the addition of a substrate terminal on which the device
type is indicated, the arrow here indicating a p-saturate and thus N-Channel device.

2.Enhancement MOSFET
Fig. 26-8 shows the structure and circuit symbol n-channel enhancement MOSFET. The
substrate is a lower-doped p-type semiconductor material and source and drain are higher-
doped n-type semiconductor. It has no channel between drain and source as part of the
basic device structure. Application of positive gate source voltage will repel holes in the
substrate region under gate leaving a depletion. When the gate voltage is sufficiently
positive, electrons are attracted into this depletion region making it then act as an n-
channel between drain and source. There is no drain current until the gate-source voltage
exceeds the threshold voltage Vt result increased drain current. The transfer characteristic
is described in Fig 26-5b .Note that no value IDss can be associated with an enhancement
MOSFET because 'no drain current occurs with VGs=0 V. Although the enhancement
MOSFET is more restricted in operating range than is the depletion device. The
enhancement device is very useful in large-scale integrated circuits in which the simple
construction and smaller size make it a suitable device
 Fig. 26-8 Enhancement MOSFET Structure and circuit Symbol

1. Complementary MOSFET (CMOS)

A complementary MOSFET (CMOS) connects enhancement PMOS and NMOS FETs into a
complementary device which is primarily used in digital circuits. The input is
internallyconnected in common to the gate of both PMOS and NMOS FETs. A high input
voltage drives the PMOS off and the NMOS on. A low input voltage will correispondingly
drives the PMOS on and the NMOS off.

2. Power MOSFET
The power Metal-Oxide-Semiconductor FET is an unipolar and voltage-controlled device.
The power MOSFET has the features of fast switching speed good high-frequency
characteristics high impedance, small drive power, excellent thermal stability, no second
breakdown, wide safe Operating Area (SOA), and high operating linearity, etc. Since the key
advantages of small size and the light weight, the power MOSFET provides a high speed,
high power, high voltage, and high gain device. The power MOSFET is widely used in high-
power switching applications such as power supplies, converters and PWM motor controls.
Structure of Power MOSFET
Power MOSFET is an integrated power device which contains tens of thousands small
MOSFET interconnected in parallel. Fig: 26-9 shows the typical structure of an n-channel
power MOSFET. Two higher-doped n+ regions are constructed as source and drain
terminals. An insulting layer (Si02) exists between gate and channel.
 Fig. 26-9 N-Channel Power MOSFET structure

The power MOSFET shown in Fig. 26-9 is a 4-layer sandwich configuration of n+(n) pn+.The
lower-doped n- region is a drift region which increases the device voltage ratting in the
device, two back-to-back pn-junctions exist between drain and source if no gate voltage is
applied, the device is always in off state whenever the drain-source voltage is either positive
or negative.

Static Characteristics of Power MOSFET

Power MOSFET's output characteristic curves have two distinct operating regions: a constant-
resistance region and a constant current region. In the constant-resistance region, the drain
current is direct proportion to the increase in the drain-source voltage until the drain-source
voltage reaches at its pinch-off 'voltage. Beyond this point, the drain current remains constant
and the device operates in the constant-current region.

When the power MOSFET is used as an electronic switch, the drain-source voltage drop is
proportional to the drain current, that is, the MOSFET operates in the constant resistance
region and it can be considered as a resistive component. The on-state drain-source resistance
RDS(on) is the key parameter which determines the power losses at a given drain current. The
drain current starts to flow at the applied gate voltage over the threshold voltage (typically 2 to
4 V). Once the gate-source voltage is over the, threshold voltage, the relationship between
drain current and gate voltage is approximately linear.
The common-source forward transconductance gm or gfs specifies the power MOSFET ac
amplification. It is measured with drain-source shorted and indicates how much the ac drain
current will change due to an applied ac gate-source voltage.

Safe Operating Area (SOA) of Power MOSFET

As mentioned before a MOSFET is a majority-carrier device and therefore it has a positive
temperature coefficient of the resistance and its second breakdown effect is minimal compared
to that of a BJT d vice. A comparison of the forward-biased safe operating areas is shown in Fig.
26-10. The dc and pulse SOAs of power MOSFET are superior to those of the BJT under dc (solid
line) and pulse (dotted line) operating conditions.

Full- Bridge ZVS MOSFET

In recent years, the power requirements of power supply systems are higher and higher,
especially in telecommunication and server applications .These requirements push the power
electronics industry to develop the power supply-equipment with higher power density and
reliability. This is a strict challenge to design engineers how to promote the power density from
5.7 W/in3 to 10 W/in3. The use of the phase-shifting Zero-Voltage-Switching (ZVS) technique nay
be a good solution of this problem. With ZVS design, higher power density and reliability can be
obtained. In designs, the ZVS technique can minimize the switching losses and increase
relatively higher switching frequency implies higher switching frequency implies that the
smaller size and shorter response time of filtering devices may be used so the circuit size is
reduced and the power density is promoted. Lower switching loss means that a lower
temperature rise can be obtained so that the requirement of heat sink is lowered. In addition,
ZVS operation can reduce the effects of transient dv/dt and di/dt, and increase reliability of
power supply equipments. However MOSFET in a full-bridge ZVS converter may be failure
under some condition such as slow recovery body diode, especially at low reserve voltage
condition. Another case of MOSFET failure is the puncture-through problem of C dv/dt. When
the MOSFET is forced ON or OFF, ZVS converter could be failure under no load or light
conditions.
In brief, the ZVS technique maximizes efficiency and enables higher power output in switch-
mode power supply (SMPS) circuits

MOSFET Body Diode in ZVS Circuit

The research for the MOSFET operation in ZVS circuits leads the development of MOSFET
technology to a new generation of fast built-in body diode. The main purpose are to lower the
reverse recovery time of body diode, to enhance the permission of dv/dt to minimize puncture
through effect of Cdv/dt, and to increase the reliability in high frequency and higher power
phase shifting ZVS applications without pay of efficiency.
In a full-bridge ZVS circuit, if the reverse recovery process of built-in body diode doesn't
complete before the MOSFET is turned off transient dv/dt will result in failure. When ZVS work
on higher frequency this problem becomes worse because built in body diode becomes shorter.

Basically the ZVS converter cannot switch at zero voltage under a light-load condition so that
the MOSFET in on-state will be forced to turn off, similar to the operation of forced-switching
full-controlled bridge circuit, and the Cdv/dt transient will create a voltage surge at the gate and
will result in a damage to the device.

In no-load or light-load conditions, the reliability of ZVS circuits will be improved by enhancing
the permission of Cdv/dt. The failure of Cdv/dt puncture through can be improved by reducing
the Qgd/Qgs1 ratio and internal gate resistance Rg.

Description of Experimental Circuit

Fig. shows the circuit for JFET/MOSFET characteristic measurements on Module KL-53015. Fig.
26-12 shows the MOSFET motor-speed control circuit.
The 2SK30A is a silicon n-channel JFET. Its major electrical specifications include, gate to drain
voltage VGDS = -50 V, gate current IG =10mA drain power dissipation PD = 100 mW, drain to
source leakage current IDSS=0.3 mA min to 6.5 mA max. (test conditions: VDs=10 V, VGs=0 V).
The 2SK2698 is a silicon n-channel MOSFET. Its major electrical specifications include: drain to
source voltage VDSS = 500 V, drain current ID = 15 A (continuous) or 60A (pulsed), drain power
dissipation PD= 150 W, drain to source on resistance RDS(on)= . 0.35 ohm (test condition VGS=
10 V, ID = 7 A), gate to source threshold voltage Vth= 2. V min and 4v max (test conditions:
VDS=10 V, ID=1 mA).
The 12-V AC supply input is full-wave-rectified 'by the bridge rectifier BR1 capacitor-filtered by
the capacitors C1 and C2 and dust voltage about ±17 VDC to supply the power to the JFET or
MOSFET. Zener diodes ZD1 and ZD2 regulate the ±17 VDc to ±6.1 V for gate-bias and the
potentiometer VR2 is used to control the gate bias voltage. When connect plugs are placed in
positions 1, 4. 6. and 7. the JFET is constructed as common source configuration and a negative
voltage is applied to the gate.
When the connect plugs are placed in positions 2, 4, 6, and 7 the JFET is constructed as
common source configuration and a positive voltage is applied to the gate.

For the MOSFET characteristic measurements, the connect plugs in positions 1, 4, 5, and 8 to
construct the MOSFET as common source configuration and to apply a negative voltage at the
gate. When the connect plugs are placed in positions 2, 4, 5, and 8, the MOSFET is configured as
common source configuration and a positive voltage is applied at the gate. For drain current lD,
measurement, the required gate-source voltages are provided by adjusting the potentiometer
VR2. And finally, the characteristic will be plotted according to the measured results.
Conclusion :

In this experiment there are two objectives, understating the structures and characteristics
of JFETs and MOSFETs. In experimental circuit, when we apply 12V AC voltage then bridge
rectifier converts it into pulsating DC voltage then capacitors smooths the voltage as pure DC.
Zener diodes changes ±17 VDc to ±6.1 V for gate bias and VR2 used to control gate bias voltage.
When 1, 4, 6 and 7 connections are in contact then the JFET configuration is common source a
negative voltage is applied to the gate but when 2, 4, 6 and 7 are in contact then the
configuration will be same but the applied voltage to the gate is positive.
When measuring MOSFET characteristics, the position 1, 4, 5 and 8 are in contact then the
configuration of MOSFET is common source and a negative voltage is applied at gate but when
2, 4, 5 and 8 are in contact then the configuration will be same but the applied voltage to the
gate is positive.