International Conference on Electrical, Electronics and Civil Engineering (ICEECE'2011) Pattaya Dec.

2011

Hardware Implementation of PCI Interface

Using Verilog & FPGA
Iqbalur. Rahman Rokon Towsif. Sazzad, Samilat. Kaiser

distinct interfacing pins and according to these pins we need

Abstract - PCI (Peripheral Component Interconnect) is a computer to interface with other devices.
bus for attaching hardware devices in a computer. Work on PCI first
began at Intel's Architecture Development Lab, circa 1990. PCI The PCI bus has 4 main characteristics:
provides direct access to system memory for connected devices, but  Synchronous: bus uses one clock. PCI clock runs at
uses a bridge to connect to the frontside bus and therefore to the 33MHz by default but can run lower to save power or
CPU. PCI bus traffic is made of a series of PCI bus transactions. higher (66MHz) if the hardware supports it.
Each transaction is made up of an address phase followed by one or  Transaction/Burst oriented: We start a
more data phases. The direction of the data phases may be from transaction>specify the starting address>send as
initiator to target (for write transaction) or vice-versa (for read
transaction). A PCI interface will connect any generic devices to the
many data we want>end the transaction
PCI bus. This interface will create the communication between  Bus mastering: transactions work in a master-slave
master and slave devices. The interface will read the command of the relationship. A master is an agent that initiates a
master and send corresponding response to the master. Generally, the transaction (can be a read or a write).
master initiates and controls all communication that takes place over  Plug-and-play: host-CPU/host-OS can: Determine
the bus. Our interface design includes read and write operations and the identity of each PCI board in a PCI bus,
will be able to communicate to register and RAM through the
PCI.PCI has distinct interfacing pins and according to these pins we
determine the abilities/requirements of each board,
made interface with Register and RAM. and Relocate each board memory space.[2]

Keywords— PCI Protocol, PCI Interface, VLSI, FPGA, Verilog.

PCI timing:
I. INTRODUCTION PCI specifies timing related to its clock.
With a 33MHz clock, we have:
HE form PCI stands for Peripheral Component
T Interconnect, which suitably describes what it does. PCI
was designed to satisfy the requirement for a standard
• 7ns/0ns Tsu/Th (setup/hold) constraint on
inputs
interface for connecting peripherals to a PC, capable of
• 11ns Tco (clock-to-output) on outputs.[2]
sustaining the high data transfer rates needed by modern
graphics controllers, storage media, network interface cards II. INTERFACE I/O SIGNALS
and other devices. [1]

Although many computer users think of PCI as a way of

laying out electrical wires, it is actually a complete set of
specifications defining how different parts of a computer
should interact. PCI bus is an improved bus for PC compatible
computers. It is faster than the previous buses. And it can be
expandable to both 32-bit and 64-bit. The PCI specification
covers most issues related to computer interface. PCI has

Iqbalur. Rahman Rokon is a Faculty member in North South University,

Dhaka, Bangladesh. Former Sr. Engineer, VLSI Chip Research and
Development (R&D), Emulex Corporation, California, USA; Fig. 1 Interface Block
(Phone: +88-01726246189 ; e-mail: irahman@northsouth.edu ).
Towsif Sazzad is a graduate from North South University, Dhaka, • Frame: It is the activation signal. When it is low the
Bangladesh. He is now working as a Senior SQA Engineer in Speedwell device is ready to perform.[3]
Softtech LTD, Dhaka, Bangladesh; (e-mail: towsifsazzad@gmail.com ).
Samilat Kaiser is a graduate from North South University, Dhaka, • Command or Byte Enable (C_be[3:0]): It is a 4 bit
Bangladesh. She is now working as a Pre-Sales Consultant in Tech one bus. It sends 0010 for read command and 0011for
Global, Dhaka, Bangladesh (e-mail: samilatkaiser@gmail.com ). write command to PCI.[3]

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 International Conference on Electrical, Electronics and Civil Engineering (ICEECE'2011) Pattaya Dec. 2011

• Address (Ad[31:0]): It is a 32 bit bus. Both address V. TIMING DIAGRAM

bus and data bus are multiplexed in this same bus.[3]
• Initiator Ready(irdy): Initiator ready is low when the A. Read Transaction:
master device is ready to make transaction.[3]
1) The following timing diagram illustrates a read
• Target Ready(trdy): ): Target ready is low when the
transaction on the PCI bus:
slave device is ready to make transaction.[3]
• Device Select(Devsel): The target asserts devsel low
as an acknowledgement that it has positively decoded
the address. [3]
• CE: When it goes low, RAM is active to make the
transaction.[4]
• r_w: when it is high, read operation occurs. When
low, write operation occurs to Ram.[4]
• Read_en: When read enable is high data is read from
the Register.
• Write_en: When write enable is high data is written to
Register.

III. ADDRESS MAPPING

In our design, the method that we have applied to select the

Slave devices is called address mapping. We have divided the
address of our Master (PCI) device into two parts. One is for
Ram and another is for Register. Our Master (PCI) device has
a 32-bit address from which we can have 2^32 that means
4294967296 number of addresses. To map the address we
have taken the most significant 4 bits. And by these 4 bits we
can have 16 combinations starts from 0000 and ends up with Fig. 3 Read Transfer Diagram
1111. From these 16 combinations, we have chosen the first
12 combinations for the RAM and the rest of the 4 The following is a cycle by cycle description of the read
combinations for REGISTER. So the address for RAM is transaction:
selected from 0000 to 1011 and the address for REGISTER is
• Cycle 1 - The bus is idle.
selected from 1100 to 1111. Finally the address ranges for
these two slave devices are: • Cycle 2 - The initiator asserts a valid address and
Address Range for RAM: 0000_0000 to 1011_1111 places a read command on the C/BE# signals. This is
Address Range for REGISTER: 1100_0000 to 1111_1111 the address phase.
IV. SIMULATION ENVIRONMENT • Cycle 3 - The initiator tri-states the address in
preparation for the target driving read data. The
initiator now drives valid byte enable information on
the C/BE# signals. The initiator asserts IRDY# low
indicating it is ready to capture read data. The target
asserts DEVSEL# low (in this cycle or the next) as
an acknowledgment it has positively decoded the
address. The target drives TRDY# high indicating it
is not yet providing valid read data.

• Cycle 4 - The target provides valid data and asserts

TRDY# low indicating to the initiator that data is
valid. IRDY# and TRDY# are both low during this
cycle causing a data transfer to take place. The
Fig. 2 Simulation Environment initiator captures the data. This is the first data phase.
PCI interface is a device, which acts as a transitional
medium between Master/Initiator and Slave/Target devices. In • Cycle 5 - The target deasserts TRDY# high
our design, we have used PCI as the Master/Initiator and indicating it needs more time to prepare the next data
RAM and REGISTER as the Slave/Target devices. Here, we transfer.
can read data from RAM and REGISTER to PCI and also can
write data from PCI to RAM and REGISTER.

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 International Conference on Electrical, Electronics and Civil Engineering (ICEECE'2011) Pattaya Dec. 2011

• Cycle 6 - The second data phase occurs as both • Cycle 4 - The initiator provides new data and byte
IRDY# and TRDY# are low. The initiator captures enables. The second data phase occurs as both
the data provided by the target. IRDY# and TRDY# are low. The target captures the
write data.
• Cycle 7 - The target provides valid data for the third
data phase, but the initiator indicates it is not ready • Cycle 5 - The initiator deasserts IRDY# indicating it
by deasserting IRDY# high. is not ready to provide the next data. The target
deasserts TRDY# indicating it is not ready to capture
• Cycle 8 - The initiator re-asserts IRDY# low to the next data.
complete the third data phase. The initiator captures
the data provided by the target. The initiator drives • Cycle 6 - The initiator provides the next valid data
FRAME# high indicating this is the final data phase and asserts IRDY# low. The initiator drives
(master termination). FRAME# high indicating this is the final data phase
(master termination). The target is still not ready and
• Cycle 9 - FRAME#, AD, and C/BE# are tri-stated, as
keeps TRDY# high.
IRDY#, TRDY#, and DEVSEL# are driven inactive
high for one cycle prior to being tri-stated.[5]
• Cycle 7 - The target is still not ready and keeps
TRDY# high.
A. Write Transaction:
The following timing diagram illustrates a write • Cycle 8 - The target becomes ready and asserts
transaction on the PCI bus: TRDY# low. The third data phase occurs as both
IRDY# and TRDY# are low. The target captures the
write data.

• Cycle 9 - FRAME#, AD, and C/BE# are tri-stated, as

IRDY#, TRDY#, and DEVSEL# are driven inactive
high for one cycle prior to being tri-stated.[5]

VI. FINITE STATE MACHINE

Fig. 4 Write Transfer Diagram

The following is a cycle by cycle description of the read Fig. 5 State Machine
transaction:
• Cycle 1 - The bus is idle. S0 = State_idle
S1 = State_take_address
• Cycle 2 - The initiator asserts a valid address and S2 = State_take_data
places a write command on the C/BE# signals. This S3 = State_semd_address
is the address phase. A. State_idle:
In this state all the signals are in idle mode. Or if they are
• Cycle 3 - The initiator drives valid write data and not in idle state then we are reseting all the signals to idle
byte enable signals. The initiator asserts IRDY# low state. That means all the signals are inactive to perform
indicating valid write data is available. The target operation and wait for the master device activation signal.
asserts DEVSEL# low as an acknowledgment it has When the Frame signal goes low, it activates the master
positively decoded the address (the target may not device that means the PCI is now active to read or write data
assert TRDY# before DEVSEL#). The target drives to slave devices. And just the moment frame goes low, the ad
TRDY# low indicating it is ready to capture data. signal works as an address bus. After this happen the device
The first data phase occurs as both IRDY# and changes its state and put the address value into the address
TRDY# are low. The target captures the write data. buffer (addr_buff). And if it is find that the frame is not low it

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 International Conference on Electrical, Electronics and Civil Engineering (ICEECE'2011) Pattaya Dec. 2011

remains in the idle state. After getting the frame low it sends a
read or writes command by the command bus and stays in the
next state.

B. State_take_address:
The second state is the state take address. If irdy changes its
state from idle state that is 1, it also changes the state and goes
to the next state which is state take data. After changing the
state it makes the address acknowledgement signal high and
again store the ad value into a data buffer (data_buff). At that Fig. 6 Altera DE1 Board
time the ad bus works as a data bus. But if the irdy signal is
VIII. SIMULATION RESULTS
not low then it waits for this signal to be low. And if the frame
again changes its state from low to high, it goes back to the
idle state.

C. State_take_data:
The third state is the state take data and if it is found that
devsel and trdy are low here and address acknowledgement is
given (addr_ack = 1), it makes the data acknowledgement
high and after this it changes its state to the next state. But if
the signals devsel and trdy are not low, it goes back to the
previous state.

D. State_send_address:
The fourth and final state is the state send ad. In this state at
first it checks that weather it is a write transaction or a read
transaction and which of the slave devices would be selected.
If it is a write transaction and the slave device is Ram, then it
makes the other internal signals as its need and makes the Fig. 7 Simulation waveform of write data to RAM
Ram’s activation signal ‘chip select’ (cs) as low and also
make the rd_wr (we) low. And thus the transaction occurs.
Again if it is a read operation from Ram, then again it makes
the other internal signals as its need and makes the Ram’s
activation signal ‘chip select’ (cs) low and r_w (we) high.
Thus a read transaction performs.
Again if Register is selected as the slave device and writes
command is send it makes the other internal signals as its need
and write the data to Register. And if it is a read command
send to Register, it also does the same thing and the data
would be read from Register. This process will continue until
or unless the frame signal goes high. If it goes high, then it
stops the transaction and goes back to the idle state.

VII. SIMULATION AND IMPLEMENTATION

For our simulation process, we have used Xilinx 9.2i.For
synthesis and implementation; we have used Xilinx9.2i and
Fig. 8 Simulation waveform of write data to RAM (cont.)
Altera DE1 development and Education board.

A. FPGA Board Used:

The purpose of the Altera DE1 Development and Education
board is to provide the ideal vehicle for advanced design
prototyping in the multimedia, storage, and networking. [6]

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 International Conference on Electrical, Electronics and Civil Engineering (ICEECE'2011) Pattaya Dec. 2011

should keep it relevant well into the next century. Originally

conceived as a mechanism for interconnecting peripheral
components on a motherboard, PCI has evolved into at least a
half dozen different physical implementations directed at
specific market segments yet all using the same basic bus
protocol. In the form known as Compact PCI, it is having a
major impact in the rapidly growing telecommunications
market.
Though in our project we have made an interface with register
and RAM but this will work for any generic device in the PCI
network. We hope that this project will help the further PCI
related invention. Technologies are becoming smarter and
Fig. 9 Simulation waveform of Read data from RAM
compact day by day, so we hope PCI protocol and PCI
IX. SYNTHESIS RESULTS interface will add new dimension in that trend. This interface
will play a remarkable role with its significant speed and
reliability.

ACKNOWLEDGMENT
All praises to Allah, the Almighty, the most gracious, the
most merciful, benevolent, without whose help, this work
would not have been possible. We would like to express our
gratitude to all those who gave us the possibility to complete
this project.
We want to thank Mr. Nahid Mushfique Jawad, who
supported us in our project work. He had remained with us
throughout the research work. We want to thank him for all
his help, support, interest and valuable hints. We also want to
thank Reasat Chowdhury for his selfless concern. We want to
thank our parents and other family members for their gallant
Fig. 10 Interface Block Diagram form Xilinx Schematic concern. Finally, we want to thank the Department of
Electrical Engineering and Computer Science of our
prestigious North South University, Bangladesh for giving us
such an opportunity to carry on our research work.

REFERENCES
[1] Tech-pro.net. (n.d.). Retrieved August 5, 2010, from tech-pro.net:
http://www.tech-pro.net/intro_pci.html
[2] fpga4fun. (2010, spetember 07). Retrieved september 07, 2010, from
fpga4fun: http://www.fpga4fun.com/PCI1.html
[3] PCI Local Bus Technical Summary. (2010, october 10). Retrieved october
10, 2010, from techfest: http://www.techfest.com/hardware/bus/pci.htm
[4] Figure Block Diagram of Static RAM Table Truth Table . (2010, july 27).
Retrieved july 27, 2010, from docstoc:
http://www.docstoc.com/docs/4219029/Figure-Block-Diagram-of-Static-
RAM-Table-Truth-Table
Fig. 11 Internal Logic circuit diagram of the Interface module [5] PCI Bus Timing Diagram. (2010, august 17). Retrieved august 17, 2010,
from Xilinx schematic from silverhawk: http://silverhawk.net/notes/tutorials/hardware/pci-
timing.html
[6] Altera DE1 board. (n.d.). Retrieved december 10, 2010, from terasic:
X. CONCLUSION http://www.terasic.com.tw/cgi-
Today’s computer systems, with their emphasis on high bin/page/archive.pl?Language=English&No=83
resolution graphics, full motion video, high bandwidth
networking, and so on, go far beyond the capabilities of the
architecture that ushered in the age of the personal computer
in 1982. Modern PC systems demand high performance
interconnects that also allow devices to be changed or
upgraded with a minimum of effort by the end user. In
response to this need, PCI has emerged as the dominant
mechanism for interconnecting the elements of modern, high
performance computer systems. It is a well thought out
standard with a number of forward looking features that

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