USOO68O1157B2

(12) United States Patent (10) Patent No.: US 6,801,157 B2

(54) GUIDED WAVE RADAR LEVEL 2001/0050629 A1 * 12/2001 Benway et al. ............. 342/124
TRANSMITTER
OTHER PUBLICATIONS
(75) Inventor: Kevin M. Haynes, Lombard, IL (US) DKE Deutsche Kommission Elektrotechnik Elecktronik
(73) Assignee: Magnetrol International, Inc., Informationstechnik DIN und VDE, Electrical appara:
Downers Grove, IL (US) tus for potentially eXpolsive atmosphereS-Intrinsic safety
s European Standard EN 50020, “Standard for Intrinsic
(*) Notice: Subject to any disclaimer, the term of this Safety”, 1994, pp. 22 and 25–27.*
p a --
is Sh adjusted under 35
y U dayS.
* cited by examiner
Primaryy Examiner John B. Sotomavor
y
(21) Appl. No.: 10/642,257 ASSistant Examiner Isam Alsomiri
1-1. (74) Attorney, Agent, or Firm- Wood, Phillips, Katz, Clark
(22) Filed: Aug. 15, 2003 & Mortimer
(65) Prior Publication Data (57) ABSTRACT
US 2004/0066324 A1 Apr. 8, 2004 A guided wave radar measurement instrument comprises a
Related U.S. Application Data probe defining a guided wave radar transmission line. A
(60) Provisional application No. 60/415,489, filed on Oct. 2, pulse circuit is connected to the probe for generating a very
2002. fast Stream of pulses on the transmission line and receiving
7 reflected pulses returned on the transmission line. The
(51) Int. Cl." ................................................ G01S 13/08 reflected pulses represent a characteristic of a material being
(52) -rr. 342/124; 342/198 measured. An equivalent time Sampling circuit is connected
(58) Field of Search ................................. 342/124, 198; to the pulse circuit operable to Sample reflected pulses tO
73/290 V, 290 R; 340/621, 624; 324/124, build a time multiplied picture of the reflected pulses and
629, 644; 367/189,908 comprises a ramp generator circuit generating a Saw tooth
ramp Signal used to Selectively delay Sampling reflected
(56) References Cited pulses to build the time multiplied picture. In one aspect of
U.S. PATENT DOCUMENTS the instrument, the saw tooth ramp signal has a controlled
ramp Start for each cycle and retrace at an end of the cycle.
5,233,352 A 8/1993 Cournane ................... 342/124 A processing circuit is connected to the equivalent time
5,596,325 A : 1/1997 Maas .......................... 342/28 Sampling circuit for Selectively controlling ramp Start for
g? A : re E. ME,
2- - 2
al. - - - 7;2.5
CIOlle C al. . . . . . . . . . . . . . . .
each cycle and measuring round trip travel time for a pulse
6,137,438 A * 10/2000 McEwan .................... ... from the pulse circuit.
6,249.244 B1 6/2001 Heidecke .................... 342/124
6,320,532 B1 11/2001 Diede ......................... 342/124 8 Claims, 9 Drawing Sheets

50 52 54
48
PULSE TRANSMIT SAFETY
REPETITION PULSE BLOCKING 1.
CLOCK INPUT SHAPER CAPACTORS

SAWTOOTH WOLAGE
RAMP CONTROLED 24
GENERATOR PULSE DELAY
CIRCUITS GENERATOR

RECEIVE EQUIVALENT
PULSE TIME
SHAPER SAMPLER
46

TO SIGNAL
PROCESSING
CIRCUITS
U.S. Patent Oct. 5, 2004 Sheet 1 of 9 US 6,801,157 B2

In 1"

FIG. 1
U.S. Patent Oct. 5, 2004 Sheet 2 of 9 US 6,801,157 B2
U.S. Patent Oct. 5, 2004 Sheet 3 of 9 US 6,801,157 B2

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U.S. Patent Oct. 5, 2004 Sheet 4 of 9 US 6,801,157 B2

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U.S. Patent Oct. 5, 2004 Sheet 7 of 9 US 6,801,157 B2
U.S. Patent Oct. 5, 2004 Sheet 8 of 9 US 6,801,157 B2

- - t> =OOnS
Reset Ra mp 70mS- t = 4mS

Ramp

- -Sample Time
BASELINE - -t- (0.2ms
SAMPLE f
Z
Analog Signal Fiducia f Retrace
TWIN ROD level
END OF
PROBE : Deadzone E.
Enable Level
Detect

triot, Hi
! --Ticks
NEP- - - - Ticks: -
Enable Blanking
; : Time ; ; ; ;
T:T2:T3: T4: T5: T6: T7: T8:
Fixed Threshold - - - GNO= 0 HGH DELECTRIC
GNO GNO=1 OW DELECTRIC
PB-o
GN = O ALWAYS

FIG. 8
U.S. Patent Oct. 5, 2004 Sheet 9 of 9 US 6,801,157 B2

Ramp
End of Ramp
BASELINE
sm
--, -i,0.2ms
-
SAMPLE Z
; Fiducial Edit: ;
Analog Signal
A.
? Probe Retrace
shire ; : Nozzie noise WLevel :
PROBE Deadzone; :
Enable Level :
Time
Detect it iTicks
Fid
LEVELDATA Ticks h Retrace
Ramps
'y.
Ticks
E --
ENABLE
T2:T3 T4: T5: T6:T7. T8:
Fied Threshold : ; ; ; GNO=0 LOW SENSTIVITY
L
GNO GNO= HIGH SENSTIVETY
H
GN
 US 6,801,157 B2
1 2
GUIDED WAVE RADARLEVEL The present invention is directed to overcoming one or
TRANSMITTER more of the problems discussed above, in a novel and Simple
C.
CROSS REFERENCE TO RELATED
APPLICATION SUMMARY OF THE INVENTION
This application claims priority of Provisional Applica In accordance with the invention there is provided an
tion No. 60/415,489, filed Oct. 2, 2002. improved, relatively low cost guided wave radar measure
ment instrument.
FIELD OF THE INVENTION There is disclosed in accordance with one aspect of the
This invention relates to an apparatus utilizing guided invention a process instrument comprising a housing and an
wave radar for measuring the condition or characteristics of active Sensing element for Sensing a characteristic of a
a material, and more particularly to improvements in level process. The control circuit is disposed in the housing and is
measurement. electrically connected to the active Sensing element for
15
measuring the Sensed characteristic. A Safety barrier com
BACKGROUND OF THE INVENTION prises a blocking capacitor barrier electrically connected
Knowledge of level in industrial process tanks or vessels between the control circuit and the active Sensing element.
has long been required for Safe and cost-effective operation The active Sensing element may comprise a guided wave
of plants. Many technologies exist for making level mea radar transmission line or a capacitance probe.
Surements. These include buoyancy, capacitance, ultrasonic It is a feature of the invention that the blocking capacitor
and microwave radar, to name a few. Recent advantages in barrier comprises a plurality of Series connected high Volt
pulsed radar, also known as ultra-wide band (UWB) radar, age capacitors.
in conjunction with advances in equivalent time Sampling There is disclosed in accordance with another aspect of
(ETS), permit development of low power and low cost time the invention a guided wave radar measurement instrument
domain reflectometry (TDR) devices. 25 comprising a probe defining a guided wave radar transmis
In a TDR instrument, a very fast stream of pulse with a Sion line. A pulse circuit is connected to the probe for
rise time of 500 picoSeconds, or less, is propagated down a generating a very fast Stream of pulses on the transmission
transmission line that Serves as a probe in a vessel. The line and receiving reflected pulses returned on the transmis
pulses are reflected by a discontinuity caused by a change in Sion line. The reflected pulses represent a characteristic of a
impedance, Such as at a transition between two media. For material being measured. An equivalent time Sampling cir
level measurement, that transition is typically where the air cuit is connected to the pulse circuit operable to Sample
and the material to be measured meet. Alternatively, the reflected pulses to build a time multiplied picture of the
transition could be two different liquids. The amplitude of reflected pulses and comprises a ramp generator circuit
the reflected Signal depends on the difference between the generating a saw tooth ramp signal used to Selectively delay
dielectrics of the two media. The dielectric of air is one, 35 Sampling reflected pulses to build the time multiplied pic
while the dielectric of water is about eighty. The larger the ture. The saw tooth ramp signal has a controlled ramp Start
difference in dielectric, the larger the reflected Signal. for each cycle and retrace at an end of the cycle. A proceSS
Guided wave radar is one technique available to measure ing circuit is connected to the equivalent time Sampling
the level of liquids or Solids in an industrial environment circuit for Selectively controlling ramp Start for each cycle
using TDR principles. Guided wave radar works by gener 40 and measuring round trip travel time for a pulse from the
ating a Stream of pulses of electromagnetic energy and pulse circuit.
propagating the pulses down a transmission line formed into It is a feature of the invention that the ramp generator
a level Sensing probe. The probe is generally placed verti circuit comprises a latching ramp comparator. The latching
cally in a tank or other container and the electromagnetic ramp comparator latches at the end of the cycle and is reset
pulse is launched downward from the top of the probe. The 45 by the processing circuit to Start the ramp for each cycle. The
probe is open to both the air and the material to be sensed latching ramp comparator has an output coupled to a non
in Such a way that the electromagnetic fields of the propa inverted input. The processing circuit resets the latching
gating pulse penetrate the air until they reach the level of the comparator by applying a low Voltage to the non-inverted
material. At that point, the electromagnetic fields See the input.
higher dielectric of the material. This higher dielectric 50 It is another feature of the invention that the ramp
causes a reduction in the impedance of the transmission line, generator circuit comprises a resistor network operatively
resulting in a pulse echo being reflected back to the top of controlled by the processing circuit for controlling slope of
the probe. The pulse travels through the air dielectric portion the saw tooth ramp signal.
of the probe at a known velocity. This allows the material There is disclosed in accordance with a further aspect of
level on the probe to be determined by measuring the round 55 the invention a domain reflectometry measurement instru
trip travel time of the pulse from the top of the probe to the ment comprising a probe and a pulse circuit connected to the
level and back to the top of the probe. Conductive materials probe for generating a very fast Stream of pulses on the
generate echoes similar to the echoes from high dielectric probe and receiving reflective pulses returned on their probe.
materials. Therefore, the same measurement technique also The reflected pulses represent a characteristic of a material
Works with conductive materials. 60 being measured. An equivalent time Sampling circuit is
Guided wave radar level measuring instruments may use connected to the pulse circuit operable to Sample reflected
time domain reflectometry for determining level. These pulses to build a time multiplied picture of the reflected
instruments use both electrical and electronic circuits to pulses, comprising a ramp generator circuit generating a saw
determine level. Some Such instruments use complex cir tooth ramp signal used to Selectively delay Sampling
cuits for implementing the TDR techniques. The complexity 65 reflected pulses to build the time multiplied picture. The
of the circuits may require additional components increasing ramp generator circuit comprises a ramp comparator that
the costs of the resulting devices. latches at a start Voltage during each cycle until receiving a
 US 6,801,157 B2
3 4
Start ramp signal and retraces to the Start Voltage at an end to measure distanced or levels. When a pulse reaches a
of the cycle. A processing circuit is connected to the equiva dielectric discontinuity then a part of the energy is reflected.
lent time Sampling circuit for Selectively generating the Start The greater the dielectric difference, the greater the ampli
ramp Signal for each cycle and measuring round trip travel tude of the reflection. In the measurement instrument 20, the
time for a pulse from the pulse circuit. probe 24 comprises a wave guide with a characteristic
Further features and advantages of the invention will be impedance in air. When part of the probe 24 is immersed in
readily apparent from the Specification and from the draw a material other than air, there is lower impedance due to the
ings. increase in the dielectric. Then the EM pulse is sent down
the probe it meets the dielectric discontinuity, a reflection is
BRIEF DESCRIPTION OF THE DRAWINGS generated.
FIG. 1 is a side elevation view of a measurement instru ETS is used to measure the high speed, low power EM
ment in accordance with the invention; energy. The high speed EM energy (1000 foot/microsecond)
is difficult to measure over Short distances and at the
FIG. 2 is a block diagram of a control circuit for the resolution required in the proceSS industry. ETS captures the
instrument of FIG. 1; 15
EM Signals in real time (nanoseconds) and reconstructs them
FIG. 3 is a block diagram of the probe interface circuit for in equivalent time (milliseconds), which is much easier to
the control circuit of FIG. 2; measure. ETS is accomplished by Scanning the wave guide
FIG. 4 is a block diagram of the Signal processing circuit to collect thousands of Samples. Approximately eight Scans
for the control circuit of FIG. 2; are taken per Second.
FIGS. 5 and 6 are a schematic diagram of the probe Referring to FIG. 2, the electronics mounted in the
interface circuit of FIG. 3; housing 22 of FIG. 1 are illustrated in block diagram form
FIG. 7 is a Schematic diagram of the Signal processing as a controller in the form of a control circuit 30 connected
circuit of FIG. 4; to the probe 24. The control circuit 30 includes a digital
FIG. 8 is a timing diagram illustrating operation of the 25
circuit board 32 and an analog circuit board 34. The digital
control circuit in accordance with the invention used with a circuit board 32 includes a microprocessor 36 connected to
coaxial or twin rod probe; and a Suitable memory 38 (the combination forming a computer)
and a display/push button interface 40. The display/push
FIG. 9 is a timing diagram illustrating operation of the button interface 40 is used for entering parameters with a
control circuit in accordance with the invention used with a keypad and displaying user information. The memory 38
Single rod probe. comprises both non-volatile memory for Storing programs
DETAILED DESCRIPTION OF THE and calibration parameters, as well as volatile memory used
INVENTION during level measurement. The microprocessor 36 is also
connected to a digital to analog input/output circuit 42 which
Referring to FIG. 1, a process instrument 20 according to is in turn connected to a two-wire 4-20 mA circuit 44 for
35
the invention is illustrated. The process instrument 20 uses connecting to remote devices. Particularly, the two-wire
pulsed radar in conjunction with equivalent time Sampling circuit 44 utilizes loop control and power circuitry which is
(ETS) and ultra-wide band (UWB) transceivers for measur well known and commonly used in process instrumentation.
ing level using time domain reflectometry (TDR). The power is provided on the line from an external power
Particularly, the instrument 20 uses guided wave radar for 40
supply. The circuit 44 controls the current on the two-wire
sensing level. While the embodiment described herein line which represents level or other characteristics measured
relates to a guided wave radar level Sensing apparatus, by the probe 24.
various aspects of the invention may be used with other The control circuit 30 has the capability of implementing
types of process instruments for measuring various proceSS digital communications through the two-wire circuit 44 with
parameterS. 45
remote devices and the outside World. Such communication
The process instrument 20 includes a control housing 22, preferably uses the HART protocol, but could also use
a probe 24, and a connector 26 for connecting the probe 24 fieldbus protocols such as Foundation Fieldbus or Profibus
to the housing 22. The probe 24 is typically mounted to a PA
proceSS vessel V using a threaded fitting 28. Alternatively, a The microprocessor 36 is also connected to a signal
flange may be used. The housing 22 is then Secured to the 50 processing circuit 46 on the analog board 34. The Signal
probe 24 as by threading the connector 26 to the probe 24 processing circuit 46 is in turn connected via a probe
and also to the housing 22. The probe 24 comprises a high interface circuit 48 to the probe 24. The probe interface
frequency transmission line which, when placed in a fluid, circuit 48 includes an ETS circuit which converts real time
can be used to measure level of the fluid. Particularly, the Signals to equivalent time signals, as discussed above. The
probe 24 is controlled by a controller, described below, in the 55 Signal processing circuit 44 processes the ETS Signals and
housing 22 for determining level in the vessel V. The probe provides a time output to the microprocessor 36, as
24 may comprise any one of a single rod probe, a coaxial described more particularly below.
probe or a twin rod probe, as is well known. The general concept implemented by the ETS circuit is
The vessel V contains a material M and has vapor or air known. The probe interface circuit 48 generates hundreds of
A above a liquid Surface L. AS described more particularly 60 thousands of very fast pulses of 500 picoseconds or less rise
below, the controller in the housing 22 generates and trans time every Second. The timing between pulses is tightly
mits pulses TP on the probe. A reflected signal RP is controlled. The reflected pulses are Sampled at controlled
developed off any impedance changes, Such as the liquid intervals. The samples build a time multiplied “picture” of
Surface L of the material M being measured. A Small amount the reflected pulses. Since these pulses travel on the probe 24
of energy, E, may continue down the probe 24. 65 at the Speed of light, this picture represents approximately
Guided wave radar combines TDR, ETS and low power ten nanoSeconds in real time for a five-foot probe. The probe
circuitry. TDR uses pulses of electromagnetic (EM) energy interface circuit 48 converts the time to about seventy-one
 US 6,801,157 B2
S 6
milliseconds. AS is apparent, the exact time would depend probe Signal and the fiducial for a single rod probe. Its output
on various factors, Such as, for example, probe length. The is also Supplied to the timing logic level data output circuit
largest Signals have an amplitude on the order of twenty 74. The variable gainstage 70 is also connected to a negative
millivolts before amplification to the desired amplitude by peak detector circuit 80 which is connected to the negative
common audio amplifiers. For a low power device, a thresh signal comparator 78. The negative peak detector circuit 80
old Scheme is employed to give interrupts to the micropro is a proportional threshold comparator circuit that develops
ceSSor 36 for Select Signals, namely, fiducial, target, level, a threshold as a proportion of the peak Signal level. This
and end of probe, as described below. The microprocessor threshold is provided to the negative Signal comparator 78
36 converts these timed interrupts into distance. With the which determines presence of the proceSS level pulse. The
probe length entered through the display/push button inter negative Signal comparator 78 is provided via an enable
face 40, or Some other interface, the microprocessor 36 can level detect circuit 82 to the timing logic level data output
calculate the level by Subtracting from the probe length the 74. The enable level detect circuit 82 adjusts a deadzone
difference between the fiducial and level distances.
time based on user input and a microprocessor timing
In accordance with the invention, the known ETS cir output.
cuitry is modified to provide enhanced operation, as 15 With reference to FIG. 5, an electrical Schematic illus
described below.
Referring to FIG. 3, a block diagram illustrates the probe trates a portion of the probe interface circuit of FIG. 3. The
interface circuit 48 in greater detail. A pulse repetition clock overall operation of the electrical schematic of FIG. 5, and
input 50 is connected to a transmit pulse shaper 52 which is likewise FIGS. 6 and 7, will be apparent to those skilled in
in turn connected via a Safety blocking capacitor circuit 54 the art. Only those components necessary for an understand
ing of the improvements are described in detail.
to the probe 24. The clock input 50 is also connected to a The clock input 50 is supplied to the transmit pulse shaper
pulse input of a Voltage controlled pulse delay generator 56.
The output of the delay generator 56 is connected to a 52 comprising a NAND gate U7A having its output con
receive pulse shaper 58 that is connected to an equivalent nected to another NAND gate U7B. An output of the second
time sampler 60. The sampler 60 is connected via the safety 25
NAND gate U7B drives a transistor Q1. The transistor Q1 is
blocking capacitor circuit 54 to the probe 24. An output of connected to the safety barrier circuit 54. When the mea
the Sampler 60 is connected to the Signal processing circuit Surement instrument 20 is applied as an explosion proof unit,
46. A saw tooth ramp generator circuit 62 develops a saw it must have a Suitable housing, rated as explosion proof, but
tooth ramp as an input to the Voltage controlled pulse delay also must limit energy that enters the process via the probe
generator 56. 24 to intrinsically Safe levels. Three high Voltage capacitors,
The clock input 50 generates a pulse train at the frequency C4, C5 and C6 are connected in series between a probe
of the transmitted pulses. For each input pulse, the pulse connection J2 and via a capacitor C3 to the transistor Q1.
delay generator 56 generates an output pulse with a delay The Safety barrier assures that no unsafe Voltage or current
that is controlled by its control Voltage input received from enters the probe. Each part must be capable of withstanding
the saw tooth ramp generator circuit 62. The delayed pulse 35
a fault voltage. The value of the capacitors C4-C6 must be
chosen to assure that the circuit will not allow fault currents
passes through the receive pulse shaper 58 and is provided beyond a safe level, at any possible fault frequency. The
to the sampler 60. The sampler 60 samples the reflected capacitors C4-C6 may be on the order of 1000 pF.
pulses from the probe 24 at a time determined by the delayed
and shaped output pulse. The resulting low frequency In the illustrated embodiment of the invention, the mea
Sampled Signal is amplified and passed on to the Signal 40 Surement instrument 20 comprises a guided wave radar
processing circuit 46. instrument. AS will be apparent to those skilled in the art, the
Referring to FIG. 4, the Signal processing circuit 46 of safety barrier circuit 54 may be used in connection with a
FIG. 2 is illustrated in greater detail. The signal from the measurement instrument in which the probe 24 comprises a
Sampler 60 is provided to again Stage 64 which amplifies the capacitance probe and, as Such, the probe 24 of FIG. 1 is
low frequency Sampled Signal. The amplified Signal is 45 likewise illustrative of a capacitance probe.
provided to a baseline sample circuit 66 that allows the With reference also to FIG. 6, the saw tooth ramp gen
microprocessor 36 to push the AC coupled signal back to a erator circuit 62 is provided with controlled start and retrace
reference Voltage. This signal can be adjusted by the micro after an end of the ramp. An end of ramp comparator resets
processor 36 to control the fiducial time and optimize the ramp output to a starting Voltage and latches itself. The
performance. The output from the baseline Sample circuit 66 50 microprocessor 36 must Start the ramp by Sending a control
is provided to a fixed fiducial gain Stage 68 and a variable Signal that clears the latch. AS Such, the microprocessor 36
gain stage 70. The fixed fiducial gain state 68 provides a controls the ramp which freeruns to its end. The ramp stays
fixed gain and feeds a negative fiducial comparator circuit at a start Voltage until Started by the microprocessor 36 So
72 which looks for a negative bump on the return signal, control is Smoother at the Start of a cycle. Range Selection is
indicating the fiducial or reference marker. The indication of 55 also provided, as described below.
the fiducial is provided to a timing logic level data output An operational amplifier USB operates as a ramp genera
circuit 74. As described above, differing signal levels result tor. Capacitors C24 and C25 are connected between an
from differing dielectric constants of the reflecting medium output of the Op-Amp U5B and its inverted input. The
and from the probe characteristics. For example, the fiducial non-inverted input is connected to receive a Select Voltage
generally produces a Smaller signal than does the reflecting 60 reference VMIN. A resistor R29 is connected between the
material. As a result, the fixed fiducial gain Stage 68 gener inverted input and ground. A Second resistor R29A is con
ally uses a higher gain than does the variable gain Stage. The nected between the inverted input and a transistor Q10. The
variable gain Stage 70 allows for variable gain Selection capacitors C24 and C25 are charged by the current estab
according to the particular material being Sensed. The output lished by VMIN and the resistance of the resistor R29. The
of the variable gain Stage 70 is provided to a positive signal 65 output of the Op-Amp U5B is connected via a resistor R28
comparator 76 and a negative signal comparator 78. The to the non-inverted input of a comparator U4B. The inverted
positive signal comparator is used for Sensing an end of input of the comparator U4B is connected to a signal VMAX
 US 6,801,157 B2
7 8
representing the upper Voltage of the ramp. When the ramp The signal input is provided from the amplifier U5A to the
voltage output of the Op-Amp U5B reaches the voltage non-inverted input of an Op-Amp U6A. The inverted input
VMAX the comparator U4B trips high turning on a tran is connected via a resistor R54 to the reference Voltage.
sistor Q3 connected across the Op-Amp U5B and resets the When the signal from the Op-Amp U6A pulls below the
RAMP voltage to VMIN. reference by Sufficient amount the output of the latching
The output of the comparator U4B is coupled by a diode comparator U2A goes high. A diode D8 couples the high
D3 and resistor R26 to the non-inverted input of the com output back to the non-inverted input of the latching com
parator U4B. This holds the comparator output high until parator U2A. This latches the comparator high until the next
reset by a low Voltage at a diode D2 connected to the cycle. The microprocessor 36 controls the next cycle by
non-inverted input of the comparator U4B. The opposite control of the reset Signal, described above, which resets the
side of the diode is connected to an N RESET RAMP. The voltage on the capacitor C49.
N RESET RAMP signal is provided from the micropro The output from the comparator U2A is also connected
cessor 36. This allows the microprocessor 36 to start the via the diode D8 to one input of a NAND gate U1D which
ramp. The diode D3 is also connected to an END OF provides the timing logic level data output LEVEL.
RAMP input to the microprocessor 36. This circuit gives 15 The Signal processing circuit 46 uses fixed or proportional
control of the ramp Starting and allows the microprocessor threshold detection. The proportional threshold detection
36 to monitor the length of the ramp. adjusts the threshold of the Sensor to a constant proportion
The transistor Q10 is controlled by a Range2 input from of the peak amplitude of the pulse echoed from the material
the microprocessor 36 to change the slope of the ramp by Surface.
Selectively placing an additional resistor R29A in parallel A comparator U2B operates as a proportional threshold
with the resistor R29. A faster slope allows the ramp to scan comparator. Its inverted input is connected via a Series
the same length of probe in less time. This in combination resistor R78 and capacitor C53 to ground. The junction
with the selection of the voltage VMAX allows the selection between the resistor R78 and the capacitor C53 is connected
of probe lengths to be Scanned in a fixed period of time. The 25
via a diode D10 to a FIXED THRESHOLD input from the
instrument 20 has a fixed repetition rate of the number of microprocessor 36.
measurements per Second. The Signal input to the gain Stage 64 is connected through
Referring again to FIG. 5, the clock input 50 is also an Op-Amp U6B to an Op-Amp U5B. The output of the
provided to a NAND gate U8D having its output connected Op-Amp U5B is connected via the diode D10 to the com
to another NAND gate U8C which drives a transistor Q2. parator U2B. When the fixed threshold control line is low the
The ramp signal is connected via resistors R20 and R15 to output of the Op-Amp U5B, which is a percentage of the
the output of the NAND gate U8C. The NAND gates U8D negative peak detected signal, is held by the capacitor C53.
and U8C operate as a time delay gate. The ramp signal This allows the comparator U2B to act as proportional
Works against the pulse width timing of the output gate. threshold of the return signal. When the fixed threshold
Particularly, as the ramp Voltage increases additional delay 35 control line is high, the diode D10 cathode is held high so
is provided. The delayed pulse drives the transistor Q2 that resistors R71 and R77 connected between the voltage
which turns on a diode D1. The voltage from returned pulses and ground establish the voltage on the capacitor C53. The
from the probe connection J2 are provided via the safety comparator U2B acts as the fixed threshold detector. The
barrier circuit 54 to a capacitor C14 connected between the output of the comparator U2B is connected via an analog
transistor O2 and the diode D1. A resistor R18 is connected 40 Switch U3C controlled by an enable level signal from the
between the junction of the capacitor C4 and the diode D1 microprocessor 36, to the NAND gate U1D.
and provides a Signal labeled +SIG to the Signal processing The microprocessor 36 controls the time when the level
circuit of FIG. 4. Signal can be permitted to effect the proportional threshold.
Referring to FIG. 7, an electrical schematic illustrates the Holding the fixed threshold control line high does not allow
signal processing circuit 46 of FIG. 4. The signal line +SIG 45 the return signal on the Op-Amp U5C to couple into the
is connected to the gain Stage 64 comprising an Op-Amp capacitor C53. AS a result, the microprocessor 36 can reject
U5A. A baseline sample input from the microprocessor 36 Signals that occur after the end of the probe is detected. After
controls an analog Switch U3A connected between a refer the end of the probe is detected, only signal anomalies occur.
ence voltage and an output of the Op-Amp U5A. This These can be larger than the true level Signal causing
provides a DC reference by forcing the signal to the 2.5 volt 50 problems where the comparator U2B cannot detect the
reference in the illustrated embodiment. actual level.
In a guided wave radar unit a fiducial Signal, which is a Known guided wave radar transmitters can use Single rod
Small signal reflected in the top of a probe, establishes the probes, coaxial probes, and twin rod probes. Such known
reference time for the level Signals that are received from the devices typically require different circuitry depending on the
proceSS material. The fiducial is typically very Small com 55 type of probe. This is because coaxial or twin rod probes
pared to the level Signal and must be detected accurately to have a negative fiducial and Single rod probes have a
assure proper level measurements. In accordance with the positive fiducial because of the increased impedance at the
invention, a latching comparator U2A detects the fiducial top of the probe. In accordance with the invention, the
Signal. The baseline Sample control signal from the micro measurement instrument 20 uses one logic circuit for any
processor 36 is also provided to a NAND gate U1A which 60 probe type.
is in turn connected to a NAND gate U1B and then through Two control lines are used by the microprocessor 36 to
a diode D7 to the non-inverted input of the latching com select the probe type. The line N708 controls the signals to
parator U2A. A capacitor C49 is connected between the the negative fiducial comparator U2A by being connected to
non-inverted input and ground. The microprocessor 36 uses its inverted input. When the signal N708 is tri-stated (high
this circuit to reset the voltage on the capacitor C49 to the 65 impedance), the signals from the amplifier U6A are allowed
reference Voltage. This causes the output of the latching to pass to the negative fiducial comparator U2A. This is the
comparator U2A to go low arming it for the next fiducial. condition used for coaxial and twin rod probe types. A
 US 6,801,157 B2
9 10
comparator U4A comprises a positive signal comparator. A which any reflected Signals are ignored. This is a user
line N EOP Enable control signal from the microproces adjustable time. During the deadzone time, the tickS counter
Sor 36 is connected to the non-inverted input of the com continues until the reflected level pulse is received at a time
parator U4A. The signal line is received from the Op-Amp T5. The END OF PROBE signal is received at a time T6.
U6B to the inverted input of the comparator U4A. When the The ramp reaches the voltage VMAX at a time T7 and
signal on the line N EOP Enable is low the comparator retraces to the VMIN value where it remains until the
U4A detects positive Signals, as can occur from the top of the completion of the cycle at a time T8 when the next RESET
signal rod probe or from the end of the probe. The output of RAMP signal is sent from the microprocessor 36. In the
the comparator U4A is connected via a diode D4 to the illustrative example, the fixed threshold output is set low
NAND gate U1D of the timing logic level data output circuit between the times T1 and T6 to operate in the proportional
threshold mode.
74.
AS is apparent from FIG. 8, the analog Signal, shown for
With coaxial or twin rod probe selection, the control N708 twin rod operation, comprises the time multiplied fixture of
is tri-stated at all times. The line N EOP Enable is pulled the reflected pulses. The level data Signal shows the pulses
low after Some blanking time to account for the positive developed by the Signal processing circuit 46 Supplied to the
Signal from the twin rod top of probe impedance transition. 15
microprocessor 36 for determining level. Particularly, the
The comparator U4A is enabled to detect the end of probe microprocessor 36 computes level by determining the ratio
Signal. of the values ticks to ramp ticks resulting in a relative
In the single rod mode, the control line N708 is always distance. This is then used for computing level.
held low to disable the comparator U2A. The control line The timing diagram of FIG. 9 differs with respect to the
N EOP Enable is pulled low before the top of the probe so use of the first end of probe input to the microprocessor as
that the positive fiducial Signal can be detected. the fiducial which is enabled after the baseline sample
Probe Selection also involves Significant complexity in the control Signal.
microprocessor 36. The fiducial timing for negative fiducial Thus, in accordance with the invention, there is provided
probes is from the falling edge of the first pulse in the 25 a guided wave radar measurement instrument of reduced
LEVEL data line from the NAND gate U1D. On a single rod complexity and cost while providing accurate and precise
probe, the leading edge of the first pulse in the level data line level measurement.
is used for the fiducial time. The present invention has been described with respect to
Gain selection for the measurement instrument 20 is timing diagrams and block diagrams. It will be understood
provided via two analog switches U3B and U3D controlled that output Signals of the timing diagrams and various blockS
by respective Gain 1 and Gain 0 control lines from the of the block diagrams can be implemented by computer
microprocessor 36. The Op-Amp U6B allows for gain program instructions. These program instructions may be
control. Resistors R65 and R69 connected to the inverted provided to a processor to produce a machine, Such that the
input of the Op-Amp U6B establish the minimum gain when instructions which execute on the processor create means for
the analog Switch is U3B and U3D are open. Switching on 35 implementing the functions Specified in the blocks. The
the Switches U3B and U3D individually or together allows computer program instructions may be executed by a pro
three additional steps of gain. Particularly, a resistor R68 is ceSSor to cause a Series of operational Steps to be performed
connected by the first Switch U3B between the inverted by the processor to produce a computer implemented pro
input of the Op-Amp U6B and the reference voltage. A ceSS Such that the instructions which execute on the proces
resistor R74 is connected by the analog switch U3D between 40 Sorprovide Steps for implementing the functions Specified in
the reference Voltage and the inverted input. Thus, the the blockS. Accordingly, the illustrations Support combina
resistors R74 and R68 determine the actual gain steps as tions of means for performing a specified function and
parallel resistance with the resistor R69. As is apparent, N combinations of Steps for performing the Specified func
switches and resistor could be used to allow for 2 gain tions. It will also be understood that each block and com
StepS. 45 bination of blockS can be implemented by Special purpose
FIGS. 8 and 9 illustrate timing diagrams for operation of hardware-based Systems which perform the Specified func
the level measurement instrument 20 in accordance with the tions or Steps, or combinations of Special purpose hardware
invention. Particularly, FIG. 8 illustrates operation with a and computer instructions.
coax or twin rod probe, while FIG. 9 illustrates operation I claim:
with a single rod probe. The signals are labeled in bold 50 1. A proceSS instrument comprising:
lettering for microprocessor outputs and in italics for micro a housing:
processor inputs. a level Sensing probe comprising a transmission line for
Referring initially to FIG. 8, the cycle begins when the Sensing a characteristic of a proceSS represented by an
reset ramp control Signal from the microprocessor 36 goes impedance change on the transmission line;
high at time T1. This corresponds to an inverted 55 a control circuit disposed in the housing and electrically
N RESET RAMP control signal going low causing the connected to the probe for measuring the Sensed char
cycle to begin and the ramp signal to Start for a particular acteristic comprising a pulse circuit connected to the
cycle. The baseline Sample control line enables Sensing by probe for generating a very fast Stream of pulses on the
resetting comparators pushing them back to the 2.5 volt transmission line at a Select operating frequency and
reference, as discussed above. Once Sensing is enabled, then 60 receiving reflected pulses returned on the transmission
a fid ticks counter is enabled at a time T2 to count the line, the reflected pulses representing impedance
amount of time to receipt of the reflected fiducial pulse, as changes; and
illustrated. The level data input is high prior to Sensing the a Safety barrier comprising a blocking capacitor barrier
fiducial pulse. A ramp ticks counter begins counting at the electrically connected between the control circuit and
initiation of the ramp. A ticks counter begins counting at the 65 the probe So that the Safety barrier comprises a portion
completion of the fiducial. The enable level detect control of the transmission line providing impedance matching
Signal utilizes a deadZone time after the fiducial during at the Select operating frequency.
 US 6,801,157 B2
11 12
2. The process instrument of claim 1 wherein the probe acteristic comprising a pulse circuit connected to the
comprises a guided wave radar transmission line. probe for generating a very fast Stream of pulses on the
3. The process instrument of claim 1 wherein the blocking transmission line at a Select operating frequency and
capacitor barrier comprises a plurality of Series connected receiving reflected pulses returned on the transmission
capacitors. 5 line, the reflected pulses representing impedance
4. The process instrument of claim 3 wherein capacitors changes; and
comprise 1000 pF capacitors. a Safety barrier comprising a plurality of Series connected
5. The process instrument of claim 1 wherein the blocking capacitors electrically connected between the control
capacitor barrier comprises a plurality of Series connected
high Voltage capacitors. 1O circuit and the probe So that the Safety barrier com -0
6. A proceSS instrument comprising: prises a portion of the transmission line providing
impedance matching at the Select operating frequency.
a housing; 7. The process instrument of claim 6 wherein the probe
a probe comprising a transmission line for Sensing a comprises a guided wave radar transmission line.
characteristic of a process represented by an impedance 8. The process instrument of claim 6 wherein the capaci
change on the transmission line; ' tors comprise 1000 pF capacitors.
a control circuit disposed in the housing and electrically
connected to the probe for measuring the Sensed char- k . . . .