Design and Simulation of 22nm FinFET
Structure Using TCAD
R. Kalaivani J. Charles Pravin
Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering
Kalasalingam Academy of Research and Education Kalasalingam Academy of Research and Education
Krishnankoil,India Krishnankoil,India
kalaimeenu26@gmail.com charles@klu.ac.in
S.Ashok Kumar R. Sridevi
Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering
Kalasalingam Academy of Research and Education Kalasalingam Academy of Research and Education
Krishnankoil,India Krishnankoil,India
6691ashok@gmail.com rkpriyaviji@gmail.com
Abstract- The FINFET concept is reviewed for the gate material used both polysilicon and metal .In
enhancement of power and performance in the VLSI the place of conventional polycrystalline silicon,
Optimizing circuit .FINFET is the basics for the scaling of metal oxide semiconductor(MOS)
upcoming technologies because of its power
needs the implementation of the metal gate because
utilization, performance, scalability and better
control in the short channel effects. In this paper the the poly gate device shows a high gate resistance,
working of FINFET is analyzed using Hfo2 dielectric dopant penetration to channel region and an
material by using TCAD tool. Drain current in the increasing equivalent oxide thickness[9]. Normally
circuits are optimized by using high K dielectric using of metal gate is attractive compared due to
material Hf02. The result shows that the improvement their chemical stability with high k gate dielectric
in the device performance by using various gate work material. The various work function such as
function (4.2ev to 4.6ev). Better device Structure will aluminium (4.28ev), titanium (4.33ev),chromium
surely be the solution for high optimizing devices (4.5ev),molybdenum (4.6ev) is used in this paper.
Keywords- FINFET, Dielectric material,TCAD
The increasing gate work function is also improves
the FINFET structure. A paper is organized as in
I. INTRODUCTION section II, the methodology is discussed. The
overall result are discussed in section III, Finally
Normally, MOSFET have the problems of high the paper is terminated in Section IV
amount leakage current from gate to channel
terminals and mainly the transistor characteristics II. METHODOLOGY
are not easily predicted. To overcome these
problems FINFET technology is considered, which The FINFET structure were generated using
it has a major impact on the semiconductor technology computer aided design (TCAD) tool
industry [1]. In the FINFET device, the gate is [10] [11]. The TCAD tool is used to model the
covered around a thin and silicon without doping is semiconductor device and also device operation
called fin, the drawback of channel length [12] [13]. Analyses of the FINFET done with key
reduction, cut off frequencies, short channel effect geometrics are listed in Table 1. The gate length is
will be overcome for the better technology. Mostly chosen to be 22nm and the overall analysis is done
the structure is trying hard to overcome the with same length. The 3D structure is generated by
drawbacks. It normally fabricated in two different writing the code using TCAD tool. After writing
types of dual gate FINFET and Trigate FINFET for the process code, the 3D FINFET structure with
attaining the different benefit of FINFET. To high k dielectric material Hfo2 is generated.
scaling the MOSFET to deca - nanometer range
[2], the double gate FINFET is used.
Double gate MOSFET is also used to reduce the
drain induced barrier lowering and improves
threshold [3]. High K dielectric material in the
device has the advantage of increasing I on/I off ratio
and lowering the power consumption[4]-[8].The
2
𝑛𝑝−𝑛𝑖,𝑒𝑓𝑓
𝑆𝑅𝐻
𝑅𝑛𝑒𝑡 = 𝜏𝑝 (𝑛+𝑛1 )+𝜏𝑛 (𝑝+𝑝1 )
(4)
with
𝐸𝑡𝑟𝑎𝑝
𝑛1 = 𝑛𝑖,𝑒𝑓𝑓 exp ( 𝐾𝑇
)
(5)
and
−𝐸𝑡𝑟𝑎𝑝
𝑝1 = 𝑛𝑖,𝑒𝑓𝑓 exp ( 𝐾𝑇
) (6)
Figure 1. Device Structure of 3D FINFET[14] Etrap is the diference between the defect level and
intrinstic level and its variable is accessible in the
TABLE I. Device parameter for FINFET using Hfo 2[15]
parameter file. The default value of silicon value is
PARAMETER DIMENSION Etrap =0
Gate length , Lg 22nm
Effective oxide thickness , T ox 6.7nm III. RESULT AND DISCUSSION
Height of the gate , HGate 40nm
Channel doping concentration, 1e+15/cm3 This section deals with the device structure and
NCh simulation result obtained. The overall simulation
Doping concentration,N Sd 1e+15/cm3 is done at room temperature. Simulation has been
done and the characteristics curve of FINFET has
been plotted .The supply voltage has chosen to be
A. Drift-Diffusion model 1V
In sentaurus device, the drift diffusion model is the
common carrier transport model. The current
density for electrons is given by [16]
(1)
The cur11rent density for holes is given by
(2)
The first term is considering for the contriibutions
due to the spatial variation of the electrostatic .
potential , the electron affinity , and the band gap .
The other term considering the contribution due to
the gradient of concentration and the spatial
Figure 2. 3D TCAD model of finfet using Hfo2 as dielectric
variation of the effective masses mn and mp. From
the Einstein relation , the diffusivities are derived Figure 2 illustrates the 3D TCAD model for finfet
with the use of mobilities using silicon for substrate, polysilicon for gate
material and Hfo2 as dielectric. For the optimization
𝐷𝑛 = 𝑘𝑇𝜇𝑛 𝑎𝑛𝑑𝐷𝑝 = 𝑘𝑇𝜇𝑝 (3) of device performance various work function is
used in the gate material. Where figure 3 illustrates
B. Schokley-Read-Hall recombination the Vg vs Id curve for Hfo2 as dielectric with work
function of 4.15ev. Where figure 4 illustrates the
Recombination throughdeep defect levels in the different drain current value, Vg vs Id, Vg
characteristics of FINFET contains the different
gap is normally refer to schokley-Read-Hall(SRH)
value of gate material.
recombination[10]. In sentaurus device, the
following term is implemented:
limitation of Sio2, high dielectric constant material
Hfo2 has been incorporated into the structure . The
simulation shows that FINFET using Hfo2 as
dielectric material gives better performance in
drain current where Hfo2 is the best dielectric
material for the future nanoscale device
technology. From the simulation study, it shows
that the variation of threshold voltage with respect
respect to metal gate work function will increase
the efficiency of used metal gates. The short
channel effect in FINFET will be improved by
proper adjustment of the metal gate work function.
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