REV. 4.

4 FS970X-DS-44_EN MAY 2014

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Datasheet

FS970X

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5,000/50,000 counts DMM analog front end.
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 FS970X

Fortune Semiconductor Corporation

富晶電子股份有限公司
23F., No.29-5, Sec. 2, Zhongzheng E. Rd.,
Danshui Town, Taipei County 251, Taiwan
Tel.：886-2-28094742
Fax：886-2-28094874
www.ic-fortune.com

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This manual contains new product information. Fortune Semiconductor Corporation reserves the rights to
modify the product specification without further notice. No liability is assumed by Fortune Semiconductor
Corporation as a result of the use of this product. No rights under any patent accompany the sale of the
product.

Rev. 4.4 2/46

 FS970X

Contents

1. GENERAL DESCRIPTION ......................................................................................................................... 5

2. FEATURES ................................................................................................................................................. 5

2.1 General Features (FS9701A/B as an example) ........................................................................... 5

2.2 Measurement Range (FS9701B as an example) ......................................................................... 6

3. ORDERING INFORMATION ....................................................................................................................... 6

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4.

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ELECTRICAL CHARACTERISTICS .......................................................................................................... 6

BLOCK-DIAGRAM ..................................................................................................................................... 8

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6. PACKAGING & PINS ................................................................................................................................. 8

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6.1 LQFP 64 Pin Definition.................................................................................................................. 8

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6.2 Pin Description .............................................................................................................................. 9

7. TYPICAL APPLICATION CIRCUIT .......................................................................................................... 10

8. REGULATOR............................................................................................................................................ 11
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8.1 Low Voltage Detector .................................................................................................................. 12

8.2 Saving Mode ................................................................................................................................ 12

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8.3 On/Off Power Output .................................................................................................................. 13

9. CLOCK AND BUZZER GENERATOR...................................................................................................... 14

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9.1 Clock Generator .......................................................................................................................... 14

9.2 Buzzer Generator ........................................................................................................................ 15

10. FUNCTION NETWORK ............................................................................................................................ 16

10.1 Function Decoder........................................................................................................................ 17

10.2 Fixed Voltage Generator ............................................................................................................. 18

10.3 Ω Power Supply .......................................................................................................................... 19

10.4 Multiplexers and pre-filter .......................................................................................................... 20

10.5 Operation Amplifier and Comparator ........................................................................................ 22

11. ANALOG TO DIGITAL CONVERTER (ADC) ........................................................................................... 24

11.1 The operating theory of - ADC ............................................................................................... 24

11.2 Transfer Function & Non-ideal affect ........................................................................................ 24

11.3 Function Gain Setup ................................................................................................................... 25

11.4 Digital Filter ................................................................................................................................. 26

11.5 Reading and operation of ADC .................................................................................................. 28

11.5.1 High-resolution, low-speed output ............................................................................................ 28

11.5.2 Low-resolution, high-speed output ........................................................................................... 28

11.5.3 Scale-type resistance measurement and Analog Bargraph .................................................... 29

Rev. 4.4 3/46

 FS970X

11.6 The Conversion of Digital Output & Equivalent Voltage .......................................................... 30

11.7 The different output code of different models .......................................................................... 31

11.8 Other Control setting .................................................................................................................. 31

12. DIGITAL SIGNAL PROCESS ................................................................................................................... 31

12.1 Frequency counter ...................................................................................................................... 31

12.2 The reading process of frequency counter .............................................................................. 32

12.3 Peak-hold sampling process...................................................................................................... 32

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13. MICROPROCESSOR INTERFACE .......................................................................................................... 33

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13.1 Control register ........................................................................................................................... 33

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13.2 The interrupt process ................................................................................................................. 35

13.3 Measurement Registers .............................................................................................................. 36

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14. BASIC MEASUREMENT APPLICATION ................................................................................................. 37

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14.1 DCmV ........................................................................................................................................... 37

14.2 DC voltage ................................................................................................................................... 38

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14.3 AC Voltage (ACV) ........................................................................................................................ 39

14.4

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14.5 AC Current (ACA) ........................................................................................................................ 41

14.6 Resistor ().................................................................................................................................. 42

14.7 Capacitor...................................................................................................................................... 43
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14.8 Diode ............................................................................................................................................ 44

15. PACKAGE OUTLINE................................................................................................................................ 45

16. ATTACHMENT (1) OP-AMP SPECIFICATIONS ...................................................................................... 46

17. REVISION HISTORY ................................................................................................................................ 46

Rev. 4.4 4/46

 FS970X

1. General Description
FS970X is a series of Digital Multi-function Meter (DMM) front-end chip. The core is a high resolution Σ-Δ ADC,
combined with function network, operation amplifier, comparator, digital filter, crystal oscillator circuit, digital
control logic and micro processor interface.

FS970X ADC includes not only high-resolution output to achieve accurate measurement, but high-speed ADC
output to display the bar graph of digital meter and to measure +/- peak hold.

Combined with a micro processor, FS970X can function as an auto-range DMM to measure DC/AC voltage,

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DC/AC current, resistance, frequency, peak hold and diode, etc. In addition, it includes several sets of

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programmable ADC direct input to expand product applicability (such as pressure function, temperature
function, etc….)

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There are two operation amplifiers built in FS970X to act as high impedance buffer and DC/AC converter when
measuring AC voltage. These two amplifiers are with other functions as well even not acting as DC/AC

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converter. One of them can be connected to external resistor to build a x10 amplify circuit. The reading from the

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x10 signal into the ADC can still be of accuracy due to the excellent noise immunity of the amplifier.
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Max. resolution (counts)/

Frequency counter
Speed output (HZ) /
resolution (counts)

AC/DC Converter

Voltage regulator
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Diode testing
DC Voltage

DC Current
output (Hz)

ADP input
Peak hold
AC Buffer

X 10 path

Capacitor
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Resistor
Chip

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FS9701B 5000 / 5 640 / 500            5

FS9704B 80000 / 5 640 / 800            5

Chart 1. FS970X A/B series chips

There are two different versions of FS970X with different specifications and functions. With the same micro
processor FSμP01 chip (programs), customers can easily and quickly develop different levels of DMM.

2. Features

General Features (FS9701A/B as an example)

1) Built-in high resolution Δ-Σ ADC
2) 5,000 counts, high-resolution low-speed input, 5 times / sec.
3) 500 counts, low resolution, high-speed input, 640 times / sec.
4) Built-in voltage regulator with 9V input, 3.2V output
5) Under DC voltage, power consumption is under 1.2mA
6) Standby saving mode
7) Low battery detection
8) Good CMRR at 50/60HZ
9) Built-in crystal oscillator circuit
10) 2.5 kHz beeper driver

Rev. 4.4 5/46

 FS970X

11) Standard 4-bit parallel interface to directly connect to micro processor port
12) 4 programmable ADC direct input channel
13) 64 PIN LQFP package

Measurement Range (FS9701B as an example)

1) 500.0 mV, 50.00mVDC voltage, high impedance input.
2) 0.5000V, 5.000 V, 50.00 V, 500.0 V and 1000 V DC voltage
3) 500.0 uA, 5.000 mA, 50.00mA, 500.0 mA, 5.000 A, and 10.00 A DC current
4) 500.0 , 5.000 K, 50.00 K, 500.0 K, 5.000 M and 50.00 M resistance
5) 0.5000V, 5.000 V, 50.00 V, 500.0 V and 1000 V AC voltage
6) 500.0 uA, 5.000 mA, 50.00mA, 500.0 mA, 5.000 A, and 10.00 A AC current

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7) 10.00 nF, 100.0 nF, 1.000 uF,10.00 uF, and 100.0 uF capacitor

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8)
9)
50.00 Hz, 500.0 Hz, 5.000 Khz, 50.00 Khz, 500.0 Khz, and 5.000 Mhz frequency.
Diode forward bias voltage test, with maximum forward voltage of 2V

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10) 1 mS above peak hold detector

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3. Ordering Information

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Product Number Package Type
FS9701B 64-pin LQFP
FS9704B 64-pin LQFP
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FS9701B-GCE Green 64-pin LQFP

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FS9704B-GCE Green 64-pin LQFP
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4. Electrical Characteristics
(VBAT = 9V, VSS = 0V, TA=+25℃, unless otherwise indicated)
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PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNITS

Zero Input Reading VIN=0V, 500mV Scale -1 0 1 Counts
Zero Reading Drift VIN=0V, 0℃<TA<+70℃ μV/℃
Linearity (Max. deviation from best 500mV Scale -2 0 2 Counts
straight line fit)
Input Common-Mode Rejection Ratio VCM=±1V, VIN=0V, 500mV Scale 120 μV/V
Input Common-Mode Voltage Range VIN=0V, 500mV Scale, ±12 Counts -1 1 V
Noise (p-p Value not Exceeding 95% VIN=0V, 500mV Scale 0 1 Counts
of Time)
Rollover Error (Difference in reading -VIN=+VIN=500.00mV 0 1 5 Counts
for equal positive and negative inputs
near Full Scale)
Input Leakage Current VIN=0V 1 10 pA
Scale Factor Temperature Coefficient VIN=500.00mV, 0℃<TA<+70℃ 7.5 ppm/℃
Analog Ground Voltage (With respect 3.2 V
to VSS)
Analog Supply Voltage (With respect 6.2 V
to VSS)
Digital Supply Voltage (With respect 5 V
to VSS)
Analog Ground Source Capability ΔVO=-0.1V 20 μA
Analog Ground Sink Capability ΔVO=0.1V 3 mA
Analog Supply Source Capability ΔVO=0.1V 60 mA
VBAT 7 9 V

Rev. 4.4 6/46

 FS970X

PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNITS

Low Battery Detection Voltage 6.7 6.8 6.9 V
VBAT Operating Current VIN=0, 500mV Scale 960 μA
RIN=1KΩ, 500Ω Scale 3000
Sleep Current 10 30 μA
ADC Current VIN=0 660 μA
ACOP Current VIN=0 170 μA
Comparator Current VIN=0.5V DC 14 μA
OSRC Source Capability ΔVO=-0.1V, 500Ω Scale 600 μA
Bandwidth of ACOP Hz

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DC Gain of ACOP dB

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Bandwidth of Comparator VIN=600mVP-P SIN
VIN=40mVrms SIN
15M
500K
Hz

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Hysteresis of Comparator ENSCHMT=1 0.2 V
ACBUF Linearity Error Gain=1
(RL=10MΩ, CL=30pF) VIN=0.4Vrms, 100KHz SIN 0.25 %

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VIN=0.4Vrms, 50KHz SIN 0.05

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VIN=0.4Vrms, 20KHz SIN 0.01
VIN=0.4Vrms, 10KHz SIN calibration -
VIN=0.4Vrms, 50Hz SIN 0.0025
(RL=10KΩ, CL=30pF) VIN=0.4Vrms, 100KHz SIN 0.23
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VIN=0.4Vrms, 50KHz SIN 0.045

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VIN=0.4Vrms, 10KHz SIN calibration
0.005
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VIN=0.4Vrms, 50Hz SIN 0.07

ACBUF Linearity Error Gain=10
(RL=10MΩ, CL=30pF) VIN=0.04Vrms, 20KHz SIN 4.3 %
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VIN=0.04Vrms, 10KHz SIN 1.14

VIN=0.04Vrms, 5KHz SIN 0.27
VIN=0.04Vrms, 1KHz SIN calibration -
VIN=0.04Vrms, 50Hz SIN 0
(RL=10KΩ, CL=30pF) VIN=0.04Vrms, 20KHz SIN 4.4
VIN=0.04Vrms, 10KHz SIN 1.14
VIN=0.04Vrms, 5KHz SIN 0.27
VIN=0.04Vrms, 1KHz SIN calibration -
VIN=0.04Vrms, 50Hz SIN 0.05
RCTOP Linearity Error VIN=0.2Vrms, 100Hz SIN calibration
VIN=0.2Vrms, 10KHz SIN 2.5 %
Switch Resistance:
SW1 240 Ω
SW2 700
SW3 2K
Parasitic Capacitance 12 pF
Digital Output High IOUT=-1mA 5 V
Digital Output Low IOUT=1mA 25 mV
Digital Input High V
Digital Input Low V
Note 1: If you wanna know OP-AMP Specifications, you can read attachment (1).

Rev. 4.4 7/46

 FS970X

5. Block-diagram

AC-to-DC
external High resolution  ADC
netw ork &
Function, Range input volatge buffers
Routers, Opamps,
Comparators
DMM &
Signal Ohm Source
Input
Conditioning Digital Signal Processing

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(Counters, Filters & Control Logic)
Netw ork

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Microprocessor
Interface PC or
& Microprocessor
Pow er Regulator (master)
Control Logic

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Regulation &

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netw ork & precise Low Battery Detector
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zenner diode Oscillator
VBAT
&
Colck generator
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9 V Battery

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VBAT
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6. Packaging & Pins

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LQFP 64 Pin Definition

16

15

14

13

12

11

10

1
CPN

RST_

VCC

CS_

ALE

WR_

RD_

AD0

AD1

AD2

AD3

IRQO

BZR

XTALO

XTALI

VSSD

17 FTC
VBAT 64

18 TENM
FCNTI 63

19 ONEM
CMP1 62

20 HUNK
CMP2 61

21 TENK
NC 60

22 ONEK
NC 59

23 FTA

FS970x
OSCO 58

24 FTB

LQ 64
VCC 57

25 SGND

(14 mm x 14 mm/10 mm x 10 mm)

VCC 56

26 AGND
VCC 55

27 VDDA
VCCS 54

28 SMV
VCCR 53

29 SA
VDDP 52

30 SDB
VDDS 51

31 ADRF
GNDR 50

32 VSSA
DVO 49
ACHO
REFH

RCTO

ACLO
RCTN
CSFB

RCTP
ACH

ACB

ACA
ACL

AX3

AX4

AX1

AX5

AX2
33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

Rev. 4.4 8/46

 FS970X

Pin Description
64 PIN Pin Symbol Description
LQFP Type
pin
1 DPI VSSD Global Ground（-3.2 V）.
2-3 DIO XTALI,XTALO The terminals of crystal oscillator circuit
4 DO BZR The Output terminal of BUZZER function
5 DO IRQO The Interrupt output terminal when updating data
6-9 DIO AD<3:0> The I/O ports of Address and Data Lines
10 DI RD_ When Active_low, read values from FS970X
11 DI WR_ When Active_low, write values to FS970X
12 DI ALE When Active_Hi, AD<3:0> acts as address line

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13 DI CS_ When Active_low, enable FS970X interface
14
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DI
VCC
RST_
Digital power supply（+1.8 V）
Reset all the registers to “0” when Active_low

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16 AIO CPN The connector of the compensation capacitor at ACV function
17 AIO FTC The terminal of pre-filter capacitor
18-22 AIO TENM,ONEM,HUNK,TENK,ONEK The terminal of resistors of router

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23-24 AIO FTA,FTB The terminal of pre-filter capacitor

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25 AI SGND The sensing point of analog ground
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26 API AGND Analog ground（0 V）
27 API VDDA Positive analog power supply（+3.0 V）
28 AIO SMV The input of DCmV function
29 AIO SA The terminal of current function
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30 AIO SDB The negative terminal of reference under resistance measurement
31
32

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API
ADRF
VSSA
The input of the voltage reference of ADC
Negative analog power supply（-3.2 V）.
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33 AI REFH The output of Zener diode

34 AIO CSFB The terminal of Zener diode function
35-36 AIO ACH, ACL The output terminals of AC-to-DC function
37-38 AIO ACB, ACA The connection of AC buffer OPAMP
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39-40 AIO RCTP, RCTN The terminal of OPAMP of AC-to-DC function

41 AIO RCTO The output terminal of OPAMP of AC-to-DC function
42-43 AIO ACHO, ACLO The output terminals of rectify function of AC-to-DC measurement
44-48 AIO AX1-AX5 The input terminal of ADC
49 AO DVO The output terminal SDV through an analog switch control
50 APO GNDR The analog ground of internal voltage regulator (0 V).
51 PO VDDS The output terminal VDD through an analog switch control
52 PI VDDP The power supply of regulator (+3.0 V)
53 DPO VCCR The output of regulator（+1.8 V）
54 DPO VCCS The output terminal VCC through an analog switch control
55-57 DOI VCC Digital power supply（+1.8 V）
58 DO OSCO The output of crystal oscillator circuit (the output frequency can be
programmable)
59-61 NC No use.
62 DO CMP1 The output of comparator
63 DI FCNTI The input terminal of frequency counter
64 P VBAT The terminal of battery
1) D － (Digital)
2) A － (Analog)
3) P － (Power)
4) O － (Output)
5) I － (Input)
6) For example, DIO stands for Digital Input and Output pin.

Rev. 4.4 9/46

 FS970X

7. Typical Application Circuit

1 2 3 4

PB0 VCC VCC

SW2 SW3 SW4 SW5 VSS

J ext1 J ARHCR1

E XROM
BtBacklight BtHz BtPeak BtAH

ARHCR
RCR11M
L3

4
3
2
1
D BKLI 1 2 RBKLI1 D
CR1 VSS
VSS VSS SW1

RT0

RT1

RT2

RT3
180
VCC RFS LED
4.000M Hz
J mVP VSS
J 3a J RS1

XOUT
C10

XIN
TP6 TP5 RS232
mVP SW6 SW7 SW8 SW9 RPB1 VCC
9013 9013 BtFunction BtREC BtRange BtRel 500K 10uF

RFS 2 5
RFS 1 6
P SE N 7
8
CPB1 VSS

RFS 4
RFS 3
3 0 E XROM

BKL I
PB1

ARHCR

P B2
P B1
B0

A6
A5
A4
A3
A2
A1
A0

D7
D6
D5
D4
D3
2 6 AHE
2 8 VSS

P
p26
D3 D6 10nF RST
4004 4004

29

27

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
COMMON

9
8
7
6
5
4
3
2
1
D4 D5
U3

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P4.7 /PSEN
P12 .2 /AHE
EXRO M

VSS

VSS
RST

P12 .1
P12 .0

P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
/A6
P4.5 /A5
P4.4 /A4
P4.3 /A3
P4.2 /A2
P4.1 /A1
/A1 4/A0
D7
P3.6 /A1 3 D6
P3.5 /A1 2 D5
P3.4 /A1 1 D4
D3
SCO
D2 4004 4004 D7

P3.3 /A1 0
P4.6

P3.7P4.0
4004 4004 XIN 31 100 D2
XIN P3.2

P12 .3 /O
F1 XOUT 32 99 D1
XOUT P3.1
1 2 33 98 VCC

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VC1 D0
VC1 P3.0

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VC2 34 97
RLCD1 70K VC2 VCC
1A/600V VC3 35 96 CS
VC3 P2.7
36 95 WR RSIN1
J mA1 J uA1 VCC VCC P2.6
COM 4 37 94 RD 100K
mA uA COM4/P6.3 P2.5
F2 COM 3 38 93 ALE
RA2 RA3 RCPN2 J Ain1 COM3/P6.2 P2.4
1 2 AMP_IN AX1 COM 2 39 92
COM2/P6.1 P2.3
0.99,5W,10ppm 99,0.25W,10ppm COM 1 40 91
100 K Ain BZR1 COM1 P2.2
15A/600V SEG1 41 90 RXD L2 RSO1
2.5kHz SEG1 P2.1
RA1 SEG2 42 FSup01N 89 TXD 3K
SEG2 P2.0
0.01,2W,10ppm VDD SEG3 43 88 RT3 1 2
SEG3 P1.7 VSS
AMP.TEST VSS RCR21M SEG4 44 87 RT2

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SEG4 P1.6
SEG5 45 86 RT1 DioR
SEG5 P1.5
SEG6 46 85 RT0 L1
SEG6 P1.4
COMMON CCPN1 CPB2 SEG7 47 84 AD3
C RCPN1 J notCAP1 J CAP1 RBZR1 CR2 SEG7 P1.3 C
AX2 SEG8 48 83 AD2 1 2
SEG8 P1.2
1k SEG9 49 82 AD1
100 K 4.000M Hz SEG9 P1.1
5.6pF VCC 10nF SEG10 50 81 AD0 DioS

SEG 1 1
SEG 1 2
SEG 1 3
SEG 1 4
SEG 1 5
SEG 1 6
SEG 1 7
SEG 1 8
SEG 1 9
SEG 2 0
SEG 2 1
SEG 2 2
SEG 2 3
SEG 2 4
SEG 2 5
SEG 2 6
SEG 2 7
SEG 2 8
SEG 2 9
SEG 3 0
SEG 3 1
SEG 3 2
SEG 3 3
SEG 3 4
SEG 3 5
SEG 3 6
SEG 3 7
SEG 3 8
SEG 3 9
SEG 4 0
SEG10 P1.0
X970O

POhm
X970I
RPB2
TP2 TP1
I RQO

500K VSS R6
BZR
ALE

AD0

AD1

AD2

AD3
WR

J4
RD

9013 9013
CS

FSUP01 100K

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
DCV+OHM +DT+CAP
AMP.TEST
2

16

15

14

13

12

11

10

CDCPL1

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S EG12
S EG13
S EG14
S EG15
S EG16
S EG17
S EG18
S EG19
S EG20
S EG21
S EG22
S EG23
S EG24
S EG25
S EG26
S EG27
S EG28
S EG29
S EG30
S EG31
S EG32
RPTC1 R5
J 3a U2 R7

S EG33
S EG34
S EG35
S EG36
S EG37
S EG38
S EG39
S EG40
J 13
20M
XTAL I
CPN

VCC

BZR

VSSD

10M,1000V
ALE

XTAL O

PTC,1K,+-5%,25 C
RST _

CS_

W R_

RD_

AD0

AD1

AD2

AD3
IRQO

RSPK1 10nF,1000V
J2
FTC 17 64
OHM +CAP+DT FTC VBAT VBAT
1

O
POhm
C8 R1 TENM 18 63 FCNT1 VSS
TENM FCNT1
4pF 1.1111M
ONEM 19 62
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SPK
SPK1
ONEM CMP1
CR4
10pF R2 HUNK 20 61 NC61
HUNK NC
C3 101.01K
300pF TENK 21 60 NC60 U4
TNEK NC
CR3 D0 3 2 A7
R3 D0 Q0
ONEK 22 59 NC59 D1 4 5 A8
ONEK NC D1 Q1
D2 7 6 A9
10.010K
RFTR1 D2 Q2
20pF 23 58 OSCO D3 8 9 A10
2

J COM FTA OSCO D3 Q3

C2 D4 13 12 A11
R4 1M D4 Q4
390pF FTB 24 57 D5 14 15 A12
J 13 J1 DCV + ACV FTB VCC D5 Q5
D6 17 16 A13
1.0001K D6 Q6
C1 CFTR1 25 FS970/Q64 56 D7 18 19 A14
DCV + ACV SGND VCC VCC D7 Q7
1nF FTC 27nF VSS
1

26 55 1
RAGND1 AGND AGND VCC OE
B AHE 11 B
CON1 CLK
27 54 VCCS COM 3 1 44 COM 4
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SGND COM 1 COM 2 74S374
28 53 SEG2 SEG1
J3 RSM V1
10K SMV VCCR VCC
COMMON SMV SEG4 SEG3 U5
29 52 SEG6 SEG5 A0 10 11 D0
OHM +CAP+DT 909K SA VDDP VDD A0 D0

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SEG8 SEG7 A1 9 12 D1
RSDB1 A1 D1
SDB 30 51 SEG10 SEG9 A2 8 13 D2
RHz1 J6 SDB VDDS VDDS A2 D2
AX1 SEG12 SEG11 A3 7 15 D3
100K A3 D3
50k ADRF 31 50 SEG14 SEG13 A4 6 16 D4
mV ADRF GNDR AGND A4 D4
Pvat1 Pvss 1 SEG16 SEG15 A5 5 17 D5
J DTH A5 D5
Vbat vs s AX2 32 49 DVO SEG18 SEG17 A6 4 18 D6 VCC
VSSA DVO A6 D6
3 19
RCT O

ACHO

ACL O

A7 D7
REF H

RCT N

RRF2
CSF B

RCT P

SEG20 SEG19
DT A7 D7
ACH

ACB

ACA
ACL

AX3

AX4

AX1

AX5

AX2

249K CRF1 SEG22 SEG21 A8 25

27nF A8 J9
VSS SEG24 SEG23 A9 24 27
A9 WE
VBAT VSS RRF1 Text FS970/Q64 SEG26 SEG25 A10 21
Fo P R

J7 RDT2 RDT1 A10

PDT 49.9K SEG28 SEG27 VCC A11 23 22 PSEN
33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

A11 OE
SEG30 SEG29 A12 2 A14
CPN

A12
AX4

AX1

AX5

AX2

DT 900k 100k
REF H

RCT N

RCT O

ACHO

ACL O

J5 J 10
CSF B

RCT P

AGND ACOUT SEG32 SEG31 A13 26 20

ACH

ACA
ACB
ACL

A13 CE
VCC VDD AGND VDD AX4 SEG34 SEG33 1
Except Hz A14
AGND SEG36 SEG35
RCS1 SEG38 SEG37 28 14
412K VCC VCC GND VSS
RAC2 SEG40 SEG39 A14
C4 C5 C7 C6 60K 28256
10uF 10uF 47uF 10uF RZNR1 AGND CON22X2 VCC C11
VDDS DRCTP1
82K
CRM S1 J9 J10
VSS AGND VSS VSS ACH RAC3 1N914 1uF 28256 : VCC A14
VBAT U1 30k DRCTN1 VSS 27256 : A14 VCC
S-81250 VDD VDDS 10uF DZNR1
U7 LM385/1.235V
2 3 1 8 1N914 U6
Vin Vout Cc COM
G ND

FO

CS 1 8
A CS VCC VCCS A
2 7 CRM S2 RAC1 ALE 2 7 VCCS C12
Vin Vdd VDDS SK NC
RRG1 10uF AGND WR 3 6
RCT1 DI TEST
Battery1 866K 3 6 ACL 10K RD 4 5
PD Out DO GND VSS
1

9V 15k 1uF
4 5 S-93C46ADP VSS
VSS Vss Cav
AGND
C9 RRG2 AD737 CAC1 Title
D1 0.1uF 187K CRM S3 ACOUT CAVG1 CAVG2
IN4002 100nF 100nF
10uF Size Number Revision
RAVG1 RAVG2
33uF A2
20k 20k
Date: 4-Jan-2004 Sheet of
VSS File: C:\Do cuments a nd Setting s\yenhong \ 桌面\桌面Drawn
暫存\DM By:
M _CLUB.D DB
1 2 3 4

Rev. 4.4 10/46

 FS970X

8. Regulator
VBAT VCC

VDD

VCCR
53
VDD VDDP
S81250 REFH
IN OUT VDDP
52 20 uF
COM

50
GNDR AGND

20 uF

'
9V Battery
ENGNDR_

y
ef pe NE FS970x Regulator 32
20 uF

VSSA

nl
VSS

en es
O
Graph 1. FS970X Regulator Block-diagram
r R ro TU
FS970X Regulator, as shown in Graph 1, needs to be connected with a S81250 low-cost regulator to convert
the battery voltage above 6.8V to VDD voltage of approx. 6.3V. There are two functions of VDD power: one is
er rti
the positive voltage (negative voltage to be VSSA) of analog circuit (or regulator), and the other is as the

ce
reference voltage of regulators.
Fo P R

The power of the digital circuit in the chip is supplied by VCC. The digital signal ground is VSSD. The digital
signal ground VSSD and negative supply of analog circuit VSSA in the chip are connected by chip foundation of
thousand ohms.
FO

As shown in Graph 1, the FS970X regulator circuit refers respectively to the voltage of VDDP and REFH; at the
same time, adjusting to the voltage of VCCR, GNDR and VSS to supply the chip. If VSS is set to be 0V, the
voltage of VCCR and GNDR will be 5V and 3.2V. This analog supply can directly supply AD737 to enable the
meter to measure the true root mean square of AC signal.

The supply source of FS970X can be selected by users, either from the chip itself or from external connection.
The analog supply within the chip is provided by VDDA, AGND and VSSA. Thus, directly feeding the output of
regulator VCCR, GNDR and VSS into VCC, AGND and VSSA will supply the chip itself. If the system has its
own supply, it can be connected directly to VCC, AGND and VSSA, instead of using VCCR and GNDR.

The power consumption of analog is static DC current, with an equivalent DC power consumption. The major
reason that will affect this DC power consumption is the change between each function. The power
consumption of FS970X analog parts is designed to be under 1.2mA and the digital parts under 0.5mA.

To be even more stringent on power consumption design under saving mode, connecting the chip’s analog
supply VDDA to VDDS will reduce the idle VDDA consumption to 0 under saving mode. For details about VDDS,
please see 5.3.

Rev. 4.4 11/46

 FS970X

Low Voltage Detector

VBAT

360K LBS

BATTER
Y
9V CMP LBO

303K
ENLBS

'
AGND

y
ef pe NE VSSD

nl
Graph 2 Low Voltage Detector

en es
O
Low voltage detector is shown as Graph 2. After the voltage of VBAT is divided as LBS by resistor, it will flow
r R ro TU
into low voltage detector. The output of the detector is LBO, used to judge whether the battery voltage VBAT is
lower than 6.8V. If it’s lower than 6.8V, the output is “Hi”, meaning that it needs a battery change. Before
reading LBO, set ENLBS to “Hi”. After approx. 0.1 ms, pull it back to “L” to read LBO.
er rti
ce
The voltage of LBS can flow into ADC, controlled by ADC multiplexers. It can also be directly measured by ADC.
The battery voltage is calculated as Formula 1.
Fo P R

17
Formula 1 ..................................................... VBAT   VLBS
8
FO

Under saving mode, setting ENGNDR_ (MISC2<1>) to “H” will turn off GNDR in order to save power
consumption.

Saving Mode
In FS970X, all the power-consumption related circuits, except for VCCR generator, can be turned off by
FS970X registers to save power. The power-consumption related control signals and components are shown in
Chart 2.

If all of the FS970X components are turned off, only VCCR regulator will still be running. This keeps the chip
power consumption under 10 uA.

According to the setup in Chart 2, the power consumption of VDDA may drift. Therefore, aside from the setup
procedures in Chart 2, the supply of VDDA should come from VDDS considering the saving mode. By doing
so, S81250 will be the only component that consumes power under saving mode.

Register Control circuit Saving mode value Related power

consumption circuit

RGD>3:0> MODE<3:0> 000x Fixed voltage generator

SRF<7:6> SOSR<1:0> 00 Ohm power supply

SCP<0> CMPEN1 0 Comparator

Rev. 4.4 12/46

 FS970X

AFT<6> RCTEN 0 Full-wave retifier

AFT<4> ACEN 0 AC buffer

ADG<7> ENAD 0 ADC

SETADC<7:6> ENVDS, ENVCS 00 On/off power output

MISC1<4> ENOSCO_ 1 OSCO output

'
MISC1<3> ENXTL_ 1 Crystal oscillator circuit

y
ef pe NE MISC2<1> ENGNDR_ 1 AGND voltage regulator

nl
Chart 2. Saving Mode Setup.

en es
O
On/Off Power Output
r R ro TU
VDD P(52)/
VCC (55)
er rti
VDD S(51)/
VCC S(54)

ce
Fo P R

ENVD S/
ENVC S
FO

Graph 3 On/Off power output.

VDDS and VCCS are the on/off power output of VDDP and VCC. The circuit is shown in Graph 3. VDDP/VCC
flows into PMOS, output from VDDS/VCCS. PMOS on/off status is controlled by ENVDS/ ENVCS. When set
under 0 and 1, PMOS is respectively under open/close status.

Connecting VDDA to VDDS under saving mode, this will decrease VDDA power consumption to 0.

Rev. 4.4 13/46

 FS970X

9. Clock and Buzzer Generator

Clock Generator

XTALI ENXTL_
2
FSDIV
TBDIV
4.0000 MHz

ENBP
3
CNTBP
XTALO CLK
DIVIDER FS

'
FBP

y
ef pe NE BZR
4
FTB

ENOSCO_

nl
Buzzer
58
OSCO
OSCO

en es
VBAT

O
FTB
r R ro TU
1/F TB
FS
1/F S
er rti
ce
Graph 4 Clock Generator.

Clock generator is shown in Graph 4. It can be connected to a 4.000 MHz crystal oscillator to produce 4.000
Fo P R

MHz clock frequency. It can then be divided to FS, FTB, and FBP frequencies by a divider. Among these, FS is
used by ADC. (please refer to 8.4 for details.) FTB is used by digital circuits, such as the reference frequency of
frequency counter (please refer to section 9.1). FBP is used by buzzer to initiate buzzing.
FO

FTB and FS are respectively controlled by ENXTAL_. TBDIV and FSDIV. The true value Chart is shown in
Chart 3:

ENXTAL_ TBDIV FTB FSDIV FS

L L 1.0000 MHz L 166.67 kHz

L L 1.0000 MHz H 83.33 kHz

L H 125.0 kHz L 166.67 kHz

L H 125.0 kHz H 83.33 kHz

H X 0, (L) X 0, (L)

Chart 3. FTB / FS generator true value Chart.

Rev. 4.4 14/46

 FS970X

Buzzer Generator
FBP generator is controlled by ENBP. CNTBP and CMP1. The true value Chart is shown in Chart 4.

ENBP CNTBP CMP1 FBP

H X X 2.6 kHz

L L X 0, (L)

L X L 0, (L)

'

y
ef pe NE X H H 2.6 kHz

nl
Chart 4. FBP true value Chart

The output of buzzer, BZR, is an open drain output. It can be connected to an external pull-up resistor to pull

en es
the “Hi” output to the required voltage. When ENBP is “Hi” or CMP1 and CNTBP are both “Hi”, BZR will produce

O
approx. 2.6 kHz square-wave output to initiate buzzer. ENBP and CNTBP can be set up directly by digital
r R ro TU
interface while the value of CMP1 is related to the measurement status. Please refer to Function Network for
details.
er rti
When ENOSCO_=0, the square-wave output of OSCO is fixed to be 2.000 MHz. When ENOSCO_=1,the fixed

ce
output is 0. This will save VCC power consumption.
Fo P R
FO

Rev. 4.4 15/46

 FS970X

10. Function Network

10K 30K
AGND

FUNCT ION
FUN1,2

FUN1 60K
10 uF 1 M
FUN2
1M 27nF
AGND 27 nF

ACHO

ACLO

RCTO
RCTN

RCTP

ACH
ACA

ACB

ACL

FTC
FTA

FTB
MSB LSB 38 37 40 39 42 43 41 36 35 23 24 17
7 6 5 4 3 2 1 0
AFT<7:0> EXTD RCTEN ACDIV ACEN ENSCHMT CAPM CPN<1> CPN<0> ACDIV
SCP<7:0> SCMPH<3:0> SCMPL<1:0> 0 CMPEN1 FTR FTR
14K 15K 15K
SIN<7:0> SINH<3:0> BPFTR SINL<2:0>
ACDIV ACL ACH
SRF<7:0> SOSR<1:0> SRFH<1:0> FTR SRFL<2:0>
RGD<7:0> RANGE<3:0> MODE<3:0>
BPFTR
BPACBF
INH

'
RCTOP

y
ACBUF ACBO

ef pe NE
CMPH
mA+uA RCTEN
ACEN

SINH<3:0>

SMV FTIN

nl
mA uA SDV
10A SA
SINL<2:0>
99 29 SGND
SA SA SDB SGND INL INL
0.99 ACH SCV
AX5 SDV
SRFH<1:0>
0.01 ADRF ACL
COMMON ACBO SDB ADRF VRH VRH

en es
10K 25 CMPH AX2 SCV
SGND SGND AX1 AX3 SMV
SRFL<2:0>

O
AX2 AX4 AX3
AX3 AGND VRL VRL
r R ro TU
INLMUX VRHMUX
AX4 SCV
LBS SDB
AGND
49 SMV
INHMUX SCMPH<3:0>
DVO SDV AX3
SMV CAPTG AX4
endvo
SDV AGND
SA CMPH
VRLMUX
DCmV + OHM ADRF
900
+ CAP + DT 28 AX1 CMPH
K
er rti
SMV SMV AX2
Vcntd1 CAPTG
Vsrc1 62

ce
DCmV DCmV AGND Vcapd1 CMP1
330 sdt Vcapd2
CMPEN1
pF CMPEN2
100 K 30 Vcapc2
SDB SDB Vcapc1 SCMPL<1:0> CMP1 FCNT
CPL
1 M SGND
AGND
Fo P R

AGND cap CMPEN2

Vsrc1
VRH
Vcapc2 CMPL
onek<0> VRL
Vrfh
SCV CMPHMUX cntd
DCV + ACV + DT 22 63
onek<1> Vcntd1
ONEK SDV FCNTI
CMPLMUX
1K
DCV+ACV
onek<2> CAPM
CAPTG CMPEN2
FO

cap
Vcapc1
tenk<0> 61
AGND Vcapc2 CAPL
CMP2 CMP2
Vcapd2
21 AX2
tenk<1> Vcapd1
TENK
CAPMUX
10K

tenk<2>
(VDD) TBDIV
SOSR1:0
hunk<0> CAPTG

20 AX5 ADRF ADRF

hunk<1> osr
HUNK Vrefh
VB+ 100K  osr OSRC AGND
OSRO
OSRC
hunk<2>
osr 0000_0000 AFT

onem<0> OSRMUX 0000_0000 SCP

1.5K 19
onem<1> 0000_0000 SIN
ONEM
1M
0000_0000 SRF
onem<2>
Vcntd
OHM + CAP
cap Vsrc1 vsr
0000_0000 RGD

DT sdt Vcapd1 TBDIV

tenm<0> vsr
DCV + OHM Vcapd2 33
+CAP 18
cntd MODE<3:0>
Vcapc2 REFH REFH
FUSE PTC TENM
tenm<1> endvo RANGE<3:0>
Vcapc1
10M Vrfh

VOLT+OHM+ tenm<1> onek<2:0> VSRC

DT+CAP
tenk<2:0>
hunk<2:0>
EXCEPT CAP
CPN<0> onem<2:0>
AX1

AX2

AX3

AX4

AX5

16
tenm<1:0>
CPN
FUNCTION
AGND DECODER
CPN<1>
AX1

AX2

AX3

AX4

AX5

Graph 5. FS970X function network diagram

Function Network, as shown in Graph 5, includes six major parts: function decoder, area network switch, fixed
voltage generator, Ohm power supply, multiplexers and pre-filter, operation amplifier and comparator.

Rev. 4.4 16/46

 FS970X

Function Decoder
Function decoder includes two set of input – MODE and RANGE. RANGE controls area network switch to
determine measurement range, and MODE controls the function network signal to determine measurement
mode.

As shown in Chart 5, the setup of register MODE3:0 (represents MODE<3:0>) can decode the control signals
such as cap. Sdt. Vsr. Cntd and endvo. It also controls the measurement mode and operation status of
function network.

When High Bandwidth AC is capable of processing AC signal more than 1 MHz, SDV can be the direct output

'
of SDV. Refer to section 7.5.1 for details.

y
ef pe NE Measurement Mode MODE3:0 cap sdt vsr cntd endvo

nl
DCmV, DCV, ACV, and PKH 0000 0 0 0 0 0

en es
DIODE 0001 0 1 0 0 0

O
r R ro TU
High Bandwidth AC 0011 0 0 1 0 1

Resistor x, Continuity 100x 0 0 1 1 0

er rti
ce Capacitor x 101x 1 0 1 0 0
Fo P R

Chart 5 Control of Measurement mode .

As shown in Chart 6, area network switch is controlled by both MODE3:0 and RANGE3:0. The four bits in
RANGE directly controls network resistor path: 1k
FO

path of 10M d by
Formula 2 e  abcd  f

Under Range Divider mode, area network becomes decay network. It controls area network on/off status to
determine different measurement range according to the setup of RANGE3:0. Under Resistor mode, area
network will become the reference resistor initiated by appropriate returned Ω supply. It selects different
reference resistor to determine different measurement range according to the setup of RANGE3:0. Resistor I or
II represent respectively whether reference resistor is parallel with the 10 M resistor. Under Capacitor mode,
area network becomes charge/discharge resistor with power supply. Capacitor I or II also represent whether
charge/discharge resistor is parallel with 10 M resistor.

Range Mode MODE3:0 RANGE3:0 onek2:0 tenk2:0 hunk2:0 onem2:0 tenm1:0

Range Divider 00xx abcd 0aa 0bb 0cc 0dd 0e

Resistor I 1000 abcd aaa Bbb ccc ddd f1

Resistor II 1001 abcd aaa Bbb ccc ddd ff

Capacitor I 1010 abcd aaa Bbb ccc ddd f1

Capacitor II 1011 abcd aaa Bbb ccc ddd ff

Chart 6 Decay network switch.

Rev. 4.4 17/46

 FS970X

10..1 Area Network Switch

Combining area network switch to an external high-precision resistor becomes a measurement network. It
transfers the signal of the sensor into suitable voltage range for ADC and measures the signal. The function
decoder controls the measurement range and on/off status. See Graph 5 and Section 7.1 for details.

Take DC5V as an example, using Chart 6 as reference, setting MODE3:0=0000 and RANGE=0001 will make
onek2:0=tenk2:0=hunk2:0=000, onem2:0=011, and tenm1:0=01. When corresponding this value to the area
network of the low-left corner of Graph 5, all the switches are under open status except for tenm<0>, onem<1>,
and onem<2>. Thus, connecting to an external resistor network will make up a ten-times decay circuit to
achieve the decay function required by DC5V.

'

y
ef pe NE

nl
Fixed Voltage Generator
When under capacity measuring, short testing, and resistor measuring, all the required power supply is
provided by this block.

en es
O
r R ro TU
The output of this block includes Vcntd, Vsrc1, Vcapd1, Vcapd2, Vcapc2, Vcapc1, and Vrfh. The output voltage
is controlled by vsr and TBDIV, as shown below. Vsr comes from the decoding of MODE3:0 input by function
decoder. TBDIV can be directly set up by register.
er rti
ce INPUT OUTPUT
Fo P R

vsr TBDIV Vrfh Vcapc1 Vcapc2 Vcapd2 Vcapd1 Vsrc1 Vcntd

1 0 1.2 V 0.8 V 0.64 V 0.56 V 0.4 V 0.16 V 0.04 V

FO

1 1 3.1 V 1.58 V 1.65 V 1.45 V 1.52 V 0.4 V 0.1 V

0 x 0V 0V 0V 0V 0V 0V 0V

Chart 7. Voltage output of fixed voltage generator.

When TBDIV=0, the block refers to the voltage of REFH, as shown in Chart 7, REFH=1.2V. And if REFH =
0.6V, the voltage generated are 0.6V, 0.4 V, 0.32 V, 0.28 V, 0.2 V, 0.08 V, and 0.02 V. When TBDIV=1, it refers
to the voltage of VDD, as shown in Chart 7, which is the voltage output of VDD voltage being 3.1 V under
normal condition.

Vrfh is the reference voltage of ohm power supply when measuring resistance and capacity. Vcapc1 and
Vcapd1 are respectively the reference voltage of charge/discharge comparator Vcapc1 (charging) and Vacpd1
(discharging) when measuring capacity. Vcapc2 and Vcapd2 are the second set of reference voltage of
charge/discharge comparator. According to the measuring capacity range, one set of the reference voltage can
be selected by CAPM setup of register. (See Chart 14 for details). Vcntd is the reference voltage of comparator
under short testing. There is no special function of Vsrc1, users can customize it according to their needs.

Rev. 4.4 18/46

 FS970X

Ω Power Supply
Ω power supply flows directly into decay network, providing voltage as shown in Chart 8. Among them, cap is
determined by function decoder. When cap=0, it’s not under capacity measuring mode. For DMM application, it
represents resistance measurement. At this time, the output of Ω is controlled by SOSR1:0, as shown in Chart
8. SOSR1:0 can be set up by register.

When cap = 1, it’s under capacity measuring mode. At this time, the output of Ωpower supply is irrelevant to
SOSR1:0, but controlled by TBDIV and CAPTG. When TBDIV = 0, Vrfh is approx. 1.2 V, and the
charge/discharge voltage is approx.1.2V. When TBDIV=1, Vrfh is approx. 3.1 V (VDD), and the
charge/discharge voltage is also approx. 3.1 V. This improves the charge/discharge speed of capacity

'
measuring. CAPTG is the output of comparator CMP1. It controls the charge/discharge selection of Ω

y
ef pe NE
power supply to the measuring capacity.

nl
When output is VDD, theΩvoltage is the voltage on the pins, which will be affected by on/off resistors on the
path so the real voltage of the load will be affected by the load.

en es
When output is other than VDD, the on/off resistor can be ignored because operation amplifier is high gain and

O
negative feedback. The real voltage of the load affected by the load can be ignored as well. Under all kinds of
r R ro TU
output, the maximum power is approx. 1.2mA.
er rti
INPUT OUTPUT

ce cap TBDIV CAPTG SOSR1:0 OSRO

Fo P R

0 x x 00 high impendence
FO

0 x x 01 AX5

0 x x 10 Vrfh

0 x x 11 VDD

1 0 0 Xx Vrfh (REFH)

1 0 1 Xx AGND

1 1 0 Xx Vrfh (VDD)

1 1 1 Xx AGND

Chart 8 Ω power supply true-value Chart

Rev. 4.4 19/46

 FS970X

Multiplexers and pre-filter

Through multiplexers such as INHMUX, INLMUX, VRHMUX and VRLMUX, selectable ADC signals are FTIN,
INL, VRH, and VRL. FTIN and INL first flow through a RC pre-filter, and then into full differential amplifier
input INH and INL of ADC. At the same time, they can bypass the RC pre-filter and flow directly into ADC
through BPFTR and FTR.

Each output path is directly controlled by registers. Details are shown in Chart 9, Chart 10, Chart 11 and Chart
12.

Name SMV SDV SA SGND SDB ACH AX5 ADRF

'

y
ef pe NE SINH 0000 0001 0010 0011 0100 0101 0110 0111

nl
Name ACBO CMPH AX1 AX2 AX3 AX4 LBS NA

en es
SINH 1000 1001 1010 1011 1100 1101 1110 NA

O
r R ro TU
Chart 9 FTIN multiplexers setup

Name SGND SCV SDV ACL SDB AX2 AX3 AX4

er rti
ce SINL 000 001 010 011 100 101 110 111
Fo P R

Chart 10 INL multiplexers setup.

Name ADRF SDV SMV AX3

FO

SRFH 00 01 10 11

Chart 11 VRH multiplexers setup.

Name AGND SCV SDB SMV AX3 AX4 AGND

SRFL 000 001 010 011 100 101 110

Chart 12 VRL multiplexers setup.

The signal into the comparator can be selected by comparator multiplexers – CMPMUX. The path is controlled
by registers as well, as show below.

Name SMV SDV SA ADRF AX1 AX2 Vcntd Vsrc1

SCMPH 0000 0001 0010 0011 0100 0101 0110 0111

Name Vcapd1 Vcapd2 Vcapc2 Vcapc1 SGND AGND VRH VRL

SCMPH 1000 1001 1010 1011 1100 1101 1110 1111

Chart 13 CMPH multiplexers setup.

Rev. 4.4 20/46

 FS970X

CPL is the negative input of CMP1, controlled by cap, cntd, SCMPL1:0, CAPM, and CAPTG. Details are shown
in Chart 14.

When cap=0 and cntd=0, the output of CPL is irrelevant to CAPM and CAPTG. It is directly selected by
SCMPL1:0.

When cap=0 and cntd=1, it’s under short testing mode. The output of CPL is fixed to be Vcntd.

When cap=1, it’s under capacitor measuring mode. At this time, the output of CPL is irrelevant to cntd and
SCMPL1:0. When CAPM=0, it means low and medium capacity measuring. The output of CPL is controlled
by CAPTG; they are Vcapc1 and Vcapd1. When CAPM=1, it means high capacity measuring. The output of

'
CPL is controlled by CAPTG. They are Vcapc2 and Vcapd2.

y
ef pe NE

nl
I cap 0 0 0 0 0 1 1 1 1

N
cntd 0 0 0 0 1 x x X x

en es
P

O
r R ro TU
SCMPL1:0 00 01 10 11 xx xx xx Xx xx
U

T CAPM x x X x x 0 0 1 1
er rti
CAPTG x x X x x 0 1 0 1

ce
Fo P R

OUTPUT CPL AGND Vsrc1 Vcapc2 Vrfh Vcntd Vcapc1 Vcapd1 Vcapc2 Vcapd2

Chart 14 CPL multiplexers setup.

FO

Rev. 4.4 21/46

 FS970X

Operation Amplifier and Comparator

The block composed by operation amplifier and comparator include AC buffer block, full-wave rectifiers block,
and comparator block.
10 k  90 k 

AGND

ACA

ACB
38 37

'
ACDIV

y
ef pe NE ACDIV

nl
BPACBF

en es
O
ACBUF ACBO
r R ro TU
CMPH
ACEN
er rti
Graph 6. AC buffer block.

ce
As shown in Graph 6, buffer block is controlled by ACBUF and ACDIV. It becomes a gain network when
connecting with an external resistor. Whether ACBUF works or not can be directly controlled by ACEN. When
Fo P R

ACEN=0, it turns off the buffer and the output becomes high impedance.

th
Signal enters through CMPH, and flows out from ACBO or the 37 pin ACB. ACDIV can at the same time
FO

controls the gain. If ACDIV=0, the gain of the buffer is 1. If ACDIV=1, the gain of the buffer is determined by
the external network resistor. In Typical Application Circuit, the gain becomes 10.

When the gain is 1, the 100 kHz side wave flowing through the buffer will be reduced to lower than 0.5%. The
bandwidth of AC is limited by the frequency response of full-wave rectifier.

th
If the signal bandwidth is higher than100 kHz, let BPACBF=1, it will change the output source to the 38 pin
(ACA) instead of AC buffer.

ACHO
42

15 k  EXTD

15 k  EXTD

43
ACLO

38 12.3 k 
RCTP
41
RCTOP RCTO
40
RCTN
RCTEN

Graph 7. Full-wave rectifier switch block `

Rev. 4.4 22/46

 FS970X

As shown in Graph 7, the AC signal, inputting from RCTP and going through the rectifier, will obtain a full
differential amplifier signal from ACHO and ACLO. It will then be connected to an external RC low-pass filter
network to do the arithmetic average. The result value, a absolute average AC/DC voltage, then flows into ADC
and displays.

The full-wave rectifier of FS970X has built in the required resistor. And the rectifier diode is controlled by EXTD
to select built-in or externally connected. When EXTD=0, it means that the bandwidth of the built-in diode is
3kHz under precision of 1%. When EXTD=1, it means that the bandwidth of the external diode using 1N914 is
10kHz under precision of 1%. It can increases the bandwidth of the rectifier if using faster diode or adding a
high-frequency compensation circuitry of full-wave rectifier. The enable capability of the rectifier is controlled by
RCTEN. When RCTEN is Lo, turning off the operation amplifier will save power consumption.

'

y
ef pe NE 62
CMP1

nl
ENSCHMT
CPL
FCNT/
CMP1
CAPTG

en es
CMPH

O
CMP1EN
r R ro TU
Graph 8. Comparator Block-diagram.
er rti
As shown in Graph 8, comparator CMP1 can directly set the enable action of control register CMPEN1. And the

ce
Schmidt trigger function of the comparator can be selected by enable ENSCHMT. When ENSCHMT=0, the
comparator has no delay, suitable for capacity measurement. When ENSCHMT=1, the comparator has the
Fo P R

delay voltage of approx. 0.1VRMS, suitable for frequency measurement.

The negative input is CPL, as shown in Chart 14. The positive input is CMPH, as shown in Chart 13. The
FO

output flows directly into frequency counter through FCNT or controls the charge/discharge function of capacity
measurement by CAPTG (as shown in Chart 14)It can also be transferred through Pin 62 (SMP 1)by a reverser
or the logic value can be obtained by the control register. (as shown Chart 18).

10..1 Bandwidth of AC Signal

According to section 7.5，When providing appropriate frequency compensation to decay network, FS970X chip
can directly process the AC signal under the frequency of approx. 100 kHz.

If the bandwidth of AC signal is over 100 kH, the AD buffer ACBUF of FS970X will be unable to process. Thus,
setting BPACBF=1, the high-frequency signal will bypass the AC buffer, and flow out directly from ACA, as
shown in the upper left corner of Graph .

However, when the bandwidth of the signal is higher than 1 MHz, if the signal flows from SDV, through
CMPHMUX to ACA, the on/off resistor and parastic capact on the path will decay the high-frequency signal
dramatically, causing problems to frequency response.

Therefore, when processing AC signal higher than 1 MHz, setting MODE3:0=0011 will make endvo=1. At this
time, the signal of SDV, through the CMOS switch controlled by endvo, flows directly out from DVO, as shown
in the upper left corner of Graph 5.

Rev. 4.4 23/46

 FS970X

11. Analog to Digital Converter (ADC)

The operating theory of - ADC

This high-resolution ADC adapts the modulation of delta and sigma. It samples the consecutive analog input
signal by the sampling frequency of far higher frequency width input signal. It will then be converted into
one-bit code by the modulation of delta and sigma. It then filters the high-frequency noise of Σ-Δ converter by
the digital filter in the chip. It becomes high-resolution digital coding to be applied in high-resolution DMM.
Besides, this kind of converter only performs a 1-bit transfer on the analog-end; therefore, it’s with better linear
characteristics. The signal input and reference voltage input will be full differential amplifier input, with good
CMRR, which can reject the common mode signal.

'

y
ef pe NE
Vin ANALOG
INTEGRATOR
DIGITAL LOW PASS
DECIMATION Dout

nl
ANALOG FILTER
INPUT
COMPARATOR

en es
Vref, -Vref, -Vref, Vref, Vref, Vref,... 1, -1, -1, 1, 1, 1,....
DAC

O
r R ro TU
Graph 9. Σ-Δ ADC concept diagram.

As shown in Graph 9, Σ-Δ ADC includes an analog differentor , an integrator, and a comparator, a one-bit ADC
and a digital low-pass filter. The analog input signal is taken from the consecutively sampled input, and
er rti
deduct it directly from the expected voltage. The difference will then flow into analog integrator, then product a

ce
predicted digital by the comparator. It will then be converted to the expected voltage（+Vref or –Vref ）by ADC,
reversely feed in to the integrator to get a stable negative feedback. The integrator has unlimited gain to DC;
Fo P R

therefore, if the speed of change of input signal is far smaller than the speed of sampling, the average of the
expected voltage signal of theΣ-Δ converter will be very close to the input signal. It’s considered equivalent
under certain resolution. Thus, the one-bit digital converted from the comparator is equal to the analog signal
FO

value  Vref. Therefore, take the one-bit digital and perform an arithmetical average by the digital filter to get a
high-resolution Σ-Δ digital.

Transfer Function & Non-ideal affect

vref

vx ADC Dx

Graph10. ADC.

As shown in Graph 10, there are two sets of input and one set of output in ADC – voltage input v x , reference
voltage input v ref , and ADC output D x . The ideal transfer function is:
vx
Formula 3 ........................................................ Dx  G ' 
v ref

G ' represents the gain value of the ADC.

However, the ADC in reality is not ideal. The relationship is:

v x  vos v v
Formula 4 ..................................................... Dx  G '   G '  x  G '  os
v ref v ref v ref

Rev. 4.4 24/46

 FS970X

G ' and v os represent respectively the gain and the offset voltage of ADC. They can both be affected during
manufacturing, and vary every single chip

Under most of the applications of ADC, reference voltage is a fixed value Vrrf . ADC converts the variable
voltage v x into an equivalent value as Vrrf . Examples are AC/DC voltage measurement and AC/DC currency
measurement of DMM. In this kind of application, reference voltage is fixed; thus, Formula 4 can be simplified
as:
vx
Formula 5 ........................................................ Dx  G '   Dos
Vref

'
Dos is a fixed value.

y
ef pe NE
However, in the application of DMM, the most often used type of measurement of resistor is scale-type
measurement. The reference voltage v ref will vary with resistor, not a fixed value. Formula 5 will not reflect

nl
the actual situation, and needs to be modified as:

en es
Formula 6 ........................................................

O
v
 
D x  G ' x  Dos v ref  G '  x  Dos R x 
R
r R ro TU
v ref Rref

 
Whereas, Dos v ref is the function of reference voltage. In the application of the measurement of scale-type
er rti
resistors, we will learn that Dos R x  is related to resistor R x .

ce
FS970X includes two kinds of ADC output: high-resolution, low-speed and low-resolution, high-speed. Under
Fo P R

high-resolution, low-speed output, the offset voltage has been eliminated. Its transfer function converts from
the ideal linear from Formula 3. Under low-resolution, high-speed output, the offset voltage still exists. The
transfer function comes from either Formula 5 or Formula 6, according to different condition. See Chapter 8 for
FO

details.

Function Gain Setup

a
0.5
ADG<0>

b x
0.5 1.0

+ +
to to
ADG<1> ADC ADG<4> ADC
VIN signal
VREF reference
c input y input
0.25 0.25
ADG<2> ADG<5>

d
0.1
ADG<3>

Graph 11. FS970X Gain setup.

As shown in Graph 11, the input of FS970X ADC includes four different gain paths. They are independently
controlled by ADG<3:0> (4 bits) of the register. The input of reference voltage includes two different gain
paths. They are independently controlled by ADG<5:4>(2 bits) of the register. All the gain values are
approximation. Precise gain values are only available after calibration.

Rev. 4.4 25/46

 FS970X

With suitable gain option control, all kinds of measurement can be applied to the best dynamic range of ADC.
Chart 15 shows the setup of three typical functions and ADG<5:0> in the application of DMM.

st nd rd
1 function 2 function 3 function

ADG<5:0> 01_0011 11_0111 11_1000

Reference voltage gain（GREFi） 1.0 1.25 1.25

Input voltage gain（GSIGi） 1.0 1.25 0.1

'

y
ef pe NE Chart 15 970x Typical ADC function setup.

nl
The measurement transfer functions of each function is:
GSIGi v x
Formula 7 Dx  

en es
G REFi v ref

O
r R ro TU
The reference voltage of each function and the gain approximation of the input voltage are shown in Chart 15.
The actual precise gain value and offset voltage should be obtained from calibration.
er rti
ce
Digital Filter
Fo P R

As shown in Graph 9, the 1-bit output from the comparator must go through a digital low-pass filter and perform
calculation similar to arithmetic average to become a high-resolution multi-bit resolution. The transfer function
of digital filter used by 970x is:
FO

1  sin Nf f S  
2

Formula 8 H  f   2  
N  sinf f S  

Whereas, N is the number of the filter (TAP).

Assuming the sampling frequency of the ADC is 166kHz and the number of the filter is 16600, the frequency
response Graph of the filter is shown as Graph 9. The first zero-point would be found at:

f S 166000 Hz
Formula 9 f Z1    10 Hz
N 16600

Thereafter, all the integer multiple points of the first zero-point occur zero-point. The signal around the
zero-point will be completely filtered out by the filter. So the frequency responses as shown in Graph 12, all
have good suppressing effect to the noise of 50 Hz and 60 Hz. By the same token, assuming the sampling
frequency is 83kHz, and the number of the filter is still 16600, then, the first zero-point position can be
calculated as 5 Hz.

Rev. 4.4 26/46

 FS970X

There are two this kind of programmable digital filters in

FS970X, namely, COMB1 and COMB2. Their output is 0

SUM1 and SUM2 respectively. The number of COMB1is -20

higher, often used to measure high resolution. And the -40

number of COMB2 is lower; its high-speed, low-resolution -60

output can be used on peak-hold sampling and analog bar

dB
-80
graph.
-100

The numbers of COMB1 and COMB2 are both -120

programmable. They can be set by TPS1 and TPS2 -140

respectively, as shown in Chart 16. Taking the sampling

'
-160
0 1 2

frequency of 166.7 kHz as an example, the location of the

y
10 10 10

ef pe NE
Hz

first zero-point is calculated as Chart 17.

 Graph 12、Digital filter frequency response of 970x

nl
The actual resolution of each status is defined by the actual
measurement.

en es
O
COMB1（TPS1） COMB2（TPS2）
r R ro TU
st st
TPSX<1:0> Number（N） 1 0-point frequency Number（N） 1 0-point frequency
（Hz） （Hz）
er rti
ce 11 16384 10.17 256 651.17
Fo P R

10 8192 20.34 128 1302.34

01 4096 40.68 64 2604.68

FO

00 2048 81.40 32 5209.38

Chart 16. Digital Filter number setup and 1st zero-point location（FS=166.7 kHz）.

Because of the delay of the digital filter, the bandwidth of the signal pulse needs to be greater than four-times
output period of the input signal of ADC. For example, when set TPS2 to 00, the output period of COMB2 will
be:
1
Formula 10 ...................................................... sec  192 us .
5209

Therefore, the pulse bandwidth of the input signal must be greater than 4  192 us  0.769 ms so that the
value can be effectively converted by ADC. When the sampling frequency (FS) is 166.7 kHz, the output reading
of SUM2 from COMB2 can detect to the smallest pulse bandwidth and TPS2, as shown in Chart 17.

TPS2<1:0> 00 01 10 11

Output frequency 5.2 kHz 2.6 kHz 1.3 kHz 0.65 kHz

Detectable smallest pulse bandwidth 0.769 ms 1.53 ms 3.06 ms 6.12 ms

Chart 17. The relationship between detectable smallest pulse bandwidth and TPS2.

Rev. 4.4 27/46

 FS970X

Reading and operation of ADC

As described in 8.2, the circuitry of FS970X ADC might drift and causes an offset voltage because of
manufacturing process. This might cause variance to the reading of ADC. To eliminate the offset variance, it’s
necessary to change the setup CYS<1:0> of register SETADC. There are three different working modes.
These modes influence the reading and operation of high-resolution and low-resolution. They are described as
below:

11..1 High-resolution, low-speed output

When CYS<1:0>=00, the input of ADC becomes short; then, we can read the negative value of offset voltage of

'
ADC from SUM1.

y
ef pe NE
When CYS<1:0>=11, the equivalent digit value of the voltage can be read from SUM1, as shown in Formula 5.

nl
When CYS<1:0>=01, then, the reading value of SUM1 is equal to the ideal reading of linear ADC of the voltage.
Its transfer function is shown as Formula 3. It can be used for all the measurement for high resolution.

en es
O
r R ro TU
When CYS<1:0>01, the output frequency of SUM1is the first zero-point frequency f Z 1 of COMB1, as shown
in Formula 9. When CYS<1:0> =01, the output frequency equals f Z 1 2 .
er rti
11..2 Low-resolution, high-speed output

ce
When CYS<1:0>=00, the input of ADC becomes short; then, we can read the negative value of offset voltage of
Fo P R

ADC from SUM2. It can be used Dos self-calibration.

When CYS<1:0>=11, the equivalent digit value of the voltage can be read from SUM2, as shown in Formula 5.
It can be used for peak-hold sampling measurement.
FO

When CYS<1:0>=01, the transfer function of low resolution output SUM2 should become (a revision from
Formula 5)

Formula 9 ...........................
 v   v 
SUM 2   G '  x  Dos   SUM 2  0    Dos  G '  x   SUM 2  0 
 V ref   V ref 
   

The value of D os can be read from SUM2 when power-on or turning the rotary, set CYS<1:0>=00. Therefore,
the flow-Chart of operation and display of fast ADC output is shown as Graph 13. Whereas, D x is the ideal
ADC values of non-offset voltage, calculated from SUM2. It can be used for Bargraph display of all kinds of high
resolution measurement.

Rev. 4.4 28/46

 FS970X

Interrupt

read SUM2<15:0>

SUM2<0>
SUM2<0>=0 SUM2<0>=1
=0 or 1

'
Dx= Dx=

y
ef pe NE
SUM2<15:0>-D os
Dos-SUM2<15:0>

nl
Cal and Display

en es
O
Wait for next
r R ro TU
interrupt

Graph 13. The flow-Chart of operation and display of fast ADC output.
er rti
ce
The output frequency of fast ADC is the same as the first zero-point frequency of COMB2. When sampling
frequency f S =166 kHz, if set TPS2<1:0>=11, then, the output frequency will be about 650 Hz.
Fo P R

11..3 Scale-type resistance measurement and Analog Bargraph

FO

FS970X is equipped with fast ADC output SUM2. In the application of DMM, it can be used for Analog
Bargraph display.

However, as shown in Formula 6, when performing the scale-type resistor measurement, the reference voltage
of feeding ADC is no longer a constant value. Thus, the equivalent digital value D os of the offset voltage is no
longer a constant value, either. It varies with resistor. The method of deduction of D os when performing the
calculation, as described in Section 8.5.2, is no longer adequate.

As shown in Graph 14, the reference voltage below 5 M varies between the range of 0.8 V~1.2 V. According
to Formula 4, the Dos will vary dramatically, and cause problems to the Analog Bargraph.

Generally speaking, the Analog Bargraph display is approx. 50 digits. The accuracy requirement is not strict;
thus, the problem can be solved by using section approximation. That is to say, when measuring the resistor,
the operation of the Analog Bargraph can be processed under the following three conditions:

Rev. 4.4 29/46

 FS970X

OSR OSR OSR OSR OSR OSR

2.4 V 1.2 V 1.2V 1.2 V 1.2 V 1.2 V

VRH VRH VRH VRH VRH VRH

RREF VRH - VRL = RREF VRH - VRL = RREF VRH - VRL = RREF VRH - VRL = RREF VRH - VRL = RREF VRH - VRL =
0.8 V ~ 0.686 V 1.0 V ~ 0.706 V 1.176 V ~ 0.789 V 1.198 V ~ 0.799 V 1.20 V ~ 0.80 V 1.20 V ~ 0.20 V
1 k 10 k 100 k 1 M 10 M 10 M

VRL VRL VRL VRL VRL VRL

RFUSE+PTC

RFUSE+PTC

RFUSE+PTC

RFUSE+PTC

RFUSE+PTC

RFUSE+PTC
2 k 2 k 2 k 2 k 2 k 2 k

INH INH INH INH INH INH

'
INH - INL = INH - INL = INH - INL = INH - INL = INH - INL = INH - INL =

y
RX 0 V ~ 0.343 V RX 0 V ~ 0.353 V RX 0 V ~ 0.395 V RX 0 V ~ 0.399 V RX 0 V ~ 0.40 V RX 0 V ~ 1.00 V

ef pe NE 0  ~ 500 

INL
0  ~ 5 k

INL
0  ~ 50 k

INL
0  ~ 500 k

INL
0  ~ 5 M

INL
0  ~ 50 M

INL

nl
AGND AGND AGND AGND AGND AGND

en es
(a) (b) (c) (d) (e) (f)

O
r R ro TU
Graph 14. The converting voltage range of scale-type resistor measurement.

The 1 condition is low resistance under 5 k. The Dos can be obtained by setting the reference voltage
st

equivalent to 0.8 V. The 0.8 V can be generated by the fixed voltage generator in the chip. (as shown in Chart
7), through ACBUF output, connecting to AX3 and then into VRH. Or obtained through ACBUF, connecting
er rti
to AX5, through Ωpower supply, and returning to VRH.

ce
The 2 condition is middle resistance between 50 k ~ 5 M. The Dos can be obtained by setting the
nd
Fo P R

reference voltage equivalent to 1.0 V. Under this condition, the Dos value, just like the other measuring
Dos value, can be processed by the same parameter.
FO

The 3 condition is high resistance – 50 M. Because the various range of the reference voltage is too
rd

great, the value of Dos can be easily use an approximate number. Therefore it can be obtained by reducing
the Bargrapg display speed and using the reading of the high resolution output, or reduce the digit of the
Bargraph to 10 or 20 digit.

By using the method illustrated in this section to set the reference voltage between 0.8 V and 1.0V when cut in
the resistor file and calibrate the Dos of under 5 k and 50 k ~ 5 M respectively. According to different
measurement range to select different Dos . Then using the calculation shown in 8.5.2, we can complete the
calculation of 50 digit of fast Bargraph display.

The Conversion of Digital Output & Equivalent Voltage

Take the high resolution digital output of FS970X, the output, SUM1<23:0>, is the compensation value of
2/24bits. Whereas, SUM1<23> is the symbol bit – “0” = positive, and “1” = negative. The floating point locates
between SUM1<22> and SUM1<21>.

Assuming SUM1<23:0>=0010_1000_0000_0000_0000_0000, the equivalent floating point calculation is:

SUM1  00.10 _ 1000 _ 0000 _ 0000 _ 0000 _ 0000

Formula 10  1  2 1  0  2 2  1  2 3  0  2 4  0  2 5  ......  0  2 22
 0.5  0.125  0.625

Assuming SUM1<23:0>=1101_1111_1111_1111_1111_1111, the equivalent floating point calculation is:

Rev. 4.4 30/46

 FS970X

SUM 1  11.01 _ 1111 _ 1111 _ 1111 _ 1111 _ 1111

 (00.10 _ 0000 _ 0000 _ 0000 _ 0000 _ 0001)
Formula 11
 (1  2 1  0  2  2  0  2 3  0  2  4  ......  1  2  22
 0.5000002384

As shown in Formula 3, when the gain G ' equals the ideal value 1, the reference voltage Vref equals
1.00000V. From the reading of ADC 0010_1000_0000_0000_0000_000, the voltage can be calculated as:

Vref 1.00000 V
vx  '
 Dx   0.625  0.62500 V .

'
G 1

y
ef pe NE
When the reading of ADC is 1101_1111_1111_1111_1111_1111, the voltage can be calculated as:

nl
Vref 1.00000 V
vx  '
 Dx   0.5000002384  0.50000 V .
G 1

en es
However, in reality, the G value affected by the drifting of the process, will not equal to 1.It will vary approx.
'

O
1% . At the same time, the reference voltage Vref , affected by the reference power and dividing resistance,
r R ro TU
will not equal to 1.00000V. Therefore, the gain variances from the components have to be calibrated.
er rti
The different output code of different models

ce
FS970X chip series has three models with different resolution, 5,000 digits, 20,000 digits, and 50,000 digits.
The digit output codes are as follows:
Fo P R

In the 5,000 digits or 50,000 digits models, when the absolute value of SUM1, and the SUM1<21:18> is greater
than 1010, then, the SUM1<21:18>will saturate to 1111. And the equivalent voltage of SUM1<21:18>=1010 will
FO

be approx. 0.625V.

In the 20,000 model, when the absolute value of SUM1, and the SUM1<21:18> is greater than 0101, then, the
SUM1<21:18>will saturate to 1111. And the equivalent voltage of SUM1<21:18>=1010 will be approx. 0.3125V.

In the 5,000 digit model, the digital output of SUM1<5:1> is a constant 00000.

Other Control setting

ENAD(ADG<7>) is the enabling signal of ADC. It turns on the ADC when value =1, and turns
off the ADC when value=0. It saves the power consumption setting the value to 0.

12. Digital Signal Process

Except digital filter, the digital signal process of FS970X includes frequency counter and peak-hold sampling
process.

Frequency counter
The frequency counter of FS970X is composed of time-based counter and signal counter. The physical value
of the target can be calculated from these two counters. The physical values of the target have signal frequency
and duty cycle. It is determined by the DTON. It performs the frequency counter when setting it as “Lo” and
performs duty cycle measurement when setting to as “Hi”.

When performing the frequency counter measurement, it needs the reference time pulse signal FTB, as shown

Rev. 4.4 31/46

 FS970X

in Graph 4. The frequency of the target can be obtained from the following formula:

K SG
Formula 12 FINSIG   FTB
K TB

Whereas KSG and KTB are the values of signal counter and time-based counter respectively. FTB is the
frequency of reference signal, as shown in Chart 3. FINSIG is the frequency of the target signal.

When performing the duty cycle measurement, the relationship between the duty cycle DT INSIG and KSG 和 KTB
is as follow:

'
K DT
Formula 13 DTINSIG  100%

y
ef pe NE K TB

nl
You may have noticed that the value is independent from the reference time pulse frequency.

en es
O
The reading process of frequency counter
r R ro TU
Both controls of frequency measurement and duty cycle measurement are the motion of the frequency counter
through FQRST_. When first setting FQRST_ to 0, and then resetting it to 1, it will trigger the action of
er rti
frequency counter. It will complete the counting in approx. 0.2 seconds. It will also advice the microprocessor

ce
to read. After the reading of KTB and KSG, the value can be calculated from Formula 12 or Formula 13.
Then, repeat the reset to get the new value of the next measurement, and so forth and so on.
Fo P R

However, whether processed by the interrupt or polling after the reset of the counter, the interrupt status bit is
set to 1, meaning the counting is completed. However, when using the frequency counter of FS970X chip,
and when entering the counter measurement, after the first reset, it should read the values of KTB and KSG. It
FO

doesn’t need to process the values. Thereafter, it starts the reading process of the interrupt status bits.

Peak-hold sampling process

As shown in the Chart 17, the reading of the output value of fast ADC meets the requirement of positive
negative peak-hold of pulse bandwidth measuring in a matter of naro-second. The peak-hold sampling logic of
FS970X accepts the control of PKHRST. It uses the SUM 2 as an input. It composed of the positive-negative
peak-hold comparison device and the positive-negative peak-hold register.

When PKHRST_ equals 0, the positive peak-hold register (POSPK) and the negative peak-hold register
(NEGPK) will be reset to the most negative and positive value respectively.

When PKHRST is set to Hi, the digit comparison device will compare the value of SUM2 with the value of the
positive peak-hold register (POSPK) and the negative peak-hold register (NEGPK). When the value of SUM2 is
greater than the value of the positive peak-hold register, the value of the positive peak-hold register will be
updated, otherwise it will remain the same. When the value of SUM2 is smaller than the value of the negative
peak-hold register, the value of the negative peak-hold register will be updated, otherwise it will remain the
same.

Therefore, after resetting the peak-hold sampling logic, set PKHRST_ equal 1, and the interrupt status digit of
the peak-hold sampling to 1; then, read the values of POSPK and NEGPK registers. One can obtain the values
of the measuring of positive peak-hold and negative peak-hold values.

Because the value of the peak-hold sampling device is derived from the value of SUM2, one should use
Formula 5 to calculate the equivalent voltage value of the operator.

Rev. 4.4 32/46

 FS970X

13. Microprocessor interface

970x can directly connect to any microprocessor by CS_. WR_. RD_. ALE. AD3. AD2. AD1. AD0, and IRQO
pins. It can also control read / write functions of registers, and handle interrupt.

Control register
The control registers are all 8-bit register, input-output port and for microprocessor to read and write. And the
control register will be reset to the initial value of 0 when connecting to the RST_ pin of the chip.

'
The primary function of the control register is to provide the microprocessor to write to the control setting of the

y
ef pe NE
chip. Hence, it controls all the action of the chip. It can also read the value and for the use of detection.

nl
MSB LSB
Block Address Name 7 6 5 4 3 2 1 0
R 00 RGD<7:0> RANGE<3:0> MODE<3:0>
o 01 SIN<7:0> SINH<3:0> BPFTR SINL<2:0>

en es
u
02 SRF<7:0> SOSR<1:0> SRFH<1:0> FTR SRFL<2:0>
t

O
e 03 SCP<7:0> SCMPH<3:0> SCMPL<1:0> CMPEN2
0 CMPEN1
r R ro TU
r 04 AFT<7:0> EXTD RCTEN ACDIV ACEN ENSCHMT CAPM CPN<1> CPN<0>
05 ADG<7:0> ENAD CPVR
0 ADG<5:0>
ADC
06 SETADC ENVDS ENVCS CYS<1:0> TPS2<1:0> TPS1<1:0>
07 MISC1<7:0> ENBP FSDIV TBDIV ENOSCO_ ENXTL_ DTON FQRST_ PKHRST_
MISC
er rti
08 MISC2<7:0> ENCP_ CMP2 CMP1 LBO CNTBP BPACBF ENGNDR_ ENLBS

ce
INT 09 INTRG<7:0> INSTA<3:0> INTEN<3:0>
Fo P R

Chart 18 . The corresponding address table of all control and interrupt register of the chip.

There are, in total, nine (9) 00~08 addresses of control line or register; as shown in Chart 18. The functions of
each address are briefly illustrated in the Chart 19.
FO

Register Function Reference

RGD<7>0> Controls the on/off status of the measurement mode and decay As described in
network of function network Section 7.1

SIN<7:0> Controls the path and the pre-filter of signal input amplifier of ADC Chart 9 and Chart 10

SRF<5:0> Controls the path and the pre-filter of reference voltage of ADC Chart 11 and Chart
12

SRF<7:6> Output option of Ω power supply Chart 8

SCP<7:0> Controls the path & enable control of the multiplexers at the Chart 13 and Chart
front-end of comparator 14

AFT<7:0> The enable control of on/off status & operation amplifier in some Graph 5
function networks

AFT<3> When ENSCHMT = 1, the Schmidt trigger function of enable Section 7.5
comparator

ADG<5:0> The gain setting of ADC input Section 8.3

Rev. 4.4 33/46

 FS970X

ADG<7:6> Performance setting of ADC Section 8.7

SETADC<7:6> ENVDS & ENVCS, on/off power control setting Section 5.3

SETADC<5:4> CYS<1:0> elimination mode setting of offset voltage of ADC Section 8.5

SETADC<3:0> TPS1<1:0> and TPS2<1:0> the number of digital filter Section 8.4

MISC1<7> CNTBP and CMP1of ENBP and MISC2<3> determine the action Chart 4
of buzzer

'

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ef pe NE
MISC1<6:3> Setting of clock generator controls the operating mode of capacity Chart 3, Chart 7
measurement and Chart 8

nl
MISC1<2:1> DTON and FQRST_ are the counter mode of frequency counter Section 9.1
and reset control

en es
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r R ro TU
MISC1<0> PKHRST_ is the reset signal of peak-hold sampling circuitry Section 9.2

MISC2<6:4> Output of compactor and low voltage detector Section 7.5 and 5.1
er rti
ce
MISC2<2> When equal 1, the signal of CMPH can directly input from ACA, Section 7.5.1
without going through an AC buffer
Fo P R

MISC2<1:0> ENGNDR_ and ENLBS are the enable control of basic job offset 5.1 and 5.2
voltage and low voltage detector.
FO

Chart 19. The brief illustration of the function of each register in FS970X.

The read/write sequence of each control register is shown as Graph 15. Because of the data length is 8 bit, it
requires consecutive two times for each read or write, first MSB, and then LSB（4 bits each）”0” when the next
ALE occurred. Thus, it will start with MSB again when starting the next read/write sequence.

AD<3:0> Address, 00~08 DATA<7:4> DATA<3:0> AD<3:0> Address, 00~08 DATA<7:4> DATA<3:0> Next Address

ALE ALE

RD_ WR_

CS_ CS_

CYCNTR 0 1 2 CYCNTR 0 1 2

READ CONTROL REGISTER CYCLE WRITE CONTROL REGISTER CYCLE

Graph 15. The read/write sequence of the control register.

Rev. 4.4 34/46

 FS970X

The interrupt process

The measurements can be read by the microprocessor interface are high-resolution output of ADC, the low
resolution output of ADC, positive-negative peak-hold value, the output of frequency counter…etc. In any of
the registers, each new value means new “event”. The chip, thru its IRQO pin, will send an interrupt signal to
the microprocessor and request to process.

When microprocessor received an interrupt signal of negative-end trigger; means that some measuring
registers in 970x chip has detected a new value. The microprocessor will then read the interrupt status register
（INTSTA）, checking where the interrupt comes from. Chart 20 shows the corresponding event for each bit in
the INSTA. The INTEN in Chart 20 controls whether a measuring event interrupt will occur.

'

y
ef pe NE INSTA INSTA<3> INSTA<2> INSTA<1> INSTA<0>

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Event Frequency counter +/- peak-hold value Low-resolution High-resolution
output ADC ADC

en es
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INTEN INTEN<3> INTEN<2> INTEN<1> INTEN<0>
r R ro TU
Function Corresponding Corresponding Corresponding Corresponding
IRQO enable IRQO enable IRQO enable IRQO enable
er rti
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Chart 20. Interrupt status registers.
Fo P R

When microprocessor reads the register again, the interrupt bit will be reset to 0, and waiting for the new
measurement to generate the interrupt again.
FO

The interrupt status register INSTA<3:0> is a read-only register. The interrupt enable register INTEN<3:0> is a
read/write register. The read/write sequences of both registers are the same as control register, as shown in
Graph 15.

The flow-Chart of interrupt process are as follows:

1) When there’s a new value shown in the enable register, then set IRQO equal to 0, and keep it to
0.
2) When microprocessor receive this negative-end trigger, then read the interrupt status register.
3) After reading the status register, IRQO will be pulled back to1.
4) Check if the IRQO was pulled back to 1. If not, it means that it didn’t catch a negative end; then,
it should read the interrupt status one more time.
When reading the instruction period of the interrupt register; the negative-end of the new interrupt might be lost.
Therefore, by adding Step 4) will improve this problem.

In addition, whether the value of the interrupt status register has been updated in independent from interrupt
enable register. That is to say, the interrupt enable register only affects IRQO output.

Rev. 4.4 35/46

 FS970X

Measurement Registers

Address Register Function Length of Times of

register reading

0A KTB<23:0> Output of time-based counter 24 6

0B KSG<23:0> Output of signal counter 24 6

0C POSPK<15:0> The up-most positive peak-hold register 16 4

'

y
ef pe NE 0D

0E
NEGPK<15:0>

SUM2<15:0>
The up-most negative peak-hold register

Output of low-resolution ADC

16

16
4

nl
0F SUM1<23:0> Output of high-resolution ADC 24 6

en es
O
Chart 21. all measurement value registers in the chip.
r R ro TU
All measurement registers and their corresponding address of FS970X are listed in Chart 21. There are six
addresses in total. The length of each register varies. They are all output ports, and can only be read by
microprocessor.
er rti
ce
The reading clocks of the measurement register are shown in
Fo P R

Graph . When IRQC<x> is on the negative-end, it will clear the corresponding INSTA<x>. The number of
readings of each new value has to be correct. Otherwise, read/write cycle counter CYCNTR will be cleared to
0 when ALE is “Hi”. The number of readings of each address varies with the length of each register, as shown
FO

in the last column of Chart 21.

When reading SUM1or SUM2, the first reading period (when CYCNTR=1), the low pulse width of RD_ must be
greater than the sampling period of ADC. The other reading periods need only to be greater than 2 us. For
example, when the sampling frequency of the ADC is 83.3 kHz, then, the first reading period of SUM1 and
SUM2 must be greater than 12 us.

Regarding the frequency counter, what worth mentioning is when reading the value of the time-based counter,
it will not clear the interrupt bit INSTA<3>. Only when reading the signal counter, its corresponding interrupt
bit INSTA<3> can be cleared.

INSTA<2> will be cleared whether reading registers of the up-most positive peak-hold value or up-most
negative peak-hold value.
AD<3:0> Address, 0A~0F DATA<N:N-3> DATA<N-4:N-7> DATA<3:0>

ALE

RD_

CS_

CYCNTR 0 1 2 N/4

IRQC<x>

READ MEASURED REGISTER CYCLE

Graph 16. Reading sequence diagram of measuring registers.

Rev. 4.4 36/46

 FS970X

14. Basic Measurement Application

DCmV
14..1 500 mV
BPFTR
OFF CHIP ON CHIP

DCV
ADIMUX FTR FTR
DCmV 909K 28 23 1M 24
SMV FTA FTB to INH

27nF

'
Vx 220pF EXCEPT CAP

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OFF CHIP
FTC
ADIMUX
10K 25 17
SGND to INL

nl
COMMON AGND

Graph 17. Function network diagram of 500 mV.

en es
Address 00 01 02 03 04 05 06 07 08

O
r R ro TU
Register RDG SIN SRF SCP AFT ADG SETADC MISC1 MISC2
Value 00h 00h 08h 00h 00h 93h 9Fh 00h 00h
Chart 22. 500 mV register setup.
er rti
Signal flows in SMV, through ADIMUX and pre-filter, into ADC.

ce
Fo P R

14..2 50 mV
10 k 90 k
OFF CHIP
FO

AGND
ACA

ACB

38 37
ON CHIP

ACDIV

ACBUF

ACEN

CMPHMUX ADIMUX
BPFTR

DCV
DCmV 90K 28 FTR 23 1M 24 FTR
SMV FTA FTB to INH

27nF
Vx
OFF CHIP
FTC
ADIMUX
10K 25 17
SGND to INL

COMMON AGND

Graph 18. Function network diagram of 50 mV.

Address 00 01 02 03 04 05 06 07 08
Register RDG SIN SRF SCP AFT ADG SETADC MISC1 MISC2
Value 00h 80h 08h 00h 30h 93h 9Fh 00h 80h
Chart 23. 50 mV register setup.

Signal flows in from AMV, through a 10-times amplified gain network by ACBUF, and goes through a pre-filter
before flowing into ADC.

Rev. 4.4 37/46

 FS970X

DC voltage
10 k 90 k

AGND

ACA

ACB
38 37

ACDIV
TENM<0>
DCV
DCV 18
RFUSE+PTC TENM ACBUF
10M
ACEN
ADIMUX
BPFTR

'
CMPHMUX

y
ef pe NE
Vx 1M or 100K or 10K or 1K
XOHM
XOHM

ADIMUX FTR 23
FTA
1M
FTB
24 FTR
to INH

nl
19~22
XOHM
27nF

OFF CHIP
ADIMUX FTC
10K 25
17

en es
SGND to INL

O
r R ro TU
COMMON
OFF CHIP ON CHIP
AGND

Graph 19. Function network diagram of DC voltage.

er rti
ce Address 00 01 02 03 04 05 06 07 08
Fo P R

Register RDG SIN SRF SCP AFT ADG SETADC MISC1 MISC2

0.5 V 10 80 08h 00h 30h 93h 9Fh 00h 80h

FO

5V~1000V x0h 10h 08h 00h 00h 93h 9Fh 00h 00h

Chart 24. DC voltage register setup.

Whereas, the value of RGD<7:4> is determined by function, as shown in Chart .

Address Register 0.5V~5V 50V 500V 1000V

00 RGD<7:0> 10h 20h 40h 80h

Chart 25. Voltage range setup

The voltage signal will decay to be lower than 0.5V by a suitable multiple of decay network. It will go through a
pre-filter, and then into ADC. Only the signal of 0.5V, decayed 10-times, will amplify 10-times before flow into
ADC.

Rev. 4.4 38/46

 FS970X

AC Voltage (ACV)
10K 90K 10uF
AGND
100
K

2k
AGND 47 nF

ACHO

ACLO
RCTN

RCTO
RCTP

ACH
ACB

ACL
ACA
38 37 36 35 41
40 39 42 43
CCOMPENSATION 17 CPN<1> ACDIV
ACL ACH
CPN AGND ACDIVB

CPN<0> RCTOP

'
TENM<0>
RCTEN

y
DCV

ef pe NE
ACBUF
CDECOUPLE 18
AGND
RFUSE+PTC TENM ACEN CMP1 FREQ
10M

nl
BPFTR CMPEN1
ACH
CMPMUX
XOHM

Vx 1M or 100K or 10K or 1K FTR 23 1M 24 FTR

en es
ADIMUX
XOHM FTA FTB INH

O
19~22
XOHM
r R ro TU
27nF

OFF CHIP
ACL FTC
ADIMUX
10K 25 17
SGND SGND INL
er rti
COMMON
OFF CHIP ON CHIP

ce
AGND

Graph 20. Function network diagram of AC voltage.

Fo P R

Address 00 01 02 03 04 05 06 07 08

Register RDG SIN SRF SCP AFT ADG SETADC MISC1 MISC2
FO

0.5V 10h 5Bh 00h 10h F0h 93 9F 00 00

5V~100V x0h 5Bh 00h 10h D0h 93h 9Fh 00h 00h

Chart 26. AC voltage register setup.

Whereas, the value of RGD<7:4> is determined by the function, as show in Chart .

The voltage signal of 5V~1000V will decay to be lower than 0.5V by a suitable multiple of decay network. It
will go through a AC buffer with gain value of 1, and then into a AC/DC converter or true mean square converter.
It then goes through a pre-filter, and into ADC. Under 0.5V, setting ACDIV=1 will allow the 10-times decay
signal to be 10-times amplified by AC buffer, reversing it back within the dynamic range of 0.5V before feeding it
into AC/DC converter or true mean square converter.

DC Current (DCA)

Rev. 4.4 39/46

 FS970X

10K 30K
AGND

60K

ACB
ACA
38 37

ACDIV
ACDIVB

ACBUF

ACEN

'

y
ef pe NE
mA+uA

CMPMUX
BPFTR

nl
mA uA
10A ADIMUX
99 29 FTR 23 1M 24 FTR
SA FTA FTB INH

en es
0.99

O
27nF
0.01
r R ro TU
COMMON OFF CHIP
FTC
ADIMUX
10K 26 17
SGND INL

AGND
er rti
OFF CHIP ON CHIP
Graph 21.

ce Function network diagram of DC current.

Fo P R

Address 00 01 02 03 04 05 06 07 08

Register RDG SIN SRF SCP AFT ADG SETADC MISC1 MISC2
FO

5000uA, 500mA, 10A 00h 80h 08h 20h 10h 93h 9Fh 00h 80h

500uA, 5mA, 5A 00h 80h 08h 20h 30h 93h 9Fh 00h 80h

Chart 27. DC current register setup.

AS shown in Graph , and assuming the transferring resistor to be approx. 100, the transferring voltage will be
0.5V under 5.0000 mA. It will then flow into ADC through the ACBUF buffer of 1 (ACDIV=AFT<5>=0). Under
50.000 mA, when using the transferring resistor of 100, the transferring voltage of 5V will be too high. If
using 1, the transferring voltage will be 50mV, and the gain of ACBUF will be 10 (ACDIV=AFT<5>=1). Amplify
the signal 10-times before feeding it into ADC.

Rev. 4.4 40/46

 FS970X

AC Current (ACA)
10K 90K 10uF
AGND
100
K

2k
AGND 47 nF

ACHO

ACLO
RCTN

RCTO
RCTP

ACH
ACB

ACL
ACA
38 37 36 35 41
40 39 42 43

ACDIV ACL ACH

ACDIVB

RCTOP

'
RCTEN

y
ACBUF

ef pe NE
mA+uA
ACEN
AGND
CMP1 FREQ

nl
BPFTR CMPEN1
ACH
CMPMUX
mA uA
10A
99 29 FTR 23 1M 24 FTR
ADIMUX

en es
SA FTA FTB INH
0.99

O
27nF
r R ro TU
0.01
COMMON OFF CHIP
ACL FTC
ADIMUX
10K 25 17
SGND SGND INL
er rti
AGND

ce
OFF CHIP ON CHIP

Graph 22. Function network diagram of AC current.

Fo P R

Address 00 01 02 03 04 05 06 07 08

Register RDG SIN SRF SCP AFT ADG SETADC MISC1 MISC2
FO

5000uA, 500mA, 10A 00h 5Bh 08h 20h D0h 93h 9Fh 00h 00h

500uA, 5mA, 5A 00h 5Bh 08h 20h F0h 93h 9Fh 00h 00h

Chart 28. AC current register setup.

As shown in Graph, the measuring path of AC current, up to the output of AC buffer, is the same as DC current.
After going through AC buffer, the signal will flow through AC/DC converter or true mean square converter to
convert AC signal into DC signal before flow into ADC.

Rev. 4.4 41/46

 FS970X

Resistor ()
COMMON
10K 28
SGND INL

DCmV+OHM+CAP AGND
+DT+HFE+PKH 909K 25
SMV INH

1M 30
SDB VRL
EXCEPT CAP

Rx VRH
XOHM<0> OSREN

1M or 100K or 10K or 1K OSR OSRC

220pF XOHM<1>

'
XOHM OSRC
19~22

y
ef pe NE
XOHM<2>
OHM+CAP
+HFE+CALR
AGND TENM<0> OSR

nl
18
FUSE PTC TENM
DCV+OHM 10M
VOLT+OHM+ +CAP+HFE+PKH
DT+CAP

en es
16 CPN<0>

O
CPN
r R ro TU
CPN<1>
27nF
AGND

OFF CHIP ON CHIP

Graph 23. Function network diagram of resistor.

er rti
ce
Address 00 01 02 03 04 05 06 07 08
Fo P R

Register RDG SIN SRF SCP AFT ADG SETADC MISC1 MISC2

Value 89h 00h Dah 00h 00h 93h 1Fh 00h 00h
FO

Chart 29. Resistor register setup.

The setup of RGD<7:4>, SRF<7:0>, ADG<7:0>, and MISC1<7:0> varies with different functions. See below for
details.

Address Register 500 5K 50K 500K 5M 40M

00 RGD<7:0> 89h 49h 29h 19h 09h 09h

02 SRF<7:0> Dah 4Ah 4Ah 4Ah 4Ah 4Ah

05 ADG<7:0> 93h 93h 93h 93h 93h 98H

07 MISC1<7:0> 00h 00h 00h 00h 40h 40h

Chart 30. Resistor range setup.

Rev. 4.4 42/46

 FS970X

Capacitor
COMMON

DCmV+OHM+CAP AGND
CMPH CMPEN1
+DT+HFE+PKH 909K 28
SMV
CMP1 CAPTG
Cx CMPL

OSREN
XOHM<1>
10M or 1M or 100K or 10K or 1K 18~22 OSRC

'
FUSE PTC XOHM OSRC
DCV+OHM

y
OSR

ef pe NE
+CAP+HFE+PKH XOHM<2>
VOLT+OHM+
DT+CAP

OSR

nl
OFF CHIP ON CHIP

en es
Graph 24. Function network diagram of capacitor.

O
Address 00 01 02 03 04 05 06 07 08
r R ro TU
Register RDG SIN SRF SCP AFT ADG SETADC MISC1 MISC2
Value 1Bh 00h 00h 01h 00h 00h 00h 00h 00h
er rti
Chart 31. Capacitor register setup.

ce Address
00
Register
RGD<7:0>
500nF
1Bh
5uF
2Bh
50uF
4Bh
500uF
8Bh
Fo P R

04 AFT<7:0> 00h 00h 00h 04h

07 MISC1<7:0> 00h 00h 00h 20h
Chart 32. Capacitor range setup.
FO

 Measuring capacitor value of FS9704B is to charge and discharge the resistor reference added by
XOHM Pin to make an oscillation, and then calculate its oscillated cycle to get the capacitor value.
VDD

3/4VDD

1/4VDD

Tdo

Capacitor Measurement

 Title counter. When

To calculate the cycle, we send the square wave that out from CAPTG to the frequency
operating the frequency measurement, the necessary timer reference signal is FTB. For the measuring
frequency, it can be gained through the following formula. In this formula, Ksg is the signal counter and
Ktb is the value of the time-base counter. Size Num ber
Fin = (Ksg / Ktb) * FTB
A4
 The revise of the calculated Fin is the cycle.
Date: 4-Dec-2001
1 / Fin = { 1 / [ (Ksg / Ktb) * FTB ] }
File: C:\Program Files\Design
3

Rev. 4.4 43/46

 FS970X

Diode
VB+

1.5 k
OFF CHIP ON CHIP

DT

PTC
DCmV+OHM+CAP
DT+HFE+PKH

DT

909 k

'
28

y
SMV INH

ef pe NE DIODE
20
HUNK
SDT

nl
100 k

10k  25
SGND INL

en es
COMMON AGND

O
Graph 25. Function network of diode measurement.
r R ro TU
Address 00 01 02 03 04 05 06 07 08
er rti
ce
Register RDG SIN SRF SCP AFT ADG SETADC MISC1 MISC2
Fo P R

Setup value 01h 00h 08h 00h 00h 93h 1Fh 00h 00h

Chart 33. Diode register setup.

FO

Rev. 4.4 44/46

 FS970X

15. Package Outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x1.4 mm

'
c

y
ef pe NE y

nl
A

48 33

en es
49 32 ZE

O
r R ro TU
e
E HE A2
A
er rti
(A3)
A1

ce
w M
£K
bp
Lp
Fo P R

pin 1 index L
64 17

1 16 detail x
FO

ZD v M A
e w M
bp
D B

H D
v M B

0 2.5 5 mm

scale

DIMENSIONS (mm are the origlinal dimensions)

A (1) (1) (1) (1)
UNIT max. A1 A2 A3 bp c D E e HD HE L Lp v w y ZD ZE £K

0.15 1.45 0.27 0.20 10.1 10.1 12.15 12.15 0.75 1.45 1.45 7 ¢X
mm 1.60 0.25 0.5 1.0 0.2 0.12 0.075
0.05 1.35 0.17 0.09 9.9 9.9 11.85 11.85 0.45 1.05 1.05 0 ¢X

Note: 1.Plastic or metal protrusions of 0.25 mm maximum per side are not included.

Rev. 4.4 45/46

 FS970X

16. Attachment (1) OP-AMP Specifications

(VDD = 6V, VSS = 0V, TA=+25℃, unless otherwise indicated)
Instrumentation Amplifier @ Gain = 30, Vref=0.5V, TA=25℃
PARAMETER TEST CONTITIONS MIN. TYP. MAX. UNITS
Input Offset Voltage without AZ 20
Input Offset Voltage with AZ 0 3
Input Offset Drift without AZ -20℃<TA<+50℃ 200 nV/℃

'
Input Offset Drift with AZ -20℃<TA<+50℃ 20 nV/℃

y
ef pe NE
Input Referred Noise 0.3 0.6

nl
Input Bias Current [2] 100 300 pA
Current Consumption 180 220

en es
O
[1] These parameters are guaranteed by design and are tested only by sampling while mass production.
r R ro TU
[2] While a voltage source with large output impedance is measured by an instrument-ation amplifier having
input bias current, an additional input offset voltage will introduced. However, this offset voltage could be
cancelled by mirrored offset cancellation technique.
er rti
ce
17. Revision History
Fo P R

Ver. Date Page Description

3.9 2004/01/28 12 Revise typical application circuit
4.0 2004/04/23 5 1. Revise datasheet format
2. Add ordering information
FO

4.1 2006/12/21 All 1. Revise datasheet format

17 2. Add revision history
4.2 2007/02/28 6 Add Pb free ordering information
4.3 2010/02/23 6 Revise Green ordering information
4.4 2014/05/22 2 Revised company address

Rev. 4.4 46/46