Computer Architecture
Lecture IV
By
Dr. M. Moustafa Hassan
Elec. Power Engineering
Cairo University, Giza, Egypt
Control Unit Operation
▪No HW problems on this part.
▪It is important to understand this
material on :
➢ the architecture of computer control
units, and
➢ microprogrammed control units.
Basic Elements of Processor
▪ ALU
▪ Registers
▪ Internal data paths
▪ External data paths
▪ Control Unit
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A Simple Computer & its
Control Unit
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Instruction Micro-Operations
▪ A computer executes a program of
instructions (or instruction cycles)
▪ Each instruction cycle has a number to
steps or phases:
- Fetch, - Indirect (if specified),
- Execute, - Interrupt (if requested)
▪ These can be seen as micro-operations
oEach step does a modest amount of work
oAtomic operation of CPU
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Constituent Elements of its
Program Execution
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Types of Micro-operation
▪ Transfer data between registers
▪ Transfer data from register to external
▪ Transfer data from external to register
▪ Perform arithmetic or logical ops
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Control Signals
▪ Clock
o One micro-instruction (or set of parallel micro-
instructions) per clock cycle
▪ Instruction register
o Op-code for current instruction
o Determines which micro-instructions are performed
▪ Flags
o State of CPU
o Results of previous operations
▪ From control bus
o Interrupts
o Acknowledgements
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Control Signals - Output
▪ Within CPU
oCause data movement
oActivate specific functions
▪ Via control bus
oTo memory
oTo I/O modules
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Flowchart for Instruction Cycle
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Fetch - 4 “Control” Registers Utilized
▪ Program Counter (PC)
oHolds address of next instruction to be fetched
▪ Memory Address Register (MAR)
oConnected to address bus
oSpecifies address for read or write op
▪ Memory Buffer Register (MBR)
oConnected to data bus
oHolds data to write or last data read
▪ Instruction Register (IR)
oHolds last instruction fetched
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Fetch Cycle
▪ Address of next instruction is in PC
▪ Address (MAR) is placed on address bus
t1: MAR (PC)
▪ Control unit issues READ command
▪ Result (data from memory) appears on data bus
▪ Data from data bus copied into MBR
t2: MBR (memory)
▪ PC incremented by 1 (in parallel with data fetch from
memory)
PC (PC) +1
▪ Data (instruction) moved from MBR to IR
t3: IR (MBR)
▪ MBR is now free for further data fetches
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Fetch Cycle
Fetch Cycle:
t1: MAR (PC)
t2: MBR (memory)
PC (PC) +1
IR (MBR)
t3:10/28/2019
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Fetch Cycle
▪ Let Tx be the time unit of the clock. Then:
t1: MAR (PC)
t2: MBR (memory)
PC (PC) +1
t3: IR (MBR)
▪ Is this equally correct? Why?
t1: MAR (PC)
t2: MBR (memory)
t3: PC (PC) +1
IR (MBR)
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Basic Rules for Clock Cycle Grouping
▪ Proper sequence must be followed
o MAR (PC) must precede MBR (memory)
▪ Conflicts must be avoided
o Must not read & write same register at same time
o MBR (memory) & IR (MBR) must not be in same
cycle
▪ Also: PC (PC) +1 involves addition
o Use ALU ?
o May need additional micro-operations
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Indirect Cycle
• IR is now in same state as if direct
Indirect Cycle: addressing had been used
t1: MAR (IRaddress)
t2: MBR (memory)
t3: IRaddress (MBRaddress) • (What does this say about IR size?)
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Interrupt Cycle
Interrupt Cycle:
t1: MBR (PC) • This is a minimum. May be additional
micro-ops to get addresses
t2: MAR save-address
PC routine-address • N.B. saving context is done by
t3: memory (MBR) interrupt handler routine, not micro-
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Execute Cycle: ADD R1,
memory
Execute Cycle: ADD R1, X • Different for each instruction
t1: MAR (IRaddress)
t2: MBR (memory) •Note no overlap of micro-operations
t3: R1 R1 + (MBR)
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Execute Cycle: ISZ X
Execute Cycle: ISZ X (inc and skip if zero)
t1: MAR (IRaddress) • Notes:
t2: MBR (memory) • “if” is a single micro-
t3: MBR (MBR) + 1 operation
• Micro-operations done
t4: memory (MBR) during t4
if (MBR) == 0 then
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Execute Cycle: BSA X
Execute: BSA X (Branch and Save Address) • BSA X - Branch and save address
Address of instruction following
t1: MAR (IRaddress) BSA
MBR (PC) is saved in X
t2: PC (IRaddress) • Execution continues from X+1
memory (MBR)
t3: 10/28/2019
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3:09 AM
(PC)
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Control Signals
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Micro- Operation and Timing
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Branch Control: Variable Format
One bit determines
microinstruction
format:
• Control signal format
• Branch format
Does require even
more circuitry, and is
slowest.
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