Si7686DP

Vishay Siliconix

N-Channel 30-V (D-S) MOSFET

PRODUCT SUMMARY FEATURES

• Halogen-free available
VDS (V) RDS(on) (Ω) ID (A)a Qg (Typ.)
• TrenchFET® Power MOSFET RoHS
0.0095 at VGS = 10 V 35 • New Low Thermal Resistance PowerPAK® COMPLIANT
30 9.2 nC Package with Low 1.07 mm Profile
0.014 at VGS = 4.5 V 35
• Optimized for High-Side Synchronous Rectifier
PowerPAK SO-8 Operation
• 100 % Rg Tested

6.15 mm S
5.15 mm
APPLICATIONS D
1
2
S • DC/DC Converters
S
3
G
4

D
8 G
D
7
D
6
D
5

Bottom View S
Ordering Information: Si7686DP-T1-E3 (Lead (Pb)-free)
Si7686DP-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol Limit Unit
Drain-Source Voltage VDS 30
V
Gate-Source Voltage VGS ± 20
TC = 25 °C 35a
TC = 70 °C 35a
Continuous Drain Current (TJ = 150 °C) ID
TA = 25 °C 17.9b, c
TA = 70 °C 14.3b, c
A
Pulsed Drain Current IDM 50
TC = 25 °C 31.5
Continuous Source-Drain Diode Current IS
TA = 25 °C 4.2b, c
Single Pulse Avalanche Current IAS 10
L = 0.1 mH
Avalanche Energy EAS 5 mJ
TC = 25 °C 37.9
TC = 70 °C 24.2
Maximum Power Dissipation PD W
TA = 25 °C 5b, c
TA = 70 °C 3.2b, c
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150
°C
Soldering Recommendations (Peak Temperature)d, e 260

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambientb, f t ≤ 10 s RthJA 21 25
°C/W
Maximum Junction-to-Case (Drain) Steady State RthJC 2.8 3.3
Notes:
a. Package Limited.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See Solder Profile (http://www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions is 70 °C/W.

Document Number: 73451 www.vishay.com

S-80440-Rev. C, 03-Mar-08 1
Si7686DP
Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 30 V
VDS Temperature Coefficient ΔVDS/TJ 31.5
ID = 250 µA mV/°C
VGS(th) Temperature Coefficient ΔVGS(th)/TJ -6
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 1 3 V
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA
VDS = 30 V, VGS = 0 V 1
Zero Gate Voltage Drain Current IDSS µA
VDS = 30 V, VGS = 0 V, TJ = 55 °C 10
On-State Drain Currenta ID(on) VDS ≥ 5 V, VGS = 10 V 50 A
VGS = 10 V, ID = 13.8 A 0.0078 0.0095
Drain-Source On-State Resistancea RDS(on) Ω
VGS = 4.5 V, ID = 11.4 A 0.011 0.014
Forward Transconductancea gfs VDS = 15 V, ID = 13.8 A 56 S
b
Dynamic
Input Capacitance Ciss 1220
Output Capacitance Coss VDS = 15 V, VGS = 0 V, f = 1 MHz 230 pF
Reverse Transfer Capacitance Crss 98
VDS = 15 V, VGS = 10 V, ID = 13.8 A 17 26
Total Gate Charge Qg
9.2 14
nC
Gate-Source Charge Qgs VDS = 15 V, VGS = 5 V, ID = 13.8 A 4.1
Gate-Drain Charge Qgd 2.8
Gate Resistance Rg f = 1 MHz 0.8 1.2 Ω
Turn-On Delay Time td(on) 20 30
Rise Time tr VDD = 15 V, RL = 1.5 Ω 20 30
Turn-Off Delay Time td(off) ID ≅ 10 A, VGEN = 4.5 V, Rg = 1 Ω 20 30
Fall Time tf 8 15
ns
Turn-On Delay Time td(on) 13 20
Rise Time tr VDD = 15 V, RL = 1.5 Ω 16 25
Turn-Off Delay Time td(off) ID ≅ 10 A, VGEN = 10 V, Rg = 1 Ω 23 35
Fall Time tf 8 15
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current IS TC = 25 °C 31.5
A
Pulse Diode Forward Currenta ISM 50
Body Diode Voltage VSD IS = 2.6 A 0.8 1.2 V
Body Diode Reverse Recovery Time trr 25 50 ns
Body Diode Reverse Recovery Charge Qrr 15 30 nC
IF = 2.6 A, di/dt = 100 A/µs, TJ = 25 °C
Reverse Recovery Fall Time ta 12.5
ns
Reverse Recovery Rise Time tb 12.5
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

www.vishay.com Document Number: 73451

2 S-80440-Rev. C, 03-Mar-08
 Si7686DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

50 10

VGS = 10 thru 4 V
40 8
I D - Drain Current (A)

I D - Drain Current (A)

30 6

20 4

TC = 125 °C
10 2
25 °C
3V
- 55 °C
0 0
0.0 0.4 0.8 1.2 1.6 2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)

Output Characteristics Transfer Characteristics

0.0140 1500

Ciss
0.0120 1200
R DS(on) - On-Resistance (mΩ)

VGS = 4.5 V
C - Capacitance (pF)

0.0100 900

VGS = 10 V
0.0080 600

Coss
0.0060 300
Crss

0.0040 0
0 10 20 30 40 50 0 5 10 15 20 25 30

ID - Drain Current (A) VDS - Drain-to-Source Voltage (V)

On-Resistance vs. Drain Current and Gate Voltage Capacitance

10 1.8

ID = 13.8 A ID = 13.8 A
1.6
VGS - Gate-to-Source Voltage (V)

8
R DS(on) - On-Resistance

VDS = 15 V VGS = 10 V
1.4
(Normalized)

6
VDS = 21 V
1.2 VGS = 4.5 V

4
1.0

2
0.8

0 0.6
0 4 8 12 16 20 - 50 - 25 0 25 50 75 100 125 150

Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C)

Gate Charge On-Resistance vs. Junction Temperature

Document Number: 73451 www.vishay.com

S-80440-Rev. C, 03-Mar-08 3
Si7686DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

50 0.030

R DS(on) - Drain-to-Source On-Resistance (Ω)

ID = 13.8 A
0.025
I S - Source Current (A)

TJ = 150 °C
10 0.020

TJ = 125 °C
0.015

TJ = 25 °C
0.010

TJ = 25 °C

1 0.005
0.00 0.2 0.4 0.6 0.8 1.0 1.2 3 4 5 6 7 8 9 10
VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage

2.6 50

2.4
40
2.2

2.0
Power (W)

30
VGS(th) (V)

ID = 250 µA
1.8
20
1.6

1.4
10
1.2

1.0 0
- 50 - 25 0 25 50 75 100 125 150 0.01 0.1 1 10 100 600
TJ - Temperature (°C) Time (s)
Threshold Voltage Single Pulse Power, Junction-to-Ambient

100

Limited by
RDS(on)*
10
1 ms
I D - Drain Current (A)

1 10 ms
100 ms
1s
10 s
0.1
DC

0.01
TA = 25 °C
Single Pulse

0.001
0.1 1 10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum V GS at which R DS(on) is specified
Safe Operating Area, Junction-to-Ambient

www.vishay.com Document Number: 73451

4 S-80440-Rev. C, 03-Mar-08
 Si7686DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

60 40

35
50
30
40
ID - Drain Current (A)

25

Power (W)
30 20
Package Limited
15
20
10
10
5

0 0
0 25 50 75 100 125 150 25 50 75 100 125 150

TC - Case Temperature (°C) TC - Case Temperature (°C)

Current Derating* Power Derating

* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.

Document Number: 73451 www.vishay.com

S-80440-Rev. C, 03-Mar-08 5
Si7686DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

1
Normalized Effective Transient

Duty Cycle = 0.5

Thermal Impedance

0.2
Notes:
0.1
0.1 PDM

0.05
t1
t2
t1
0.02 1. Duty Cycle, D =
t2
2. Per Unit Base = R thJA = 70 °C/W
3. T JM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10-4 10-3 10-2 10-1 1 10 100 600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient

1
Normalized Effective Transient

Duty Cycle = 0.5

Thermal Impedance

0.2

0.1

0.1

0.05

0.02

Single Pulse
0.01
10-4 10-3 10-2 10-1 1
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Case

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?73451.

www.vishay.com Document Number: 73451

6 S-80440-Rev. C, 03-Mar-08
 Package Information
Vishay Siliconix

PowerPAK® SO-8, (SINGLE/DUAL)

H L
E2 K
W E4

D4
1 1

M
Z

0.150 ± 0.008
2 2

D5
D

D1

D2
D
2
e
3 3

4 4

b
θ
L1
E3
A1 Backside View of Single Pad
θ θ
H L
E2 K
A E4
c

D3(2x) D4
E1 Detail Z 1
E D1
2

D5
K1
D2
3
D2

b
Notes
1. Inch will govern.
2 Dimensions exclusive of mold gate burrs. E3
Backside View of Dual Pad
3. Dimensions exclusive of mold flash and cutting burrs.

MILLIMETERS INCHES
DIM. MIN. NOM. MAX. MIN. NOM. MAX.
A 0.97 1.04 1.12 0.038 0.041 0.044
A1 0.00 - 0.05 0.000 - 0.002
b 0.33 0.41 0.51 0.013 0.016 0.020
c 0.23 0.28 0.33 0.009 0.011 0.013
D 5.05 5.15 5.26 0.199 0.203 0.207
D1 4.80 4.90 5.00 0.189 0.193 0.197
D2 3.56 3.76 3.91 0.140 0.148 0.154
D3 1.32 1.50 1.68 0.052 0.059 0.066
D4 0.57 TYP. 0.0225 TYP.
D5 3.98 TYP. 0.157 TYP.
E 6.05 6.15 6.25 0.238 0.242 0.246
E1 5.79 5.89 5.99 0.228 0.232 0.236
E2 3.48 3.66 3.84 0.137 0.144 0.151
E3 3.68 3.78 3.91 0.145 0.149 0.154
E4 0.75 TYP. 0.030 TYP.
e 1.27 BSC 0.050 BSC
K 1.27 TYP. 0.050 TYP.
K1 0.56 - - 0.022 - -
H 0.51 0.61 0.71 0.020 0.024 0.028
L 0.51 0.61 0.71 0.020 0.024 0.028
L1 0.06 0.13 0.20 0.002 0.005 0.008
θ 0° - 12° 0° - 12°
W 0.15 0.25 0.36 0.006 0.010 0.014
M 0.125 TYP. 0.005 TYP.
ECN: T10-0055-Rev. J, 15-Feb-10
DWG: 5881

Document Number: 71655 www.vishay.com

Revison: 15-Feb-10 1
 AN821
Vishay Siliconix

PowerPAK® SO-8 Mounting and Thermal Considerations

Wharton McDaniel

MOSFETs for switching applications are now available PowerPAK SO-8 SINGLE MOUNTING
with die on resistances around 1 mΩ and with the The PowerPAK single is simple to use. The pin
capability to handle 85 A. While these die capabilities arrangement (drain, source, gate pins) and the pin
represent a major advance over what was available dimensions are the same as standard SO-8 devices
just a few years ago, it is important for power MOSFET (see Figure 2). Therefore, the PowerPAK connection
packaging technology to keep pace. It should be obvi- pads match directly to those of the SO-8. The only dif-
ous that degradation of a high performance die by the ference is the extended drain connection area. To take
package is undesirable. PowerPAK is a new package immediate advantage of the PowerPAK SO-8 single
technology that addresses these issues. In this appli- devices, they can be mounted to existing SO-8 land
cation note, PowerPAK’s construction is described. patterns.
Following this mounting information is presented
including land patterns and soldering profiles for max-
imum reliability. Finally, thermal and electrical perfor-
mance is discussed.

THE PowerPAK PACKAGE

The PowerPAK package was developed around the
SO-8 package (Figure 1). The PowerPAK SO-8 uti-
lizes the same footprint and the same pin-outs as the
Standard SO-8 PowerPAK SO-8
standard SO-8. This allows PowerPAK to be substi-
tuted directly for a standard SO-8 package. Being a
leadless package, PowerPAK SO-8 utilizes the entire Figure 2.
SO-8 footprint, freeing space normally occupied by the
leads, and thus allowing it to hold a larger die than a The minimum land pattern recommended to take full
standard SO-8. In fact, this larger die is slightly larger advantage of the PowerPAK thermal performance see
than a full sized DPAK die. The bottom of the die attach Application Note 826, Recommended Minimum Pad
pad is exposed for the purpose of providing a direct, Patterns With Outline Drawing Access for Vishay Sili-
low resistance thermal path to the substrate the device conix MOSFETs. Click on the PowerPAK SO-8 single
is mounted on. Finally, the package height is lower in the index of this document.
than the standard SO-8, making it an excellent choice
In this figure, the drain land pattern is given to make full
for applications with space constraints.
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight and layer stack,
experiments have found that more than about 0.25 to
0.5 in2 of additional copper (in addition to the drain
land) will yield little improvement in thermal perfor-
mance.

Figure 1. PowerPAK 1212 Devices

Document Number 71622 www.vishay.com

28-Feb-06 1
AN821
Vishay Siliconix
PowerPAK SO-8 DUAL For the lead (Pb)-free solder profile, see http://
The pin arrangement (drain, source, gate pins) and the www.vishay.com/doc?73257.
pin dimensions of the PowerPAK SO-8 dual are the
same as standard SO-8 dual devices. Therefore, the
PowerPAK device connection pads match directly to
those of the SO-8. As in the single-channel package,
the only exception is the extended drain connection
area. Manufacturers can likewise take immediate
advantage of the PowerPAK SO-8 dual devices by
mounting them to existing SO-8 dual land patterns.

To take the advantage of the dual PowerPAK SO-8’s

thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
The gap between the two drain pads is 24 mils. This Ramp-Up Rate + 6 °C /Second Maximum
matches the spacing of the two drain pads on the Pow- Temperature at 155 ± 15 °C 120 Seconds Maximum
erPAK SO-8 dual package. Temperature Above 180 °C 70 - 180 Seconds
Maximum Temperature 240 + 5/- 0 °C
Time at Maximum Temperature 20 - 40 Seconds
Ramp-Down Rate + 6 °C/Second Maximum
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
Figure 3. Solder Reflow Temperature Profile
reflow reliability requirements. Devices are subjected
to solder reflow as a test preconditioning and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
ture profile used, and the temperatures and time
duration, are shown in Figures 3 and 4.

10 s (max)
210 - 220 °C

3 °C(max) 4 °C/s (max)

183 °C
140 - 170 °C

50 s (max)

3 °C(max) 60 s (min) Reflow Zone

Pre-Heating Zone

Maximum peak temperature at 240 °C is allowed.

Figure 3. Solder Reflow Temperatures and Time Durations

www.vishay.com Document Number 71622

2 28-Feb-06
 AN821
Vishay Siliconix
THERMAL PERFORMANCE

Introduction Because of the presence of the trough, this result sug-

gests a minimum performance improvement of 10 °C/W
A basic measure of a device’s thermal performance is by using a PowerPAK SO-8 in a standard SO-8 PC
the junction-to-case thermal resistance, Rθjc, or the board mount.
junction-to-foot thermal resistance, Rθjf. This parameter
is measured for the device mounted to an infinite heat The only concern when mounting a PowerPAK on a
sink and is therefore a characterization of the device standard SO-8 pad pattern is that there should be no
only, in other words, independent of the properties of the traces running between the body of the MOSFET.
object to which the device is mounted. Table 1 shows a Where the standard SO-8 body is spaced away from the
comparison of the DPAK, PowerPAK SO-8, and stan- pc board, allowing traces to run underneath, the Power-
dard SO-8. The PowerPAK has thermal performance PAK sits directly on the pc board.
equivalent to the DPAK, while having an order of magni-
tude better thermal performance over the SO-8. Thermal Performance - Spreading Copper

TABLE 1. Designers may add additional copper, spreading cop-

DPAK and PowerPAK SO-8
per, to the drain pad to aid in conducting heat from a
Equivalent Steady State Performance device. It is helpful to have some information about the
DPAK PowerPAK Standard thermal performance for a given area of spreading cop-
SO-8 SO-8 per.
Thermal
Resistance Rθjc 1.2 °C/W 1.0 °C/W 16 °C/W Figure 6 shows the thermal resistance of a PowerPAK
SO-8 device mounted on a 2-in. 2-in., four-layer FR-4
Thermal Performance on Standard SO-8 Pad Pattern PC board. The two internal layers and the backside layer
are solid copper. The internal layers were chosen as
Because of the common footprint, a PowerPAK SO-8 solid copper to model the large power and ground
can be mounted on an existing standard SO-8 pad pat- planes common in many applications. The top layer was
tern. The question then arises as to the thermal perfor- cut back to a smaller area and at each step junction-to-
mance of the PowerPAK device under these conditions. ambient thermal resistance measurements were taken.
A characterization was made comparing a standard SO-8 The results indicate that an area above 0.3 to 0.4 square
and a PowerPAK device on a board with a trough cut out inches of spreading copper gives no additional thermal
underneath the PowerPAK drain pad. This configuration performance improvement. A subsequent experiment
restricted the heat flow to the SO-8 land pads. The was run where the copper on the back-side was
results are shown in Figure 5. reduced, first to 50 % in stripes to mimic circuit traces,
and then totally removed. No significant effect was
observed.
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board Rth vs. Spreading Copper
SO-8 Pattern, Trough Under Drain (0 %, 50 %, 100 % Back Copper)
60 56

50
Impedance (C/watts)

51
Impedance (C/watts)

40
Si4874DY
30
46
Si7446DP
20

41 100 %
10
0%

0 50 %
0.0001 0.01 1 100 10000 36
Pulse Duration (sec) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 5. PowerPAK SO-8 and Standard SO-0 Land Pad Thermal Path Figure 6. Spreading Copper Junction-to-Ambient Performance

Document Number 71622 www.vishay.com

28-Feb-06 3
AN821
Vishay Siliconix
SYSTEM AND ELECTRICAL IMPACT OF Suppose each device is dissipating 2.7 W. Using the
PowerPAK SO-8 junction-to-foot thermal resistance characteristics of the
In any design, one must take into account the change in PowerPAK SO-8 and the standard SO-8, the die tem-
MOSFET rDS(on) with temperature (Figure 7). perature is determined to be 107 °C for the PowerPAK
(and for DPAK) and 148 °C for the standard SO-8. This
is a 2 °C rise above the board temperature for the Pow-
On-Resistance vs. Junction Temperature erPAK and a 43 °C rise for the standard SO-8. Referring
1.8
to Figure 7, a 2 °C difference has minimal effect on
VGS = 10 V rDS(on) whereas a 43C difference has a significant effect
1.6 ID = 23 A on rDS(on).
r DS(on) - On-Resistance ( )

1.4 Minimizing the thermal rise above the board tempera-

(Normalized)

ture by using PowerPAK has not only eased the thermal

1.2 design but it has allowed the device to run cooler, keep
rDS(on) low, and permits the device to handle more cur-
1.0
rent than the same MOSFET die in the standard SO-8
package.
0.8

CONCLUSIONS
0.6
- 50 - 25 0 25 50 75 100 125 150 PowerPAK SO-8 has been shown to have the same
thermal performance as the DPAK package while hav-
TJ - Junction Temperature (°C)
ing the same footprint as the standard SO-8 package.
Figure 7. MOSFET rDS(on) vs. Temperature The PowerPAK SO-8 can hold larger die approximately
equal in size to the maximum that the DPAK can accom-
A MOSFET generates internal heat due to the current modate implying no sacrifice in performance because of
passing through the channel. This self-heating raises package limitations.
the junction temperature of the device above that of the Recommended PowerPAK SO-8 land patterns are pro-
PC board to which it is mounted, causing increased vided to aid in PC board layout for designs using this
power dissipation in the device. A major source of this new package.
problem lies in the large values of the junction-to-foot
thermal resistance of the SO-8 package. Thermal considerations have indicated that significant
advantages can be gained by using PowerPAK SO-8
PowerPAK SO-8 minimizes the junction-to-board ther- devices in designs where the PC board was laid out for
mal resistance to where the MOSFET die temperature is the standard SO-8. Applications experimental data gave
very close to the temperature of the PC board. Consider thermal performance data showing minimum and typical
two devices mounted on a PC board heated to 105 °C thermal performance in a SO-8 environment, plus infor-
by other components on the board (Figure 8). mation on the optimum thermal performance obtainable
including spreading copper. This further emphasized the
DPAK equivalency.

PowerPAK SO-8 Standard SO-8

PowerPAK SO-8 therefore has the desired small size
characteristics of the SO-8 combined with the attractive
107 °C 148 °C
thermal characteristics of the DPAK package.

0.8 °C/W 16 C/W

PC Board at 105 °C

Figure 8. Temperature of Devices on a PC Board

www.vishay.com Document Number 71622

4 28-Feb-06
 Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single

0.260
(6.61)
0.150
(3.81)

0.024
(0.61)

(3.91)

(4.42)
0.154

0.174
0.026
(0.66)
(1.27)
0.050

0.050 0.032 0.040

(1.27) (0.82) (1.02)

Recommended Minimum Pads

Dimensions in Inches/(mm)

Return to Index
Return to Index

APPLICATION NOTE

Document Number: 72599 www.vishay.com

Revision: 21-Jan-08 15
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Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
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liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
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provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.

Material Category Policy

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.

Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.

Revision: 02-Oct-12 1 Document Number: 91000