The University of Alabama in Huntsville

ECE Department
CPE 628 01
Test 1 Solution
Fall 2008

1. (10 points) For the circuit shown, calculate the probability-based observabilities given the
controllabilities given.
d
a
e
j
b
k g
f
i
h

Line 0-C/1-C/O
f 0.5/0.5/_0.0625_
a 0.5/0.5/_0.25_
h 0.5/0.5/_0.0625_
b 0.5/0.5/_0.25_
i 0.125/0.5/_0.125_
c 0.5/0.5/_0.03125_
j 0.5/0.25/_0.5_
d 0.5/0.5/_0.25_
k 0.25/0.5/_0.25_
e 0.5/0.5/_0.25_
g 0.125/0.5/_1

O(g) =1 O(j) = O(g)*C1(k) = 1*0.5 = 0.5 O(k) = O(g)*C1(j) = 1*0.25 = 0.25

O(i) = O(k)*C1(c) = 0.25*0.5 = 0.125 O(c) = O(k)*C1(i) = 0.25*0.125 = 0.03125
O(h) = O(i)*C1(f) = 0.125*0.5 = 0.0625 O(f) = O(i)*C1(h) = 0.125*0.5 = 0.0625
O(e) = O(j)*C1(d) = 0.5*0.5 = 0.25 O(d) = O(j)*C1(e) = 0.5*0.5 = 0.25
O(a) = max{O(d), O(h) = max{0.25, 0.0625} = 0.25
O(b) = max{O(e), O(f) = max{0.25, 0.0625} = 0.25

2. (5 points) The number of failures in 109 hours is a unit (abbreviated FITS) that is often used in
reliability calculations. Calculate the MTBF for a system with 10 components where each
component has a failure rate of 3000 FITS.

k
3000 3000
λ = ∑ λi , λi = 9
. Thus, λ = 9
*10 = 3*10-5
i =1 10 10
1
MTBF = =1/3*105 hours = 33,333 hours
λ

3. (10 points) Generate a minimum set of test vectors to completely test an n-input XOR gate under
the single stuck-at fault model. How many test vectors are needed? at most 3

There are two cases, n odd and n even

 For n odd, two patterns are required. The test pattern 111…1 will detect all s-a-0 faults on inputs
and the test pattern 000…0 will detect all s-a-a faults on inputs. The s-a-0 fault on the output is
detected by the all 1s pattern and the s-a-1 fault on the output is detected by the all 0s pattern.

For n even, a third pattern is required to detect the s-a-0 fault on the output. This pattern must
have an odd number of 1s.

4. (15 points) For the circuit given, calculate the SCOAP controllability measures.

c
d h j
a m
b e k
g i
f

CO(a) = CO(b) = 1 C1(a) = C1(b) = 1 C0(c) = C0(d) = C0(e) = C0(f) = 1

C1(c) = C1(d) = C1(e) = C1(f) = 1 C0(g) = C1(d) + C1(e) + 1 = 1 + 1 + 1 = 3
C1(g) = min{C0(d), C0(e)} + 1 = min{1, 1} + 1 = 1 + 1 = 2 C0(h) = C0(i) = C0(g) = 3
C1(h) = C1(i) = C1(g) = 2 C0(j) = C1(c) + C1(h) + 1 = 1 + 2 + 1 = 4
C1(j) = min{C0(c), C0(h)} + 1 = min{1, 3} + 1 = 1 + 1 = 2
C0(k) = C1(i) + C1(f) + 1 = 2 + 1 + 1 = 4
C1(k) = min{C0(i), C0(f)} + 1 = min{3, 1} + 1 = 1 + 1 = 2
C0(m) = C1(j) + C1(k) + 1 = 2 + 2 + 1 = 5
C1(m) = min{C0(j), C0(k)} + 1 = min{4, 4} + 1 = 4 + 1 = 5

5. (1 point) The symbol _u_ represents the logic value unknown.

6. (10 points) For the circuit shown and the two faults α = e/0, β = f/1, use the parallel-pattern
single-fault propagation technique to identify which faults can be detected by the test patterns
(a, b, c, d) = (0, 1, 0, 1), (1, 1, 0, 1).

m
g u
n
e

o
a v
h p
b q z
i r
c
w
f
d
j
s
k x
t
 PPSFP input internal output
fault P a b c d e f g h i j k m n o p q r s t u v w x z
fault- P1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 1 1 0 0 0 1 0 1 1
free P2 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1
P1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 1 1 0 0 0 1 0 1 1
α
P2 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1
P1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 1 1 0 0 0 1 0 1 1
β
P2 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1

Neither of the faults are detected.

7. (1 point) A _defect_ is a flaw or physical imperfection that may lead to a fault.

8. (1 point) The goal of _test generation_ is to find an efficient set of test vectors that detects all
faults considered for a circuit.
9. (10 points) Use the circuit, faults and patterns of problem 6 to do parallel fault simulation.

m
g u
n
e

o
a v
h p
b q z
i r
c
w
f
d
j
s
k x
t

PPSFP input internal output

fault P a b c d e f g h i j k m n o p q r s t u v w x z
ff P1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 1 1 0 0 0 1 0 1 1
α P1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 1 1 0 0 0 1 0 1 1
β P1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 1 1 0 0 0 1 0 1 1
ff P2 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1
α P2 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1
β P2 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1

Neither of the faults are detected.

10. (1 point) The most widely used structured DFT methodology is _scan design_.
11. (1 point) _Logic simulation_ helps the designer verify that a design conforms to the functional
specifications.
12. (15 points) For the circuit shown, use deductive fault simulation to determine the faults detected
by the pattern shown.
d 1
1 a
e 0
j 0
0 b 1
k 1 g
f 0 0 i
h 1

1 c

La = {a/0} Lb = {b/1} Lc = {c/0} Ld = {a/0, d/0} Le = {b/1, e/1}

Lf = {b/1, f/1} Lh = {a/0, h/0} Li = {b/1, f/1, i/1}
Lj = {a/0, d/0, j/1} Lk = {b/1, c/0, f/1, i/1, k/0} Lg = {a/0, d/0, j/1, g/0}

13. (15 points) For the circuit shown, use concurrent fault simulation to determine whether the faults
g/0, c/0, k/0 are detectable for the pattern given.

c
d h j
1 a m
0 b e k
g i
f

0
c/0 1
1 1
c/0 0
c 1
1
d h 0 j
1 a 1 1 0 m
0 b e 1 k 1
0 g i 1
1
f 1
0 0
k/0 1
0 0
g/0 1
0
Only c/0 is detectable.