April 1997

NDS351AN
N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description Features

These N-Channel logic level enhancement mode power field 1.2A, 30 V. RDS(ON) = 0.25 Ω @ VGS = 4.5 V
effect transistors are produced using Fairchild's proprietary, RDS(ON) = 0.16 Ω @ VGS = 10 V.
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance. Industry standard outline SOT-23 surface mount package
These devices are particularly suited for low voltage using proprietary SuperSOTTM-3 design for superior
applications in notebook computers, portable phones, PCMCIA thermal and electrical capabilities.
cards, and other battery powered circuits where fast
switching, and low in-line power loss are needed in a very small High density cell design for extremely low RDS(ON).
outline surface mount package.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount

_________________________________________________________________________________

G S

Absolute Maximum Ratings T A = 25°C unless otherwise noted

Symbol Parameter NDS351AN Units
VDSS Drain-Source Voltage 30 V
VGSS Gate-Source Voltage - Continuous 20 V
ID Maximum Drain Current - Continuous (Note 1a) ± 1.2 A
- Pulsed ± 10
PD Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b) 0.46
TJ,TSTG Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W

© 1997 Fairchild Semiconductor Corporation NDS351AN Rev. C

Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1 µA
TJ =125°C 10 µA
IGSSF Gate - Body Leakage, Forward VGS = 20 VDS = 0 V 100 nA
IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS = 0 V -100 nA
ON CHARACTERISTICS (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.8 1.7 2 V
TJ =125°C 0.5 1.3 1.5
RDS(ON) Static Drain-Source On-Resistance VGS = 4.5 V, ID = 1.2 A 0.19 0.25 Ω
TJ =125°C 0.28 0.37
VGS = 10 V, ID = 1.4 A 0.125 0.16
ID(ON) On-State Drain Current VGS = 4.5 V, VDS = 5 V 3.5 A
gFS Forward Transconductance VDS = 5 V, ID= 1.2 A, 1.8 S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VDS = 10 V, VGS = 0 V, 125 pF
f = 1.0 MHz
Coss Output Capacitance 100 pF
Crss Reverse Transfer Capacitance 90 pF
SWITCHING CHARACTERISTICS (Note 2)

td(on) Turn - On Delay Time VDD = 10 V, ID = 1 A, 6 15 ns

tr Turn - On Rise Time VGS = 10 V, RGEN = 50 Ω 15 30 ns
td(off) Turn - Off Delay Time 14 30 ns
tf Turn - Off Fall Time 18 40 ns
Qg Total Gate Charge VDS = 10 V, ID = 1.2 A, 1.9 2.7 nC
VGS = 4.5 V
Q gs Gate-Source Charge 0.5 nC
Q gd Gate-Drain Charge 0.9 nC

NDS351AN Rev. C
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS Maximum Continuous Drain-Source Diode Forward Current 0.42 A
ISM Maximum Pulsed Drain-Source Diode Forward Current 5 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.2 A (Note 2) 0.8 1.2 V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is

guaranteed by design while RθCA is determined by the user's board design.

T J− TA − TA
P D (t ) = = = I 2D (t ) × RDS(ON )
TJ
R θJA(t ) R θJC+RθCA(t ) TJ

Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper.

b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.

1a 1b

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

NDS351AN Rev. C
 Typical Electrical Characteristics

5 1.8
V GS =10V 6.0
5.0

DRAIN-SOURCE ON-RESISTANCE
4.5 1.6
I D , DRAIN-SOURCE CURRENT (A)

4 4.0 VGS = 3.5V

R DS(on ) , NORMALIZED
1.4

3 1.2 4.0
3.5
1 4.5
2 5.0
0.8 6.0
3.0 7.0
1
0.6 10

0 0.4
0 1 2 3 0 1 2 3 4
V , DRAIN-SOURCE VOLTAGE (V) I D , DRAIN CURRENT (A)
DS

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation

with Drain Current and Gate Voltage.

1.8 1.8
I D = 1.2A VGS = 4.5 V
DRAIN-SOURCE ON-RESISTANCE
DRAIN-SOURCE ON-RESISTANCE

1.6 1.6 TJ = 125°C

V GS = 4.5V
R DS(ON), NORMALIZED

RDS(on) , NORMALIZED

1.4
1.4

1.2
1.2 25°C
1
1 -55°C
0.8

0.8
0.6

0.6 0.4
-50 -25 0 25 50 75 100 125 150 0 1 2 3 4
TJ , JUNCTION TEMPERATURE (°C) I D, DRAIN CURRENT (A)

Figure 3. On-Resistance Variation Figure 4. On-Resistance Variation

with Temperature. with Drain Current and Temperature.

5 1.2
T = -55°C
GATE-SOURCE THRESHOLD VOLTAGE

V DS = 5.0V J 25°C
1.1 V DS= V GS
4
I D = 250µA
Vth , NORMALIZED

125°C
I D , DRAIN CURRENT (A)

1
3

0.9
2
0.8

1
0.7

0 0.6
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -50 -25 0 25 50 75 100 125 150
V , GATE TO SOURCE VOLTAGE (V) TJ , JUNCTION TEMPERATURE (°C)
GS

Figure 5. Transfer Characteristics. Figure 6. Gate Threshold Variation

with Temperature.

NDS351AN Rev. C
Typical Electrical Characteristics (continued)

1.12 5
V GS = 0V
DRAIN-SOURCE BREAKDOWN VOLTAGE

I D = 250µA

I , REVERSE DRAIN CURRENT (A)

1
1.08
TJ = 125°C
BV DSS , NORMALIZED

25°C
0.1
1.04 -55°C

1 0.01

0.96 0.001

S
0.92
-50 -25 0 25 50 75 100 125 150 0.0001
0 0.2 0.4 0.6 0.8 1 1.2
T , JUNCTION TEMPERATURE (°C)
J V SD , BODY DIODE FORWARD VOLTAGE (V)

Figure 7. Breakdown Voltage Variation with Figure 8. Body Diode Forward Voltage Variation with
Temperature. Source Current and Temperature.

10
400
I D = 1.2A 10V
, GATE-SOURCE VOLTAGE (V)
VDS = 5V
300
8
15V
CAPACITANCE (pF)

200
6
150
C iss
4
100 C oss

80 f = 1 MHz
2
C rss
GS

V GS = 0V
V

50 0
0.1 0.2 0.5 1 2 5 10 20 30 0 1 2 3 4
V , DRAIN TO SOURCE VOLTAGE (V) Q g , GATE CHARGE (nC)
DS

Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics.

VDD t on t off
t d(on) tr t d(off) tf
V IN RL 90%
90%
D V OUT
VOUT
VGS 10% 10%
R GEN DUT INVERTED
G
90%

V IN 50% 50%
S
10%

PULSE WIDTH

Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms.

NDS351AN Rev. C
 Typical Electrical Characteristics (continued)

5 20
, TRANSCONDUCTANCE (SIEMENS)

VDS = 5.0V 10 1m
s
4 T J = -55°C 5
10m

I D , DRAIN CURRENT (A)

3 IT
LIM s
N)
S(O
25°C RD
3 1 100
ms

0.3 1s
125°C
2 10s
0.1 V GS = 4.5V DC
1
SINGLE PULSE
0.03 RθJA =See Note1b
FS

TA = 25°C
g

0 0.01
0 1 2 3 4 5 0.1 0.2 0.5 1 2 5 10 20 30 50
I , DRAIN CURRENT (A) V , DRAI N-SOURCE VOLTAGE (V)
D DS

Figure 13. Transconductance Variation with Figure 14. Maximum Safe Operating Area.
Drain Current and Temperature.

1 1.6
STEADY-STATE POWER DISSIPATION (W)

I , STEADY-STATE DRAIN CURRENT (A)

0.8
1.4

0.6 1a
1.2 1a
1b
0.4
1b 4.5"x5" FR-4 Board
o
1 TA = 2 5 C
0.2 Still Air
4.5"x5" FR-4 Board VG S = 4 . 5 V
TA = 25 oC
D

Still Air
0 0.8
0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4
2oz COPPER MOUNTING PAD AREA (in 2 ) 2oz COPPER MOUNTING PAD AREA (in 2 )

Figue 15. SuperSOTTM _ 3 Maximum Steady-State Figure 16. Maximum Steady-State Drain
Power Dissipation versus Copper Mounting Pad Area. Current versus Copper Mounting Pad Area.

1
TRANSIENT THERMAL RESISTANCE

0.5 D = 0.5
r(t), NORMALIZED EFFECTIVE

R θJA (t) = r(t) * R θJA

0.2 0.2
R θJA = See Note 1b
0.1 0.1

0.05 0.05
P(pk)
0.02
0.02 t1
0.01 t2
0.01
Single Pulse TJ - TA = P * R θJA (t)
0.005
Duty Cycle, D = t1 /t2
0.002

0.001
0.0001 0.001 0.01 0.1 1 10 100 300
t 1 , TIME (sec)

Figure 17. Transient Thermal Response Curve.

Note : Characterization performed using the conditions described in note 1b. Transient thermal response will
change depending on the circuit board design.

NDS351AN Rev. C