SEMICONDUCTOR TECHNICAL DATA

 
!  " 
! #
! #
High–Performance Silicon–Gate CMOS J SUFFIX
CERAMIC PACKAGE
The MC54/74HC4066 utilizes silicon–gate CMOS technology to achieve 14 CASE 632–08
fast propagation delays, low ON resistances, and low OFF–channel leakage 1
current. This bilateral switch/multiplexer/demultiplexer controls analog and
digital voltages that may vary across the full power–supply range (from VCC
to GND). N SUFFIX
The HC4066 is identical in pinout to the metal–gate CMOS MC14016 and PLASTIC PACKAGE
14
MC14066. Each device has four independent switches. The device has CASE 646–06
been designed so that the ON resistances (RON) are much more linear over 1
input voltage than RON of metal–gate CMOS analog switches.
This device is identical in both function and pinout to the HC4016. The
D SUFFIX
ON/OFF control inputs are compatible with standard CMOS outputs; with 14 SOIC PACKAGE
pullup resistors, they are compatible with LSTTL outputs. For analog 1 CASE 751A–03
switches with voltage–level translators, see the HC4316.
• Fast Switching and Propagation Speeds
• High ON/OFF Output Voltage Ratio DT SUFFIX
• Low Crosstalk Between Switches 14 TSSOP PACKAGE
CASE 948G–01
• Diode Protection on All Inputs/Outputs 1
• Wide Power–Supply Voltage Range (VCC – GND) = 2.0 to 12.0 Volts
• Analog Input Voltage Range (VCC – GND) = 2.0 to 12.0 Volts ORDERING INFORMATION
• Improved Linearity and Lower ON Resistance over Input Voltage than MC54HCXXXXJ Ceramic
the MC14016 or MC14066 or HC4016 MC74HCXXXXN Plastic
• Low Noise MC74HCXXXXD SOIC
MC74HCXXXXDT TSSOP
• Chip Complexity: 44 FETs or 11 Equivalent Gates

LOGIC DIAGRAM PIN ASSIGNMENT

XA 1 14 VCC
A ON/OFF
1 2 YA 2 13 CONTROL
XA YA
YB 3 12 D ON/OFF
CONTROL
13 XB 4 11 XD
A ON/OFF CONTROL
B ON/OFF
CONTROL 5 10 YD
4 3
XB YB C ON/OFF 6 9 YC
CONTROL
GND 7 8 XC
5 ANALOG
B ON/OFF CONTROL OUTPUTS/INPUTS

8 9
XC YC
FUNCTION TABLE
6 On/Off Control State of
C ON/OFF CONTROL
Input Analog Switch
11 10 L Off
XD YD
H On

12
D ON/OFF CONTROL ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD
PIN 14 = VCC
PIN 7 = GND

10/95

 Motorola, Inc. 1995 1 REV 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC54/74HC4066
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Value Unit This device contains protection

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) – 0.5 to + 14.0 V circuitry to guard against damage

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
due to high static voltages or electric
VIS Analog Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin Digital Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V
be taken to avoid applications of any

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
voltage higher than maximum rated
I DC Current Into or Out of Any Pin ± 25 mA voltages to this high–impedance cir-

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
cuit. For proper operation, Vin and
PD Power Dissipation in Still Air, Plastic or Ceramic DIP† 750 mW

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vout should be constrained to the
SOIC Package† 500
v
range GND (Vin or Vout) VCC. v
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TSSOP Package† 450
Unused inputs must always be

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C tied to an appropriate logic voltage
level (e.g., either GND or VCC).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C Unused outputs must be left open.
(Plastic DIP, SOIC or TSSOP Package) 260

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
I/O pins must be connected to a
(Ceramic DIP) 300 properly terminated line or bus.
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) 2.0 12.0 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIS Analog Input Voltage (Referenced to GND) GND VCC V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin Digital Input Voltage (Referenced to GND) GND VCC V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIO* Static or Dynamic Voltage Across Switch — 1.2 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf Input Rise and Fall Time, ON/OFF Control ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Inputs (Figure 10) VCC = 2.0 V 0 1000
VCC = 4.5 V 0 500

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VCC = 9.0 V 0 400

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC = 12.0 V 0 250

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
* For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input components.

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v v
VCC – 55 to

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIH Minimum High–Level Voltage Ron = Per Spec 2.0 1.5 1.5 1.5 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ON/OFF Control Inputs 4.5 3.15 3.15 3.15
9.0 6.3 6.3 6.3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
12.0 8.4 8.4 8.4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIL Maximum Low–Level Voltage Ron = Per Spec 2.0 0.3 0.3 0.3 V
ON/OFF Control Inputs 4.5 0.9 0.9 0.9

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 9.0 1.8 1.8 1.8

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
12.0 2.4 2.4 2.4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Current Vin = VCC or GND 12.0 ± 0.1 ± 1.0 ± 1.0 µA
ON/OFF Control Inputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 2 20 40 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Current (per Package) VIO = 0 V 12.0 8 80
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
160

MOTOROLA 2 High–Speed CMOS Logic Data

DL129 — Rev 6
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC4066

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Ron
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum “ON” Resistance Vin = VIH 2.0† — — — Ω

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIS = VCC to GND 4.5 170 215 255
v IS 2.0 mA (Figures 1, 2) 9.0 85 106 130

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
12.0 85 106 130

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = VIH 2.0 — — —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIS = VCC or GND (Endpoints) 4.5 85 106 130
v IS 2.0 mA (Figures 1, 2) 9.0 63 78 95

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
12.0 63 78 95

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
∆Ron Maximum Difference in “ON” Vin = VIH 2.0 — — — Ω

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Resistance Between Any Two VIS = 1/2 (VCC – GND) 4.5 30 35 40
v
Channels in the Same Package IS 2.0 mA 9.0 20 25 30

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
12.0 20 25 30

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Ioff Maximum Off–Channel Leakage Vin = VIL 12.0 0.1 0.5 1.0 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Current, Any One Channel VIO = VCC or GND
Switch Off (Figure 3)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Ion Maximum On–Channel Leakage Vin = VIH 12.0 0.1 0.5 1.0 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Current, Any One Channel VIS = VCC or GND
(Figure 4)
†At supply voltage (V CC – GND) approaching 2 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
operation, it is recommended that these devices only be used to control digital signals.

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Analog Input to Analog Output 2.0 50 65 75 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL (Figures 8 and 9) 4.5 10 13 15
9.0 10 13 15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
12.0 10 13 15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ, Maximum Propagation Delay, ON/OFF Control to Analog Output 2.0 150 190 225 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ (Figures 10 and 11) 4.5 30 38 45
9.0 30 30 30

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
12.0 30 30 30

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZL, Maximum Propagation Delay, ON/OFF Control to Analog Output 2.0 125 160 185 ns
tPZH (Figures 10 and 1 1) 4.5 25 32 37

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 9.0 25 32 37

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
12.0 25 32 37

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
C Maximum Capacitance ON/OFF Control Input — 10 10 10 pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Control Input = GND
Analog I/O — 35 35 35

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
NOTES:
Feedthrough — 1.0 1.0 1.0

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* 15 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).

High–Speed CMOS Logic Data 3 MOTOROLA

DL129 — Rev 6
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC54/74HC4066

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Limit*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC 25_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 54/74HC Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
BW Maximum On–Channel Bandwidth or fin = 1 MHz Sine Wave 4.5 150 MHz
Minimum Frequency Response Adjust fin Voltage to Obtain 0 dBm at VOS 9.0 160

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 5) Increase fin Frequency Until dB Meter Reads – 3 dB 12.0 160
RL = 50 Ω, CL = 10 pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
— Off–Channel Feedthrough Isolation fin Sine Wave 4.5 – 50 dB
(Figure 6) Adjust fin Voltage to Obtain 0 dBm at VIS 9.0 – 50

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fin = 10 kHz, RL = 600 Ω, CL = 50 pF 12.0 – 50

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 4.5 – 40

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
9.0 – 40
12.0 – 40

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
— v
Feedthrough Noise, Control to Vin 1 MHz Square Wave (tr = tf = 6 ns) 4.5 60 mVPP

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Switch Adjust RL at Setup so that IS = 0 A 9.0 130
RL = 600 Ω, CL = 50 pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 7) 12.0 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RL = 10 kΩ, CL = 10 pF 4.5 30
9.0 65

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
12.0 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
— Crosstalk Between Any Two Switches fin Sine Wave 4.5 – 70 dB
(Figure 12)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Adjust fin Voltage to Obtain 0 dBm at VIS 9.0 – 70
fin = 10 kHz, RL = 600 Ω, CL = 50 pF 12.0 – 70

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 4.5 – 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
9.0 – 80
12.0 – 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
THD Total Harmonic Distortion fin = 1 kHz, RL = 10 kΩ, CL = 50 pF %

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 14) THD = THDMeasured – THDSource

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIS = 4.0 VPP sine wave 4.5 0.10
VIS = 8.0 VPP sine wave 9.0 0.06

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VIS = 11.0 VPP sine wave

* Guaranteed limits not tested. Determined by design and verified by qualification.
12.0 0.04

MOTOROLA 4 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC4066

600 120
125°C
500 100
R on , ON RESISTANCE (OHMS)

R on , ON RESISTANCE (OHMS)
400 80
25°C

300 60
– 55°C
200 40
– 55°C
25°C
100 20
125°C

0 0
0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1a. Typical On Resistance, VCC = 2.0 V Figure 1b. Typical On Resistance, VCC = 4.5 V

80 120
70 125°C
100
R on , ON RESISTANCE (OHMS)

R on , ON RESISTANCE (OHMS)
60
25°C 80
50
125°C
40 – 55°C 60
25°C
30
40
20 – 55°C
20
10

0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1c. Typical On Resistance, VCC = 6.0 V Figure 1d. Typical On Resistance, VCC = 9.0 V

80 PLOTTER

70
R on , ON RESISTANCE (OHMS)

60 PROGRAMMABLE
125°C POWER MINI COMPUTER DC ANALYZER
50 SUPPLY
25°C
40 – + VCC
DEVICE
30 UNDER TEST
– 55°C
20
ANALOG IN COMMON OUT
10

0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 11 12 GND
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1e. Typical On Resistance, VCC = 12 V Figure 2. On Resistance Test Set–Up

High–Speed CMOS Logic Data 5 MOTOROLA

DL129 — Rev 6
MC54/74HC4066

VCC

VCC VCC
GND 14 VCC 14
A ON N/C
VCC A OFF GND

SELECTED VIL SELECTED VIH

CONTROL CONTROL
7 INPUT 7 INPUT

Figure 3. Maximum Off Channel Leakage Current, Figure 4. Maximum On Channel Leakage Current,
Any One Channel, Test Set–Up Test Set–Up

VCC VOS VIS VCC VOS

14 14
fin ON fin OFF
dB dB
0.1µF CL* 0.1µF CL*
METER RL METER

SELECTED
CONTROL
SELECTED VCC INPUT
CONTROL
7 INPUT 7

*Includes all probe and jig capacitance. *Includes all probe and jig capacitance.

Figure 5. Maximum On–Channel Bandwidth Figure 6. Off–Channel Feedthrough Isolation,

Test Set–Up Test Set–Up

VCC/2 VCC VCC/2

14

RL RL
VOS
OFF/ON IS
VCC
CL*
50%
SELECTED ANALOG IN
CONTROL GND
Vin ≤ 1 MHz 7 INPUT tPLH tPHL
tr = tf = 6 ns
VCC
GND CONTROL
50%
ANALOG OUT
*Includes all probe and jig capacitance.

Figure 7. Feedthrough Noise, ON/OFF Control to Figure 8. Propagation Delays, Analog In to

Analog Out, Test Set–Up Analog Out

MOTOROLA 6 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC4066

VCC tr tf
14 VCC
90%
ANALOG IN ANALOG OUT TEST CONTROL 50%
ON POINT 10% GND
CL*
tPZL tPLZ
HIGH
IMPEDANCE
SELECTED VCC 50%
10% VOL
CONTROL
7 ANALOG
INPUT tPZH tPHZ
OUT
90% VOH
50%
*Includes all probe and jig capacitance. HIGH
IMPEDANCE

Figure 9. Propagation Delay Test Set–Up Figure 10. Propagation Delay, ON/OFF Control
to Analog Out

POSITION 1 WHEN TESTING tPHZ AND tPZH VIS

POSITION 2 WHEN TESTING tPLZ AND tPZL VCC
1
14
RL VOS
2
VCC fin ON
VCC 14 1 kΩ 0.1 µF
1
TEST OFF
ON/OFF POINT
2 VCC OR GND
CL* RL CL* RL CL*
RL
SELECTED
SELECTED
CONTROL VCC/2 VCC/2
CONTROL
INPUT
INPUT
7
7
VCC/2
*Includes all probe and jig capacitance. *Includes all probe and jig capacitance.

Figure 11. Propagation Delay Test Set–Up Figure 12. Crosstalk Between Any Two Switches,
Test Set–Up

VCC

A
VIS
14 VCC VOS
0.1 µF TO
N/C OFF/ON N/C fin ON DISTORTION
CL* METER
RL

SELECTED VCC/2
7 CONTROL SELECTED VCC
INPUT CONTROL
7
INPUT
ON/OFF CONTROL

*Includes all probe and jig capacitance.

Figure 13. Power Dissipation Capacitance Figure 14. Total Harmonic Distortion, Test Set–Up
Test Set–Up

High–Speed CMOS Logic Data 7 MOTOROLA

DL129 — Rev 6
MC54/74HC4066

0
– 10 FUNDAMENTAL FREQUENCY
– 20
– 30
– 40

dBm
– 50
DEVICE
– 60
SOURCE
– 70
– 80
– 90

1.0 2.0 3.0

FREQUENCY (kHz)
Figure 15. Plot, Harmonic Distortion

APPLICATION INFORMATION below, the difference between VCC and GND is twelve volts.
Therefore, using the configuration in Figure 16, a maximum
The ON/OFF Control pins should be at V CC or GND logic analog signal of twelve volts peak–to–peak can be con-
levels, VCC being recognized as logic high and GND being trolled.
recognized as a logic low. Unused analog inputs/outputs When voltage transients above VCC and/or below GND
may be left floating (not connected). However, it is advisable
are anticipated on the analog channels, external diodes (Dx)
to tie unused analog inputs and outputs to VCC or GND
are recommended as shown in Figure 17. These diodes
through a low value resistor. This minimizes crosstalk and
feedthrough noise that may be picked–up by the unused I/O should be small signal, fast turn–on types able to absorb the
pins. maximum anticipated current surges during clipping. An
The maximum analog voltage swings are determined by alternate method would be to replace the Dx diodes with
the supply voltages VCC and GND. The positive peak analog MO  sorbs (Motorola high current surge protectors).
voltage should not exceed VCC. Similarly, the negative peak MOsorbs are fast turn–on devices ideally suited for precise
analog voltage should not go below GND. In the example DC protection with no inherent wear out mechanism.

VCC VCC
VCC = 12 V
14 Dx 16 Dx
+ 12 V + 12 V
ANALOG I/O ANALOG O/I
ON ON
0V 0V
Dx Dx

SELECTED SELECTED
VCC
CONTROL CONTROL
OTHER CONTROL OTHER CONTROL
INPUT INPUT
INPUTS INPUTS
7 (VCC OR GND) 7 (VCC OR GND)

Figure 16. 12 V Application Figure 17. Transient Suppressor Application

MOTOROLA 8 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC4066

+5 V +5 V

ANALOG 14 ANALOG ANALOG 14 ANALOG

SIGNALS SIGNALS SIGNALS SIGNALS

R* R* R* R* HC4016 HCT HC4016

LSTTL/ LSTTL/ BUFFER
NMOS 5 NMOS 5
6 CONTROL 6 CONTROL
14 INPUTS 14 INPUTS
15 15
7 7
R* = 2 TO 10 kΩ

a. Using Pull-Up Resistors b. Using HCT Buffer

Figure 18. LSTTL/NMOS to HCMOS Interface

VDD = 5 V VCC = 5 TO 12 V

13 1 16 ANALOG 14 ANALOG
3 SIGNALS SIGNALS
5 HC4016
7 MC14504 2 5
9 4 6 CONTROL
11 6 14 INPUTS
14 8 10 15 7

Figure 19. TTL/NMOS–to–CMOS Level Converter

Analog Signal Peak–to–Peak Greater than 5 V
(Also see HC4316)

1 OF 4
CHANNEL 4
SWITCHES

1 OF 4
CHANNEL 3
SWITCHES
COMMON I/O
1 OF 4
CHANNEL 2
SWITCHES

–
1 OF 4 OUTPUT
CHANNEL 1 1 OF 4
SWITCHES INPUT + LF356 OR
SWITCHES
EQUIVALENT
0.01 µF
1 2 3 4
CONTROL INPUTS

Figure 20. 4–Input Multiplexer Figure 21. Sample/Hold Amplifier

High–Speed CMOS Logic Data 9 MOTOROLA

DL129 — Rev 6
MC54/74HC4066

OUTLINE DIMENSIONS

J SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y

-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
14 8 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
-B- 3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
1 7 4. DIMESNION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
C L BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
C 0.155 0.200 3.94 5.08
-T-
SEATING K D 0.015 0.020 0.39 0.50
PLANE F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
F G N M J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
D 14 PL J 14 PL L 0.300 BSC 7.62 BSC
M 0° 15° 0° 15°
0.25 (0.010) M T A S 0.25 (0.010) M T B S
N 0.020 0.040 0.51 1.01

N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
14 8 MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
1 7 FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J J 0.008 0.015 0.20 0.38
N K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
SEATING
PLANE K M 0_ 10_ 0_ 10_
H G D M N 0.015 0.039 0.39 1.01

MOTOROLA 10 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC4066

OUTLINE DIMENSIONS

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
14 8 MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
–B– P 7 PL PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G MILLIMETERS INCHES
R X 45° F
DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
SEATING K M J F 0.40 1.25 0.016 0.049
PLANE
D 14 PL G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S
K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O

14X K REF NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
0.10 (0.004) M T U S V S Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
N (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE INTERLEAD
2X L/2 FLASH OR PROTRUSION. INTERLEAD FLASH OR
M PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
–U– N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
IDENT. F EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
7

ÉÉÉ
ÇÇÇ
1 DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED

ÇÇÇ
ÉÉÉ
AT DATUM PLANE –W–.
0.15 (0.006) T U S
A K

ÇÇÇ
ÉÉÉ
MILLIMETERS INCHES
–V– K1 DIM MIN MAX MIN MAX

ÇÇÇ
ÉÉÉ
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
J J1 C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N–N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C –W– K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
–T– SEATING D G H DETAIL E
PLANE

High–Speed CMOS Logic Data 11 MOTOROLA

DL129 — Rev 6
MC54/74HC4066

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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*MC54/74HC4066/D*
◊ CODELINE MC54/74HC4066/D
MOTOROLA 12 High–Speed CMOS Logic Data
DL129 — Rev 6
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