1

A Binary-To-Thermometer Decoder with

redundant switching sequences
Georgi I. Radulov, Student Member IEEE, Patrick Quinn, Member IEEE,
Hans A. Hegt, Senior Member IEEE, Arthur H.M. van Roermund, Senior Member IEEE

coding has an inherent redundancy.

Abstract— This paper presents a practical realization of a 3 2 1 ← weight → 1 1 1 1 1 1 1

binary-to-thermometer decoder with redundant output switching 0 0 0 0 0 0 0 0 0 0

   
sequences. Its particular application is to decode the DAC 0 0 1 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 1
segmented MSB part. In the presented realization, 4 MSB binary    
0

1 1

decoder
→ 
0 0 0 0 1 1 1

(1)
bits are decoded to 15 thermometer bits through 2 different 1 0 0 3b →7th 0 0 0 1 1 1 1
thermometer switching sequences. The end-user can choose the 1 0 1 0 0 1 1 1 1 1
   
decoding switching sequence, according to the distribution of the 1 1 0 0 1 1 1 1 1 1
1 1 1  1 1 1 1 1 1 1 
mismatch errors of the DAC signal current sources. Therefore,  binary  thermometer
the chip yield Yield INL , which is defined as the percentage of Theoretically, the thermometer coding redundancy means
DAC samples that meet some specifications, is expected to that the input digital codes can be equivalently represented by
improve by more than 12% for barriers Yield INL > 95% . The more than one combination of bits. For example, code 1 can be
presented realization proves the efficiency of this approach based represented by 7 different combinations, e.g. 0000001,
on two main considerations: area and power consumption. The 0000010…, etc. Notable exceptions are codes 0 and full-scale,
silicon area of the decoder is increased by only 50%, while for the where only a single bit combination exists.
whole DAC area, this increase is under 3%. On the other hand,
the power consumption of the decoder is doubled but it is still
In practice, these coding matrices control the switching of
under 0.5% of the entire DAC power consumption. These results the DAC analog signal currents (analog entities, in general).
prove not only the efficiency of the presented particular Therefore, the weights of (1) should be modified by adding the
realization but also the high efficiency of the redundant switching current mismatch (2):
sequences for the DAC MSB thermometer current sources. The b3 b2 b1 ← weight → t7 t6 t5 t4 t3 t2 t1
article concludes with general discussion and further possible 0 0 0 0 0 0 0 0 0 0
   
enhancement of the new decoder and the presented realization. 0 0 1 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 1
   
Index Terms— Binary-to-thermometer decoder, current-
0

1 1

decoder
→ 
0 0 0 0 1 1 1

(2)
1 0 0 3b →7th 0 0 0 1 1 1 1
steering DACs, flexibility, redundancy. 1 0 1 0 0 1 1 1 1 1
   
1 1 0 0 1 1 1 1 1 1
1 1 1  1 1 1 1 1 1 1 
I. INTRODUCTION  binary  thermometer

According to (2), every thermometer code combination

B INARY-to-thermometer decoders are used in the
segmented and fully thermometer digital-to-analog
converters. Their main function is to convert the binary coded
generates in reality a different analog output, because of the
particular mismatch errors of the current sources. Thus, codes
input digital word into a thermometer coded digital word. A 0000001 and 0000010 generate different output analog current
short example of 3 binary to 7 thermometer decoder as a with mismatch errors respectively t1 and t2 for the same input
conversion matrix is given by (1). The columns of the binary digital number. In practice, it is not possible to predict the
decoder are weighted with the powers of 2, while all the current mismatch errors and hence the exact weights tk .
columns of the thermometer decoder have the same weight.
Rather, the mismatch errors can be measured after the chip is
The binary coding has higher efficiency. The thermometer
manufactured. This knowledge allows determining which
thermometer code combination (called also switching
Manuscript received September 1, 2006. This work was supported by the sequence) combines so the mismatch errors that they cancel
Dutch Technical Foundation STW, ECS.6098. each other and produce DAC analog output with the smallest
Georgi I. Radulov is a PhD student at the Department of Electrical possible mismatch error. Such a best case scenario requires a
Engineering of the Eindhoven University of Technology (TU/e), EH5.15,
P.O. Box 513, 5600MB Eindhoven, the Netherlands, tel: +31 40 247 3242, e- hardware realization of the binary-to-thermometer decoder that
mail: g.radulov@tue.nl. can realize all possible switching sequences. In principle, the
Patrick J. Quinn is an senior design manager at the Xilinx Ireland. hardware costs would be huge. However, note that such
Johannes A. Hegt is an Associate Professor at the Department of Electrical
Engineering of TU/e, e-mail: j.a.hegt@tue.nl. implementations exist [1].
Arthur H.M. van Roermund is a Full Professor at the Department of Instead of realizing all possible switching sequences and
Electrical Engineering of TU/e, e-mail: a.h.m.v.roermund@tue.nl.

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paying the big hardware price, this paper suggests to realize LSB/MSB BINARY IN MSB/LSB
only a few switching sequences. The increase in the hardware
... 1st level of ...
is very small, while the rate of DAC linearity improvement is decoding
high. For example, if two switching sequences are compared to X/Xa DECODER
the usual only one, then the number of possible error Xaj Xj Xaj+1 Xj+1

distributions is doubled. However, if another switching

sequence is added, then the number of possible distributions is

Y/Ya DECODER
again increased but only by half. Thus, for every extra Array of
switching sequence, the rate of improvement decreases.
Therefore, it makes greater sense to implement a few possible identical

...
Yj
switching sequences, instead of implementing all the Ya
Yj+1
j

decoding cells
possibilities for the price of a huge hardware investment. The Yaj+1
theoretical framework of these approaches is elaborated in [1]
and [2]. It is shown that a decoder with more than one
(Xj+Yai+1)*(Xaj+1+Yi)
switching sequence can improve DAC yield. Xj
Yai+1
For the industry, the yield is among the most important Xaj+1
figures. Poor yield makes the manufactured chips more Yi
2nd level of THERMO OUT
decoding
expensive, because the production costs for the “bad” devices
must be calculated in the price of the “good” devices. Figure 1 - A decoder with two built-in switching sequences.
Production tolerances, which can result in random mismatch
and gradient errors, are among the main reasons for lower To select the switching sequence, extra control signals
yields. For DACs, yield is primarily defined by static need to be embedded in the first decoding level. These signals
performance, which is the percentage of devices that meet control the second decoding level and set the chosen switching
some pre-defined INLmax specifications. The random sequence. The logic equations of the second decoding level
are:
mismatch of the analog elements is a main error contributor to
DAC INL, providing that any systematic and gradient errors
are minimized through careful layout. The INL errors depend Tij = ( X j + Yai +1 ) ⋅ ( Xa j +1 + Yi ),
on both the element mismatch errors and their distribution.
 Mode 1: Ya = Y , Xa = 0; (3)
This paper shows that redundancy in the binary-to- with 
thermometer decoder can relax the DAC mismatch  Mode 2 : Ya = 0, Xa = X .
requirements with respect to yield. The improvement is
achieved for little additional resources. It may not offer a lot of The information for the mode of operation is provided by
switching sequences, but statistically it pays back with the Xa and Ya decoders. In Mode 1, all thermo Ya signals are
equal to Y signals, and all thermo Xa signals are zero. The
substantial yield improvement for the whole D/A Converter.
symmetrical decoder operates as a Row-Column Decoder with
The latter makes the proposed solution much more area and Xj being Cj and Yi being Ri. In Mode 2, all thermo Ya signals
power efficient. The proposed solution improves chip yield are zero and all thermo Xa signals are equal to X. The
and DAC static linearity. It does not deteriorate in any way the symmetrical decoder operates as a Column-Row Decoder with
dynamic DAC performance. Xj being Ri and Yi being Cj. Figure 2 shows how the
Section II presents the proposed decoder architecture with 2 symmetrical ORORAND gate is transformed to an ORAND
built-in switching sequences. Section III presents a practical gate with different connectivity in the two modes of operation.
realization and simulation results. Finally, conclusions are (Xj+Yai+1)*(Xaj+1+Yi)
drawn. Xj
Yai+1
MODE 1 Xaj+1 MODE 2
Yi
(Xj+Yi+1)*Yi Xj*(Xj+1+Yi)
II. DECODER WITH REDUNDANCY
Xj
The conceptual diagram of a binary-to-thermometer Yi+1 Xj
decoder with two switching sequences is shown in figure 1. Yi
Xj+1
For the second decoding level, instead of the usual ORAND Yi
gate, an ORORAND decoding cell is used. ORORAND gate
has inputs that are balanced between the decoder rows and Figure 2 – A functional view of the 2nd level decoding in mode 1 and 2.
columns. Symmetrical decoding cells allow two operation
As discussed, mode 1 and mode 2 generate different
modes, i.e. two switching sequences instead of only one.
thermometer switching sequences. Figure 3 shows a
geometrical example of the two switching sequences for a 4-
to-15 binary-to-thermometer decoder. These switching
sequences are realized in practice. Note how in mode 1 the

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thermometer code develops horizontally, while in mode 2 the 100

Chip Yield of Mode 1, Mode 2, and the Flexible decoder, 12b op−mode

thermometer code develops vertically.

90

1 2 3 4 8 12 4 80
5 6 7 8 5 9 13 1
a) b) 70
9 10 11 12 6 10 14 2

Good chips [%]

60
13 14 15 7 11 15 3
50

Figure 3 - Switching sequences: a) for mode 1; b) for mode 2. 40

30

20
III. PRACTICAL REALIZATION 10

The redundant binary-to-thermometer decoder is 0

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
implemented in a flexible current-steering DAC based on 4 Sigma/I [%]

parallel 12b sub-DACs. The architecture of the DAC is similar

Figure 6 - DAC Yield INL against the currents matching for 12b op-mode.
to the basic DAC architecture used in [3, 4], see figure 4. Each
of the 12b sub-DACs is segmented to 8b LSB binary part and
Statistically, the two switching sequences produce the same
4b MSB thermometer part (15 thermometer currents).
results. However, if the better switching sequence is always
w1(nT) Iout1(t) chosen for a given DAC sample, then the DAC yield can be
12b sub-DAC
significantly improved. For the basic 12b sub-DAC, the yield
improvement can reach up to 20% for moderate yield barriers
w2(nT)
12b sub-DAC
Iout2(t) For the 13b mode of operation, when two 12b sub-DACs
FPGA
w(nT) Iout(t) work in parallel to produce 13b resolution, the improvement is
or
even greater. The possible switching sequences from the basic
pre-processor w3(nT) Iout3(t)
12b sub-DAC 2 types are now 8 (each sub-DAC has 2 possible switching
sequences and can work either on the LSB or on MSB part of
w4(nT) Iout4(t)
the 13b transfer characteristic). Figure 7 shows the DAC INL
12b sub-DAC
yield for a 13b op-mode. Statistically, the two switching
sequences produce the same results. However, if the better
Figure 4 – Flexible 14b DAC architecture based on 4 parallel 12b sub-DACs. switching sequence is always chosen for a given DAC sample,
then the DAC yield can be significantly improved. The yield
The sub-DACs thermometer currents are controlled by a
improvement can reach up to 30% for moderate yield barriers.
redundant binary-to-thermometer decoder. Its whole Chip Yield of Mode 1, Mode 2, and the Flexible decoder, 13b op−mode
implementation consists of 4 instances of 4-to-15 binary-to- 100

thermometer decoders with 2 switching sequences for each. 90

The two switching sequences generate two different INL DAC 80

characteristics, as shown in figure 5 for a single 12b sub-DAC. 70

Good chips [%]

INL 60

50
0.5

0.4 40

0.3 30
INLmax for mode 1
0.2
20
0.1
10
LSB

−0.1 0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Sigma/I [%]
−0.2

−0.3

−0.4
Figure 7 - DAC Yield INL against the currents matching for 13b op-mode.
INLmax for mode 2
−0.5
The decoder is realized in CML logic to operate at speeds of
0 500 1000 1500 2000 2500 3000 3500 4000
digital input up to 500MS/s. For one instance of the 4-to-15 binary to
Figure 5 – An example of the 2 INL charactertisitcs of a 12b sub-DAC.
thermometer decoder, the first level decoders are each 3 gates,
i.e. 12 all. The second decoding level consists of 16
If for every DAC sample the better INL characteristic is ORORAND gates and 15 buffers and 1 OR gate that combines
chosen out of the two possible, then an improvement in the the 3rd thermo bit with the missing 16th bit, see figure 3. The
DAC Yield INL can be achieved. Figure 6 shows the DAC INL overall current consumption is 1.2mA per decoder instance
yield for a 12b sub-DAC with the proposed decoder. (30µA per gate). The increase of the power consumption with
respect to the usual implementation is about 50%. The layout

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implementation of one instance of the decoder is shown in ACKNOWLEDGMENT

Figure 7. The silicon area of the decoder is increased by only The authors would like to acknowledge the Dutch
50%, while for the whole DAC area, this increase is under 3%, technology Foundation STW for the financial support of the
see figure 9. On the other hand, the power consumption of the project ECS.6098.
decoder is doubled but it is still under 0.5% of the entire DAC
power consumption REFERENCES
[1] Chen, T.; Geens, P.; Van der Plas, G.; Dehaene, W.; Gielen, G.; “A 14-
0.04mm X/Xa/Y/Ya decoder bit 130-MHz CMOS current-steering DAC with adjustable INL”, Solid-
0.17mm State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the
30th European 21-23 Sept. 2004 Page(s):167 – 170
ORORAND gates [2] Radulov, G.L.; Quinn, P.J.; van Beek, P.C.W.; Hegt, J.A.; van
Roermund, A.H.M.;“A binary-to-thermometer decoder with built-in
Buffer redundancy for improved DAC yield”, Circuits and Systems, 2006.
s ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 21-
Figure 8 – The layout implementation of one instance of the decoder. 24 May 2006 Page(s):4 pp.
[3] R.A.T. van den Hoven, G.I. Radulov, J.A.Hegt, A. van Roermund, “A
The full layout of the 14b flexible DAC chip is shown in parallel current-steering DAC architecture for flexible and improved
figure 8. The area of the binary-to-thermometer decoder is performance”, ProRISC 2005, Veldhoven 17-18 Nov. 2005.
[4] Radulov, G.L.; Quinn, P.J.; Harpe, P.; Hegt, J.A.; van Roermund,
around 3% of the whole chip area. A.H.M.; “Parallel current-steering D/A Converters for Flexibility and
Smartness”, submitted to 2007 IEEE International Symposium on
Circuits and Systems, 2007. ISCAS 2007.

4 x binary-to-thermo decoder
Sub-DAC 1 Sub-DAC 2 Sub-DAC 3 Sub-DAC 4

0.8mm

1 mm

Figure 9 - 14b flexible DAC based on 4 parallel 12b sub-DACs

IV. CONCLUSION
A new flexible binary-to-thermometer decoder for
segmented D/A Converters was presented. Instead of the
conventional only one thermometer switching sequence, the
proposed decoder can generate two different switching
sequences. Such a built-in redundancy affects the whole DAC
by allowing two different INL characteristics. A practical
realization of a 4-to-15 bit binary-to-thermometer decoder in a
14b flexible DAC based on 4 parallel 12bit sub-DACs has two
switching sequences for 12b op-mode, 8 switching sequences
for a 13b op-mode, and 32 switching sequences for 14b op-
mode. Simulations show that the improvement of the chip
yield can reach up to 20% for 12b op-mode and up to 30% for
the 13b op-mode. As concluded from the layout realization,
the improvement is achieved for little redundant hardware
resources, which makes the proposed decoder architecture
very area and power efficient. Ultimately, the proposed
decoder may lead to an improved chip yield and hence to
reduced price of the segmented D/A Converters of all types:
resistor based, switched capacitors, or current-steering type.

333