NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM

November 1993

NMC27C64
65,536-Bit (8192 x 8) CMOS EPROM
General Description Features
The NMC27C64 is a 64K UV erasable, electrically repro- Y High performance CMOS
grammable and one-time programmable (OTP) CMOS Ð 150 ns access time
EPROM ideally suited for applications where fast turn- Y JEDEC standard pin configuration
around, pattern experimentation and low power consump- Ð 28-pin DIP package
tion are important requirements. Ð 32-pin chip carrier
The NMC27C64 is designed to operate with a single a 5V Y Drop-in replacement for 27C64 or 2764
power supply with g 10% tolerance. The CMOS design al- Y Manufacturers identification code
lows the part to operate over extended and military temper-
ature ranges.
The NMC27C64Q is packaged in a 28-pin dual-in-line pack-
age with a quartz window. The quartz window allows the
user to expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written electrically into
the device by following the programming procedure.
The NMC27C64N is packaged in a 28-pin dual-in-line plastic
molded package without a transparent lid. This part is ideal-
ly suited for high volume production applications where cost
is an important factor and programming only needs to be
one once.
This family of EPROMs are fabricated with National’s propri-
etary, time proven CMOS double-poly silicon gate technolo-
gy which combines high performance and high density with
low power consumption and excellent reliability.

Block Diagram

Pin Names
A0 – A12 Addresses
CE Chip Enable
OE Output Enable
O0 –O7 Outputs
PGM Program
NC No Connect
VPP Programming
Voltage
VCC Power Supply
GND Ground
TL/D/8634 – 1

TRI-STATEÉ is a registered trademark of National Semiconductor Corp.

NSC800TM is a trademark of National Semiconductor Corp.

C1996 National Semiconductor Corporation TL/D/8634 RRD-B30M17/Printed in U. S. A. http://www.national.com

 Connection Diagram

27C512 27C256 27C128 27C32 27C16 NMC27C64Q/N 27C16 27C32 27C128 27C256 27C512
27512 27256 27128 2732 2716 Dual-In-Line Package 2716 2732 27128 27256 27512

A15 VPP VPP VCC VCC VCC

A12 A12 A12 PGM A14 A14
A7 A7 A7 A7 A7 VCC VCC A13 A13 A13
A6 A6 A6 A6 A6 A8 A8 A8 A8 A8
A5 A5 A5 A5 A5 A9 A9 A9 A9 A9
A4 A4 A4 A4 A4 VPP A11 A11 A11 A11
A3 A3 A3 A3 A3 OE OE/VPP OE OE OE/VPP
A2 A2 A2 A2 A2 A10 A10 A10 A10 A10
A1 A1 A1 A1 A1 CE/PGM CE CE CE/PGM CE
A0 A0 A0 A0 A0 O7 O7 O7 O7 O7
O0 O0 O0 O0 O0 O6 O6 O6 O6 O6
O1 O1 O1 O1 O1 O5 O5 O5 O5 O5
O2 O2 O2 O2 O2 O4 O4 O4 O4 O4
GND GND GND GND GND O3 O3 O3 O3 O3
TL/D/8634 – 2
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C64 pins.

Commercial Temperature Range

VCC e 5V g 10%

Parameter/Order Number Access Time (ns)

NMC27C64Q, N150 150
NMC27C64Q, N200 200
NMC27C64Q, N250 250

Extended Temp Range (b40§ C to a 85§ C)

VCC e 5V g 10%

Parameter/Order Number Access Time (ns)

NMC27C64QE150 150
NMC27C64QE200 200

Military Temp Range (b55§ C to a 125§ C)

VCC e 5V g 10%

Parameter/Order Number Access Time (ns)

NMC27C64QM200 200
NMC27C64QM250 250

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 Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, VCC Supply Voltage with
please contact the National Semiconductor Sales Respect to Ground a 7.0V to b 0.6V
Office/Distributors for availability and specifications. Power Dissipation 1.0W
Temperature Under Bias b 55§ C to a 125§ C Lead Temperature (Soldering, 10 sec.) 300§ C
Storage Temperature b 65§ C to a 150§ C ESD Rating
All Input Voltages except A9 with (Mil Spec 883C, Method 3015.2) 2000V
Respect to Ground (Note 10) a 6.5V to b 0.6V
All Output Voltages with Operating Conditions (Note 7)
Respect to Ground (Note 10) VCC a 1.0V to GNDb0.6V Temperature Range
VPP Supply Voltage and A9 NMC27C64Q150, 200, 250 0§ C to a 70§ C
with Respect to Ground NMC27C64N150, 200, 250
During Programming a 14.0V to b 0.6V NMC27C64QE150, 200 b 40§ C to a 85§ C
NMC27C64QM200, M250 b 55§ C to a 125§ C
VCC Power Supply a 5V g 10%

READ OPERATION
DC Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
ILI Input Load Current VIN e VCC or GND 10 mA
ILO Output Leakage Current VOUT e VCC or GND, CE e VIH 10 mA
ICC1 VCC Current (Active) CE e VIL, f e 5 MHz
5 20 mA
(Note 9) TTL Inputs Inputs e VIH or VIL, I/O e 0 mA
ICC2 VCC Current (Active) CE e GND, f e 5 MHz
3 10 mA
(Note 9) CMOS Inputs Inputs e VCC or GND, I/O e 0 mA
ICCSB1 VCC Current (Standby) CE e VIH
0.1 1 mA
TTL Inputs
ICCSB2 VCC Current (Standby) CE e VCC
0.5 100 mA
CMOS Inputs
IPP VPP Load Current VPP e VCC 10 mA
VIL Input Low Voltage b 0.1 0.8 V
VIH Input High Voltage 2.0 VCC a 1 V
VOL1 Output Low Voltage IOL e 2.1 mA 0.45 V
VOH1 Output High Voltage IOH e b400 mA 2.4 V
VOL2 Output Low Voltage IOL e 0 mA 0.1 V
VOH2 Output High Voltage IOH e 0 mA VCC b 0.1 V

AC Electrical Characteristics
NMC27C64Q/N
Symbol Parameter Conditions 150, E150 200, E200, M200 250, M250 Units
Min Max Min Max Min Max
tACC Address to Output Delay CE e OE e VIL
150 200 250 ns
PGM e VIH
tCE CE to Output Delay OE e VIL, PGM e VIH 150 200 250 ns
tOE OE to Output Delay CE e VIL, PGM e VIH 60 60 70 ns
tDF OE High to Output Float CE e VIL, PGM e VIH 0 60 0 60 0 60 ns
tCF CE High to Output Float OE e VIL, PGM e VIH 0 60 0 60 0 60 ns
tOH Output Hold from Addresses, CE e OE e VIL
CE or OE, Whichever PGM e VIH 0 0 0 ns
Occurred First

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 Capacitance TA e a 25§ C, f e 1 MHz (Note 2) NMC27C64Q
Symbol Parameter Conditions Typ Max Units
CIN Input Capacitance VIN e 0V 6 8 pF
COUT Output Capacitance VOUT e 0V 9 12 pF

Capacitance TA e a 25§ C, f e 1 MHz (Note 2) NMC27C64N

Symbol Parameter Conditions Typ Max Units
CIN Input Capacitance VIN e 0V 5 10 pF
COUT Output Capacitance VOUT e 0V 8 10 pF

AC Test Conditions
Output Load 1 TTL Gate and Timing Measurement Reference Level
CL e 100 pF (Note 8) Inputs 0.8V and 2V
Input Rise and Fall Times s 5 ns Outputs 0.8V and 2V
Input Pulse Levels 0.45V to 2.4V

AC Waveforms (Notes 6 & 9)

TL/D/8634 – 3
Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tACC b tOE after the falling edge of CE without impacting tACC.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE, the measured VOH1 (DC) b 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) a 0.10V.
Note 5: TRI-STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 mF ceramic capacitor be used on
every device between VCC and GND.
Note 7: The outputs must be restricted to VCC a 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL e 1.6 mA, IOH e b 400 mA.
CL: 100 pF includes fixture capacitance.
Note 9: VPP may be connected to VCC except during programming.
Note 10: Inputs and outputs can undershoot to b 2.0V for 20 ns Max.

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Programming Characteristics (Notes 1, 2, 3 & 4)
Symbol Parameter Conditions Min Typ Max Units
tAS Address Setup Time 2 ms
tOES OE Setup Time 2 ms
tCES CE Setup Time 2 ms
tDS Data Setup Time 2 ms
tVPS VPP Setup Time 2 ms
tVCS VCC Setup Time 2 ms
tAH Address Hold Time 0 ms
tDH Data Hold Time 2 ms
tDF Output Enable to Output Float Delay CE e VIL 0 130 ns
tPW Program Pulse Width 0.45 0.5 0.55 ms
tOE Data Valid from OE CE e VIL 150 ns
IPP VPP Supply Current During CE e VIL
30 mA
Programming Pulse PGM e VIL
ICC VCC Supply Current 10 mA
TA Temperature Ambient 20 25 30 §C
VCC Power Supply Voltage 5.75 6.0 6.25 V
VPP Programming Supply Voltage 12.2 13.0 13.3 V
tFR Input Rise, Fall Time 5 ns
VIL Input Low Voltage 0.0 0.45 V
VIH Input High Voltage 2.4 4.0 V
tIN Input Timing Reference Voltage 0.8 1.5 2.0 V
tOUT Output Timing Reference Voltage 0.8 1.5 2.0 V

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 Programming Waveforms (Note 3)

TL/D/8634 – 6
Note 1: National’s standard product warranty applies to devices programmed to specifications described herein.
Note 2: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a
board with voltage applied to VPP or VCC.
Note 3: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 mF capacitor is required across VPP, VCC to GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the interactive Program Algorithm, at typical power supply voltages and timings.

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Interactive Programming Algorithm Flow Chart

TL/D/8634 – 5

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 Functional Description
DEVICE OPERATION To most efficiently use these two control lines, it is recom-
mended that CE (pin 20) be decoded and used as the pri-
The six modes of operation of the NMC27C64 are listed in
mary device selecting function, while OE (pin 22) be made a
Table I. It should be noted that all inputs for the six modes
common connection to all devices in the array and connect-
are at TTL levels. The power supplies required are VCC and
ed to the READ line from the system control bus. This as-
VPP. The VPP power supply must be at 13.0V during the
sures that all deselected memory devices are in their low
three programming modes, and must be at 5V in the other
power standby modes and that the output pins are active
three modes. The VCC power supply must be at 6V during
only when data is desired from a particular memory device.
the three programming modes, and at 5V in the other three
modes. Programming
Read Mode CAUTION: Exceeding 14V on pin 1 (VPP) will damage the
NMC27C64.
The NMC27C64 has two control functions, both of which
must be logically active in order to obtain data at the out- Initially, all bits of the NMC27C64 are in the ‘‘1’’ state. Data
puts. Chip Enable (CE) is the power control and should be is introduced by selectively programming ‘‘0s’’ into the de-
used for device selection. Output Enable (OE) is the output sired bit locations. Although only ‘‘0s’’ will be programmed,
control and should be used to gate data to the output pins, both ‘‘1s’’ and ‘‘0s’’ can be presented in the data word. A
independent of device selection. The programming pin ‘‘0’’ cannot be changed to a ‘‘1’’ once the bit has been
(PGM) should be at VIH except during programming. Assum- programmed.
ing that addresses are stable, address access time (tACC) is The NMC27C64 is in the programming mode when the VPP
equal to the delay from CE to output (tCE). Data is available power supply is at 13.0V and OE is at VIH. It is required that
at the outputs tOE after the falling edge of OE, assuming at least a 0.1 mF capacitor be placed across VPP, VCC to
that CE has been low and addresses have been stable for ground to suppress spurious voltage transients which may
at least tACC – tOE. damage the device. The data to be programmed is applied 8
The sense amps are clocked for fast access time. VCC bits in parallel to the data output pins. The levels required
should therefore be maintained at operating voltage during for the address and data inputs are TTL.
read and verify. If VCC temporarily drops below the spec. For programming, CE should be kept TTL low at all times
voltage (but not to ground) an address transition must be while VPP is kept at 13.0V.
performed after the drop to insure proper output data. When the address and data are stable, an active low, TTL
Standby Mode program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be pro-
The NMC27C64 has a standby mode which reduces the
grammed. The NMC27C64 is designed to be programmed
active power dissipation by 99%, from 55 mW to 0.55 mW.
with interactive programming, where each address is pro-
The NMC27C64 is placed in the standby mode by applying
grammed with a series of 0.5 ms pulses until it verifies (up to
a CMOS high signal to the CE input. When in standby mode,
a maximum of 20 pulses or 10 ms). The NMC27C64 must
the outputs are in a high impedance state, independent of not be programmed with a DC signal applied to the PGM
the OE input.
input.
Output OR-Tying Programming multiple NMC27C64s in parallel with the same
Because NMC27C64s are usually used in larger memory data can be easily accomplished due to the simplicity of the
arrays, National has provided a 2-line control function that programming requirements. Like inputs of the paralleled
accommodates this use of multiple memory connections. NMC27C64s may be connected together when they are
The 2-line control function allows for: programmed with the same data. A low level TTL pulse ap-
a) the lowest possible memory power dissipation, and plied to the PGM input programs the paralleled
NMC27C64s. If an application requires erasing and repro-
b) complete assurance that output bus contention will not
gramming, the NMC27C64Q UV erasable PROM in a win-
occur.
dowed package should be used.

TABLE I. Mode Selection

Pins CE OE PGM VPP VCC Outputs
Mode (20) (22) (27) (1) (28) (11 – 13, 15 – 19)
Read VIL VIL VIH 5V 5V DOUT
Standby VIH Don’t Care Don’t Care 5V 5V Hi-Z
Output Disable Don’t Care VIH VIH 5V 5V Hi-Z
Program VIL VIH 13V 6V DIN
Program Verify VIL VIL VIH 13V 6V DOUT
Program Inhibit VIH Don’t Care Don’t Care 13V 6V Hi-Z

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Functional Description (Continued)
Program Inhibit The recommended erasure procedure for the NMC27C64 is
Programming multiple NMC27C64s in parallel with different exposure to short wave ultraviolet light which has a wave-
data is also easily accomplished. Except for CE all like in- length of 2537 Angstroms (Ð). The integrated dose (i.e., UV
puts (including OE and PGM) of the parallel NMC27C64 intensity x exposure time) for erasure should be a minimum
may be common. A TTL low level program pulse applied to of 15W-sec/cm2.
an NMC27C64’s PGM input with CE at VIL and VPP at 13.0V The NMC27C64 should be placed within 1 inch of the lamp
will program that NMC27C64. A TTL high level CE input tubes during erasure. Some lamps have a filter on their
inhibits the other NMC27C64s from being programmed. tubes which should be removed before erasure. Table III
shows the minimum NMC27C64 erasure time for various
Program Verify light intensities.
A verify should be performed on the programmed bits to An erasure system should be calibrated periodically. The
determine whether they were correctly programmed. The distance from lamp to unit should be maintained at one inch.
verify may be performed with VPP at 13.0V. VPP must be at The erasure time increases as the square of the distance. (If
VCC, except during programming and program verify. distance is doubled the erasure time increases by a factor of
MANUFACTURER’S IDENTIFICATION CODE 4.) Lamps lose intensity as they age. When a lamp is
The NMC27C64 has a manufacturer’s identification code to changed, the distance has changed or the lamp has aged,
aid in programming. The code, shown in Table II, is two the system should be checked to make certain full erasure
bytes wide and is stored in a ROM configuration on the chip. is occurring. Incomplete erasure will cause symptoms that
It identifies the manufacturer and the device type. The code can be misleading. Programmers, components, and even
for the NMC27C64 is ‘‘8FC2’’, where ‘‘8F’’ designates that it system designs have been erroneously suspected when in-
is made by National Semiconductor, and ‘‘C2’’ designates a complete erasure was the problem.
64k part. SYSTEM CONSIDERATION
The code is accessed by applying 12V g 0.5V to address The power switching characteristics of EPROMs require
pin A9. Addresses A1–A8, A10–A12, CE, and OE are held careful decoupling of the devices. The supply current, ICC,
at VIL. Address A0 is held at VIL for the manufacturer’s has three segments that are of interest to the system de-
code, and at VIH for the device code. The code is read out signerÐthe standby current level, the active current level,
on the 8 data pins. Proper code access is only guaranteed and the transient current peaks that are produced by volt-
at 25§ C g 5§ C. age transitions on input pins. The magnitude of these tran-
The primary purpose of the manufacturer’s identification sient current peaks is dependent on the output capacitance
code is automatic programming control. When the device is loading of the device. The associated VCC transient voltage
inserted in a EPROM programmer socket, the programmer peaks can be suppressed by properly selected decoupling
reads the code and then automatically calls up the specific capacitors. It is recommended that at least a 0.1 mF ceramic
programming algorithm for the part. This automatic pro- capacitor be used on every device between VCC and GND.
gramming control is only possible with programmers which This should be a high frequency capacitor of low inherent
have the capability of reading the code. inductance. In addition, at least a 4.7 mF bulk electrolytic
capacitor should be used between VCC and GND for each
ERASURE CHARACTERISTICS
eight devices. The bulk capacitor should be located near
The erasure characteristics of the NMC27C64 are such that where the power supply is connected to the array. The pur-
erasure begins to occur when exposed to light with wave- pose of the bulk capacitor is to overcome the voltage drop
lengths shorter than approximately 4000 Angstroms (Ð). It caused by the inductive effects of the PC board traces.
should be noted that sunlight and certain types of fluores-
cent lamps have wavelengths in the 3000Ж4000Рrange.
After programming, opaque labels should be placed over
the NMC27C64’s window to prevent unintentional erasure.
Covering the window will also prevent temporary functional
failure due to the generation of photo currents.

TABLE II. Manufacturer’s Identification Code

A0 O7 O6 O5 O4 O3 O2 O1 O0 Hex
Pins
(10) (19) (18) (17) (16) (15) (13) (12) (11) Data
Manufacturer Code VIL 1 0 0 0 1 1 1 1 8F
Device Code VIH 1 1 0 0 0 0 1 0 C2

TABLE III. Minimum NMC27C64 Erasure Time

Light Intensity Erasure Time
(Micro-Watts/cm2) (Minutes)
15,000 20
10,000 25
5,000 50

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NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted

Dual-In-Line Package (Q)

Order Number NMC27C64Q
NS Package Number J28AQ

Dual-In-Line Package (N)

Order Number NMC27C64N
NS Package Number N28B

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

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failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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