Pd evaluation test
1. In a test minimum passing percentage for girls and boys is 35% and 40% respectively. A boy scored 483 marks
and failed by 117 marks. What are the minimum passing marks for girls?
(A) 425 (B) 525 (C) 500 (D) 450
2. If a number is increased by 12% and then decreased by 18%, then find the net % change in the number.
(A) 8.16% decrease (B) 8.42 % increase (C) 8.44% decrease (D) 8.18% increase
3.A man buys 5 horses and 7 bulls for Rs 1950 he sells the horses at a profit of 10%and bulls at a profit of 16% and
on the whole his gain is Rs 237 what price does he pay for a horse?
(A) 230 (B) 250 (C) 300 (D) 225
4. The average age of 5 members is 21 years. If the age of the youngest member be 5 years, find the average age of
the family at the birth of the youngest member
(A) 20 years (B) 19 years (C)13 years (D) None of these
5. Three numbers are in the ratio 3: 4: 5 and their L.C.M. is 2400. Their H.C.F. is:
(A) 200 (B) 80 (C) 40 (D) 120
6. A person incurs 5% loss by selling a bat for Rs 1140. At what price should the watch be sold to earn 5% profit?
(A) 1260 (B) 1255 (C) 1270 (D) 1250
7. Why PMOS is connected to VDD and NMOS is connected to ground in CMOS configuration?
8. Design a mod-5 counter which has the following binary sequence: 0, 1, 2, 3, and 4.
9. What is master slave flip flop? Explain with diagram?
10. Build a 4×16 decoder using 2×4 decoder.
11. What is FINFET?
12. What is MOSFET? Explain the region of operation of mosfet?
13. What is Body Effect?
14. Implement AND, OR, NOT, NAND, NOR, XOR, XNOR using 2:1 MUX.
15. Explain briefly about Velocity saturation?
16. Explain how amplification is achieved in BJT using example?
17. The final output of a modulus-8 counter occurs one time for every ________.
18. An invalid digital signal is used as a zero.
A. True
B. False
19. Convert the following binary number to octal 010111100.
20. The two’s-complement system is to be used to add the signed numbers 11110010 and 11110011. Determine, in
decimal, the sign and value of each number and their sum
21. What is the benefit of having separate path groups for I/O logic paths?
22. Applying a weight > 1 to a path group may increase a design’s critical path delay. True or False?
23. What is the difference between a Milky Way design library and reference library? What do they have in
common?
24. What is clock gating and use of clock gating?
25. Antenna violation and reducing techniques?
26. Why we define Generated clock why can’t we use same master clock on place of it.
27. What is signal integrity? How it affects Timing?
28. What is multicycle path explain with example?
29. What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
30. What is Synthesis? What are the types of synthesis?
31. What is difference between normal buffer and clock buffer?
32. How signal integrity impact setup and hold violation?
33. What is ESD?
34. What if hot spot found in some area of block? How you tackle this?
35. What are clock tree types? Explain them?
36. What is virtual clock? How we can say any clock is virtual/ generated/ mastered by looking into sdc. File?
37. Explain mmmc. Which parasitic interconnect corners is checked for setup and hold?
38. What is setup & hold timing? Derive equation to find setup & hold slack with uncertainty and derate?
39. What is zic timing?
40. What happen if we do pg routing after placement?
41. What are all the different components you see in a reg2reg timing report?
42. Can you tape-out the chip with setup & hold violation? Explain with the reason?
43. How to check antenna violations by command wise and how to reduce it in tool?
44. Can a net have negative propagation delay?
45. Is hold always checks on the same edge? Explain with waveforms?
46. What is minimum pulse width? In which file its present? Write commands?
47. What is difference between sdf and spef?
48. Explain the terms
a) RP groups
b) DOUBLE BACK
49. What is an isolation cell? For what purpose we use it?
50. Difference between LEC & LVS?
