E-ISSN 2581 –7957 CVR Journal of Science and Technology, Volume 19, December 2020

P-ISSN 2277 – 3916 DOI: 10.32377/cvrjstxxxx

Design and Implementation of Optimized FIR

Filter using Reversible Logic
E. Janaki Ram1 and S.Swetha 2
1
Student, CVR College of Engineering/ECE Department, Hyderabad, India
Email: swetha.silveri@gmail.com
2
Asst. Professor, CVR College of Engineering/ECE Department, Hyderabad, India
Email: janakiram.emani@gmail.com

Abstract: The Finite Impulse Response (FIR) filter is robust system as long because the system was ready to return to its
and high stable architecture rather than Infinite initial state from its final state no matter what occurred in
Impulse Response (IIR) Filter for DSP applications. In this between.” It made understand that, reversible gate can
paper, a high speed and low power FIR filter is designed
and implemented using Reversible Vedic Multiplier with reduce power dissipation. Also, it minimizes cost &
Reversible Carry Look Ahead adder (RCLA) and Reversible throughput.
Carry Select Adder (RCSLA). The Vedic multiplier Reversible logic supports system running process in both
diminishes the accumulation computation time in the forward and backward. It can generate input from output &
multiplication of filter inputs and coefficients. FIR filter is vice versa. It can stop the process at any stage & go back to
implemented using both normal and pipelined architecture,
any point in computation history. There is one to one
and it is simulated and synthesized. The delay and power
corresponding to these blocks are computed and presented mapping between input and output signals because number
along with utilization summary. The proposed Architecture is of inputs are equal to number of outputs.
implemented using Xilinx Vivado in ZYNQ Zed Board which Hence, there is no requirement of feedback. Equal
can be used for DSP Applications. number of inputs & outputs will minimizes the garbage
outputs and constant inputs which shrinks the heat
Index Terms Carry look ahead Adder, Carry Select Adder,
generation and power loss. This leads to increase in overall
FIR Filters, IIR Filters, Reversible Logic and Vedic Design
circuit performance. The Design Constraints of reversible
I. INTRODUCTION gates like minimum quantum cost, complexity & gate level
makes reversible logic gate more advantageous compared to
Filters play vital role for the removal of unwanted signal conventional logic.
or noise by eliminating the chosen frequencies from
incoming signal. In other words, filter helps to extract the II. REVERSIBLE GATES
specified signal that also contain undesirable or irrelevant
frequencies. FIR filters are widely utilized in different A. INTRODUCTION
applications like biomedical, communication & control due In VLSI parameters like area, speed & power plays an
to their stability & linear phase properties. Compared to essential role as per the current developing technology. In
Infinite Impulse Response (IIR) filters, FIR filters have order to condense the power consumption and energy
simple & regular structures which are easy to implement on leakage, we require reversible logic gates which have equal
hardware. number of inputs & outputs. This unrequired the need of
feedback presence in the circuit. Currently, all digital logic
A digital filter is programmable, i.e. its process is decided
circuits are physically irreversible because they consist of
by a program stored within the processor's memory. An
irreversible gates. The energy provided by the source is
analog filter can only be changed by redesigning the filter
transformed into heat with every bit loss [2].
circuit. Digital filters are easily designed, tested &
implemented on a general purpose computer or workstation. B. COST METRICS OF REVERSIBLE LOGIC GATES:
The features of analog filter circuits are subject to drift & 1. Gate Cost: Gate count refers to number of gates required
are reliant on temperature. Digital filters don't undergo with for circuit which calculate the cost of a circuit, commonly
these difficulties, & extremely stable with reference to both entitled as gate cost (GC).
time & temperature. 2. Quantum Cost: The addition of elementary quantum
An FIR filter is often employed with a series of delays, gates are labelled as quantum cost (QC) of the circuit.
multipliers, & adders to get the filter's output. Functioning 3. Ancilla Input: The supplementary constant inputs to
of FIR Filter is predicated on current & past input values & renovate an irreversible into reversible circuit are denoted as
are the only filters to style. Ancilla inputs (AI).
In CMOS VLSI design, Power optimization are often 4. Input: The number of inputs directly influence on the
done at various abstraction levels. In 1973, C. H. Bennett qubits in a reversible circuit and Circuit size is increased. To
concluded that “no energy would be dissipated from a estimate design methodology performance, number of input
or wires (n) including ancilla input are considered.

CVR College of Engineering

 E-ISSN 2581 –7957 CVR Journal of Science and Technology, Volume 19, December 2020
P-ISSN 2277 – 3916 DOI: 10.32377/cvrjstxxxx

5. Garbage Output: To sustain the bijectivity property in coefficients of the filter.

reversible circuit’s realization, some outputs are left unused
stated as garbage outputs (GO).

The above factors display a direct connection with

circuit’s area/size and complexity. The size and complexity
depends on the values of these parameters and enrich the
power dissipation and physical cost. The quantum cost has a
impartial relation with delay, while ancilla inputs are the
additional source of input power and garbage represents the
power loss [2].
Figure 1 : Reversible FIR Filter
C. TYPES OF REVERSIBLE LOGIC GATES:
The critical path length of direct form FIR filter upturns
Table 1 : Types of Reversible Logic Gates with the increase in filter length. Enhancement in input data
processing rate or throughput can be attained through the
pipelining and parallel processing application. Reduction of
critical path length and progression of throughput at the cost
of increased latency can be succeeded using Pipelining [16].
Hence, Implementation of Pipelined Filters will be more
beneficial than normal filter which can optimize power and
critical path delay along with high throughput [16].
The proposed filter 1 uses carry look ahead adder and
proposed filter 2 uses carry select adder using carry look
ahead adder for all additions [16].

Figure 2 : Pipelined FIR Filter

IV. VEDIC MULTIPLIER & ADDER

In Reversible VM, AND gates and HA are replaced with
BME gate and Peres gate. The first BME gate attains the
sum p0 which is the multiplication of the LSB x0 & y0.
Both the two BME gate attains 2 garbage outputs. One of
III. FIR FILTER
the outputs of both the BME gate are served as inputs to the
An FIR filter is aimed by discovering the coefficients and PERES gate & sum s1, s2 and s3 are achieved [12].
filter order that encounter definite specifications, it can be in
the time domain and/or the frequency domain. Matched
filters implement a cross-correlation among the input signal
and a known pulse shape. The cross-correlation between the
input signal and an impulse response’s time-reversed copy is
termed as FIR Convolution. Therefore, the matched filter’s
impulse response is “designed” by sampling the known
pulse-shape and using those samples in reverse order as the

CVR College of Engineering

 E-ISSN 2581 –7957 CVR Journal of Science and Technology, Volume 19, December 2020
P-ISSN 2277 – 3916 DOI: 10.32377/cvrjstxxxx

Figure 6 : 8-bit Vedic Multiplier

Figure 3 : 2-bit Vedic Multiplier
Carry Look-ahead Adder is the fastest adder compared to
Utilization of BME Gate leads to faster partial product other Adders. It diminishes the propagation delay, which
generation and make the process faster than normal Vedic arises during addition, by consuming more complex
multiplier. hardware circuitry.

Figure 4 : Reversible Vedic Multiplier

Figure 7 : Block Diagram of 4-bit Carry Look ahead Adder

By using Reversible gates i.e., Peres gate for carry

propagate, carry generate & sum and Feynman gate for
carry, Carry Look Ahead Adder is designed for better
performance. Parameters like quantum cost, hardware
complexity and power consumption are enhanced than
Conventional and previous existing designs [10].
By Adding four Feynman gates at input terminal, carry
look ahead adder can also be used as borrow look ahead
subractor [10].

Figure 5 : 4-bit Vedic Multiplier

The operation of above Vedic multiplier is given as follows.

The parallel calculation of partial products will minimize
the delay. Here 4X4 Vedic multipliers will make use of
2X2Vedic multiplier for partial product generation. Three
adders of 4 bits each is utilized for generated partial
products addition.
The carry output of first two Adders are executed by OR
operation and its output is set to next adder. Zero inputs are
prearranged to some adders wherever necessary. The carry
obtained from the first adder is delivered to the next adder
and there are two zero inputs for the adder. The organization
Figure 8 : Reversible Carry Look ahead Adder
of the Adders is shown in above block diagram which can
shrink the computational time such that the delay can be To accomplish arithmetic operations as speed as possible
reduced. The process for 8-bit VM is similar as 4-bit VM then we need Carry Select Adder which is faster than
[7]. remaining existing adders. Also, the CSLA structure ensures
the reduction of area and power.

CVR College of Engineering

 E-ISSN 2581 –7957 CVR Journal of Science and Technology, Volume 19, December 2020
P-ISSN 2277 – 3916 DOI: 10.32377/cvrjstxxxx

In this paper, Carry select Adder was implemented using Table 3 : Pipeline Architecture of Reversible VD-CLA-FIR Filter
Reversible Carry look Ahead Adder, Reversible Multiplexer
using fredkin gate and D-Latch in order to compensate area,
delay and power parameters [9].
The operation of Reversible Carry Select Adder
comprises as follows. In first step, Adder and D-Latch are
operated at same time by using enable signal with values 0
& 1 respectively. In Second step, multiplexer is fed with
outputs of adder and latch as inputs and Carry output of
previous one will acts as select line [8]. Table 4 : Normal Architecture of Reversible VD-CSLA-FIR Filter

Table 5 : Pipeline Architecture of Reversible VD-CSLA-FIR Filter

Figure 9 : Reversible CSLA using D-latch

V. DESIGN ANALYSIS
FIR filter was implemented using Carry look ahead Adder
and Carry Select Adder in both architecture i.e., Normal and
Pipelined. The proposed architectures has been implemented It is confirmed that pipelined FIR Filters had incremented
using Verilog language. Xilinx Vivado 2018.3 has been the frequency along with optimized LUTs and FF, power
used to implement the FIR Filter Architecture by utilizing IP and delay than normal FIR Filters.
Integrator.
Compared to normal RTL implementation, IP Integrator VI. RESULTS
can optimize parameters like power, delay and utilization.

Figure 11 : Simulation of 32-tap FIR Filter

The above figure 13 shows Simulation Results of 32-tap

Figure 10 : Reversible FIR FILTER using IP Integrator FIR Filter using IP BLOCKS and D_0, clock, reset are
inputs and Q_0 is output.
Experimental results of FPGA performances of VD-CLA-
FIR and VD-CSLA-FIR method are as follows. IX. CONCLUSIONS
Table 2 : Normal Architecture of Reversible VD-CLA-FIR Filter Several types of full adders i.e., Carry Look Ahead Adder
and Carry Select Adder are involved for the implementation
of 4-bit & 8-bit Vedic Multiplier and FIR Filter. All these
are executed using Reversible Logic Gates which have
condensed the power, delay and area along with utilization
parameters.
In this work FIR Filter was designed by in Xilinx Vivado
2018.3 using ZYNQ Board. Parameters like power, delay,
critical path and utilization are optimized and operating
frequency was increased using IP blocks. Comparatively,
Carry Select Adder has better performance than Carry Look
Ahead Adder.

CVR College of Engineering

 E-ISSN 2581 –7957 CVR Journal of Science and Technology, Volume 19, December 2020
P-ISSN 2277 – 3916 DOI: 10.32377/cvrjstxxxx

REFERENCES [12] S.Prema, Ramanan.S.V, R.Arun Sekar and Rajan Cristin

“High Performance Reversible Vedic Multiplier Using Cadence
[1] M. Sumalatha , P.V. Naganjaneyulu and K. Satya Prasad ," 45nm Technology” International Journal of Innovative Technology
Low power and low area VLSI implementation of vedic design and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-8
FIR filter for ECG signal de-noising" in Microprocessors and Issue-7 May, 2019.
Microsystems, vol. 71, Elsevier 2019. [13] Venkata Latha.G, Syamala.Y, Anil Chowdary.T and Murali
[2] Ashutosh Kumar Singh, Masahiro Fujita and Anand Mohan, Krishna. G, “Reversible Vedic Multiplier” International Journal of
"Design and Testing of Reversible Logic," Springer Singapore, pp. Engineering and Advanced Technology (IJEAT) ISSN: 2249 –
3-11, 2020. 8958, Volume-8, Issue-6S2, August 2019.
[3]R. Arun Sekar and S. Sasipriya , "Implementation of FIR filter [14] P. Koti Lakshmi, B Santhosh Kumar and Prof.Rameshwar
using reversible modified carry select adder," in Recent Research Rao, “Implementation of Vedic Multiplier Using Reversible Gates”
Challenges in Intelligent Techniques, Big Data and Internet of Computer Science & Information Technology. 5. 125-134.
Things (ITBDIOT2018), Wiley Online Library on, vol. 31, Issue 10.5121/csit.2015.51311. Systems (2002) 566–581.
14, 25 July 2019 [15] Raghava Garipelly, P.Madhu Kiran and A. Santhosh Kumar,
[4] Bommalingaiah Nanjappa Mohan Kumar and Rangaraju “A Review on Reversible Logic Gates and their Implementation”
Hulivangala Gangappa, "Low Area VLSI implementation of CSLA International Journal of Emerging Technology and Advanced
for FIR Filter Design" International Journal of Intelligent Engineering, Volume 3, Issue 3, March 2013.
Engineering and Systems, Vol.12, No.4, 2019. [16] Pramod Patali and Shahana Thottathikkulam Kassim, “High
[5] Sumalatha Madugula, Panchala Venkata Naganjaneyulu and throughput FIR filter architectures using retiming and modified
Kodati Satya Prasad, "Implementation of FIR Filter for Low Power CSLA based adders” IET Circuits Devices Syst., 2019, Vol. 13 Iss.
and Area Minimization Using Shift –Add Method without 7, pp. 1007-1017.
Multipliers " International Journal of Intelligent Engineering and [17] S. Al-Khammasi, K. A. I. Aboalayon, M. Daneshzand, M.
Systems, Vol.10, No.6, 2017. Faezipour and M. Faezipour, "Hardware-based FIR filter
[6] Sahu L., Kumar U., Singh L., (2019) “Implementation of implementations for ECG signal denoising: A monitoring
Improved Energy-Efficient FIR Filter Using Reversible Logic”. In: framework from industrial electronics perspective," 2016 Annual
Mishra D., Yang XS., Unal A. (eds) Data Science and Big Data Connecticut Conference on Industrial Electronics, Technology &
Analytics. Lecture Notes on Data Engineering and Automation (CT-IETA), Bridgeport, CT, 2016, pp. 1-6, doi:
Communications Technologies, vol 16. Springer, Singapore. 10.1109/CT-IETA.2016.7868243.
[7] C. Durgadevi , M. Renugadevi , C. Sathyasree, R.Chitra, 2017, [18] Mahesh Kadam , Kishor Sawarkar , Sudhakar Mande,
Design of High Speed Vedic Multiplier Using Carry Select Adder, “Comparative Analysis and Efficient VLSI Implementation of FIR
INTERNATIONAL JOURNAL OF ENGINEERING RESEARCH Filter”, International Journal of Advanced Research in Electrical,
& TECHNOLOGY (IJERT) NCIECC – 2017 (Volume 5 – Issue Electronics and Instrumentation Engineering, Vol. 3, Issue 7, July
09),. 2014.
[8] V. Shiva Prasad Nayak , N. Ramchander , R. Sumanth Reddy , [19] Goldberger AL, Amaral LAN, Glass L, Hausdorff JM, Ivanov
T Hemanth Sai Praveen Redy and M. Srisri Reddy, "Analysis and PCh, Mark RG, Mietus JE, Moody GB, Peng CK, Stanley HE.
design of low-power reversible carry select adder using D-latch" in PhysioBank, PhysioToolkit, and PhysioNet: Components of a New
IEEE International Conference on Recent Trends in Electronics, Research Resource for Complex Physiologic Signals. Circulation
Information & Communication Technology (RTEICT) in, 2016, 101(23):e215-e220 [Circulation Electronic Pages;
pp. 1917-1920. http://circ.ahajournals.org/content/101/23/e215.full]; 2000 (June
[9] S.A.Mashankar, R.D.Kadam and P.R.Indurkar, "Power 13). PMID: 10851218; doi: 10.1161/01.CIR.101.23.e215.
Efficient Carry Select Adder using D-Latch" International [20] Md. Belayet Ali , Md. Mosharof Hossin and Md. Eneyat
Research Journal of Engineering and Technology (IRJET) Volume: Ullah, “Design of Reversible Sequential Circuit Using Reversible
02 Issue: 03 | June-2015 Logic Synthesis”, International Journal of VLSI design &
[10] Rahmati, M., Houshmand, M. & Houshmand Kaffashian, M. Communication Systems (VLSICS) Vol.2, No.4, December 2011.
Novel designs of a carry/borrow look-ahead adder/subtractor using [21] Samir Palnitkar, “Verilog HDL: A guide to Digital Design and
reversible gates. J Comput Electron 16, 856–866 (2017). Synthesis”, Sunsoft Press, 1996.
https://doi.org/10.1007/s10825-017-1031-6. [22] N.H.E.Weste, David Harris and Ayan Banerjee, “CMOS VLSI
[11] Shailja Shukla, Tarun Verma and Rita Jain, “Design of 16 Bit Design: A Circuits and Systems Perspective”, 2016.
Carry Look Ahead Adder Using Reversible Logic” International
Journal of Electrical, Electronics and Computer Engineering 3(1):
83-89(2014).

CVR College of Engineering