itron SMART TFT Modules TU800X480C-RT Range

TU Series Hardware Specification

7.0 inch SMART TFT Module with Resistive Touch

Customer Standard Product

Product Range TU800X480C-RT
Description 7.0 inch Intelligent TFT Module with Resistive Touch
Document Number 48320
st
Document Date 31 March 2014
Document Issue 2

Product Overview

* 7.0 inch TFT * Single 5VDC Supply * 3V3/5V Logic * 2 ADCs

* 800x480 pixels * ARM9 CPU * 3 Async UART, I2C, SPI * Up to 3 PWMs
* 262K colours * 64M byte RAM * RS232, RS485 / RS422 * AC97 Audio Bus
* LED backlighting * 128M byte NAND * Up to 31 user I/O * Real Time Clock / Alarm
* 4 Wire Resistive Touch * 8K EEPROM * USB 2.0 Device * itronOS+ / LinuxOS

Applicable Products
Part Number Touch RS232 RS485 RS422 AS1, I2C, SPI CN8 OpSystem
TU800X480C-K611A1R Resistive Yes Yes Yes 3V3 logic No itronOS+
TU800X480C-K611A1RU Resistive Yes Yes Yes 3V3 logic Yes itronOS+
TU800X480C-K611A1RUS Resistive Yes Yes Yes 5V/3V3 logic Yes itronOS+

TU800X480C-K612A1R Resistive Yes No No 3V3 logic No itronOS+

TU800X480C-K612A1RU Resistive Yes No No 3V3 logic Yes itronOS+
TU800X480C-K612A1RUS Resistive Yes No No 5V/3V3 logic Yes itronOS+

TU800X480C-K618A1RU Resistive Yes Yes No 3V3 logic Yes itronOS+

TU800X480C-K611A1RUL Resistive Yes Yes Yes 3V3 logic Yes Linux

TU800X480C-K612A1RUL Resistive Yes No No 3V3 logic Yes Linux

Suffix E Product has EMI filter glass fitted between touch and TFT panels- e.g. TUES
Suffix F Product has EMI foil fitted on the rear and sides of the module- e.g. TUFL

This product is subject to change and controlled by version number increment.

Check www.itrontft.com for the latest update.

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Index
Section Contents Firmware Notes Page
1 Change Log & Planned Changes 2
2 Product Description 3
3 Circuit Block Diagram 3
4 Electrical Characteristics 4
5 Optical Characteristics 4
6 Environmental Characteristics 5
7 EMC Test Results 5
8 ESD Test Results 5
9 Mechanical Drawing 6
10 Connector Location Drawing 7
11 Connector Pin Assignment 7
12 Connector Function 8
13 Jumper Settings 9
14 Power On, Reset, Watchdog, Brown Out 10
15 I/O Ports itronOS+ K0-K30, Linux GPIO 10
16 Asynchronous Interfaces AS1/AS2/DBG itronOS+ AS1,AS2,DBG, Linux TTYS3,-,TTYS0 10
17 RS232 Interface itronOS+ RS2, Linux TTYS1 11
18 RS485 / RS422 Interface itronOS+ RS4, Linux TTYS2 11
19 I2C Interface itronOS+ I2C, Linux driver required 12
20 SPI Interface itronOS+ SPI, Linux driver required 12
21 USB 2.0 Device Interface itronOS+ USB, Linux driver required 13
22 Interface Connector CN4 13
22.1 AC97 Audio Serial Bus Interface itronOS+ AC97, Linux driver required 13
22.2 Analogue to Digital Inputs itronOS+ ADC1-6, Linux driver required 13
22.3 Pulse Width Modulation Outputs itronOS+ PWM1-4, Linux driver required 13
24 Piezo / Relay Interface and Fuse F1 itronOS+ BUZZ, Linux GPIO 13
25 Resistive Touch Panel 14
26 Product Image – Front and Rear 14
27 Packaging 15
28 Handling and Operating Precautions 15
Quick Reference Datasheet 16

1 – Change Log
Issue Changes / Additions Date
1 Document Transfer to PDF from WEB format 14/03/2014
2 Inclusion of Quick Reference Datasheet and part number revision 31/03/2014

1.1 – Planned Changes

Item Date
Second I2C Master connection in board Q2/2014
RS485 Direction Control added to CN12/CN13 to allow LINBUS adaptor from one connector Q2/2014

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2 – Product Description
This module includes a 800X480 pixel TFT panel mounted on a printed circuit board with low profile construction.
Each pixel has red, green and blue striped elements with 18 bit colour control and 8 bit alpha blending.
The resistive touch is internally connected and controlled by the CPU with the accuracy and sensitivity controlled by the firmware.

The TFT backlight power supply requirements are achieved using a 1Mhz switching boost circuit with constant current control.
Brightness level is controlled by a PWM output from the CPU configured by the application program.

Power and data interfacing is achieved through optional PCB connections.

Many data lines have RC or LC filters to reduce effects due to noise and static discharge.
Pre-regulation of the supply permits a wide operating supply voltage to allow for voltage drop in a long supply cable.

The CPU with ARM9 core, 64Mbyte SDRAM and 128Mbyte NAND flash memory provide control of data processing, font
generation, display scanning and peripheral control. 8K bytes of EEPROM provide non-volatile memory for system and user
parameter storage. The SD card connector allows loading of the original operating system and other ports can also provide
updates depending on the operating system used.

The CPU has an adjustable peripheral and core clock frequency from 80MHz/160MHz to 92MHz/184MHz in 2MHz steps.
This can be adjusted by firmware to reduce noise within specific frequencies critical to certain applications.

An internal independent watchdog chip is reset by the main CPU on a typical 600ms cycle. In the event of a malfunction, the
watchdog resets the internal and external 3V3 supply forcing a cold boot for the CPU, memory and any external peripherals
connected to the module. The /RESET input on CN3 connects directly to the watchdog circuit and turns off the 3V3 supply when
held low.

A CR2032 battery in the optional holder or battery supply connection provide backup power for the Real Time Clock.

This module is designed to be RoHS compliant with sub class A EMI emission and 2kV human body contact model for touch

3 –Circuit Block Diagram

5V
3V3
Reset CR2032
VR
Battery
Holder
Watch Option
Dog
USB
64Mbyte
RAM

ARM9
128Mbye
CPU
I/O NAND
ADC
PWM

SD Card
Touch Holder
Screen

LED
Backlight TFT LCD
PSU Panel

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4 – Electrical Characteristics
Section Parameter Symbol Min Typ Max Unit Condition
5V Input Supply Voltage VCC1 4.5 5.0 5.5 VDC GND = 0V
Power Supply Supply Current ICC1 580 620 650 mA Vcc1=5V - All pixels ON
Icc2 250 270 320 mA Vcc1=5V - LED backlight off
Icc3 50 60 70 mA Vcc1=5V – Reset LOW
3V3 Output Supply Voltage VCC2 3.2 3.3 3.4 VDC GND = 0V
Power Supply Supply Current ICC2 - - 200 mA VCC1=5V
Data Interfaces Logic Input Low VIL 0 - 0.5 VDC VCC2=3V3
and I/O Ports Logic Input High VIH 2.0 - Vcc2 VDC K0-K30, SDHC, ADC
Logic Output Low VOL 0 - 0.7 VDC Maximum sink current 10mA per port
Logic Output High VOH 3.0 - 3.4 VDC Total sink current 70mA
RS232 Logic Input Low VIL -15.0 - 0.6 VDC VCC2=3V3
interface (RX) Logic Input High VIH 2.0 - +15.0 VDC VCC2=3V3
RS232 Logic Output Low VOL - -3.0 -2.0 VDC VCC2=3V3
interface (TX) Logic Output High VOH 4.0 7.0 - VDC VCC2=3V3
/RESET Logic Input Low VIL 0 1.2 VDC Vcc1=5V
Logic Input High VIH 2.2 3.4 VDC Vcc1=5V
Backup Battery Sustain Voltage Vbb 1.5 3V 3.6 VDC Vcc1=0V – 180mAH ~ 360 days
If data signals are applied before the power supply stabilizes, the module CPU may not start correctly until a watchdog timeout.

5 – Optical Characteristics
Visual Parameter Value
Display Area (X x Y) 152mmx91mm – 7.0 inch diagonal
Display Format (X x Y) 800 x 480 pixels
Dot Size/Pitch (X x Y) 0.19mm x 0.19mm
RGB Colours 262,144
Display Type Transmissive
Prime Viewing Angle 6 o’clock (colour inversion at 12 o’clock)
Visual Parameter Symbol Min. Typ. Max. Unit Condition
Contrast Ratio CR 250 350 - - At optimized viewing angle
Wx 0.26 0.31 0.36 - Θ=0° Φ=0°
Color Chromaticity White
Wy 0.28 0.33 0.38 - Θ=0° Φ=0°
ΘR 50 60 - Deg. CR≥10
Hor.
ΘL 50 60 - Deg. CR≥10
Viewing Angle
ΦT 40 55 - Deg. CR≥10
Ver.
ΦB 50 60 - Deg. CR≥10
Brightness - 280 300 - cd/m² Center of Display
LED Backlight Lifetime - 20,000 - - Hours 50% of brightness @ 25°C
Visual Parameter Defect Criteria Size (mm) Acc. Qty
TFT Black / White spot, ȹ= (a + b) /2 0.10 < ȹ ≤ 0.15 2
Foreign material, Pinholes a 2 defects allowed more than 3mm apart 0.15 < ȹ ≤ 0.25 1
Stain, Particles inside cell. Defects outside display area allowed 0.25 < ȹ 0
(Minor defect) b
TFT Black and White line, W W: Width L: Length L<0.25 0.03 < W ≤ 0.05 3
Scratch, Foreign material 2 defects allowed more than 3mm apart 0.05 < W ≤ 0.10 2
(Minor defect) Defects outside display area allowed 0.1 < W 0
L
Bezel Visible rust, distortion, fingerprints or stains D ≥ 0.1 0
Touch Panel D: Diameter Spot D ≥ 0.4 0
Spot & Dent D 2 defects allowed more than 10mm apart Dent D ≥ 0.4 0
Defects outside display area allowed
D
Touch Panel W W: Width L: Length L<10 Scratch W ≥ 0.10 0
Scratch 2 defects allowed more than 10mm apart
Defects outside display area allowed
L
Polarizer – Bubble or Dent ȹ= (a + b) /2 0.20 < ȹ ≤ 0.30 4
(Minor defect) a 2 defects allowed more than 3mm apart 0.30 < ȹ 0
Defects outside display area allowed
b

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6 – Environmental Characteristics
Parameter Value
Operating Temperature Range -20°C to +70°C
Storage Temperature Range -30°C to +70°C
Storage Humidity 30 to 80% RH @ 25°C Non condensing
Vibration – non operating 10-55-10Hz, amplitude 1mm for 30mins XYZ
Shock – non operating 250m/s² 10ms XYZ
Printed Circuit Board 6 layer FR4 V0
Avoid applying uneven pressure to the circuit board, connector or glass face.
Avoid magnetic fields which could induce currents within the touch screen.

7 – EMC Conducted and Radiated Emissions Test

Test Signal Frequency range Peaks Notes
Conducted VCC1 500kHz – 5MHz 720kHz @ -53.7dBm Backlight PSU
5MHz - 100Mhz 28.2MHz @ -66.2dBm TFT Panel Clock
100Mhz – 1GHz 184MHz @ -45.7dBm CPU Clock
368MHz @ -51.3dBm CPU Clock Harmonic
Radiated Vcc1 25Mhz-200Mhz 127.4MHz @ 39.5dBuV/m Just below class B 40dBuV/m
200Mhz-1GHz 461.3Mhz @ 47.1dBuV/m Just above class B 47dBuV/m
551.5MHz@ 51.2dBuV/m Above Class B
643.2Mhz @ 48.0dBuV/m Just above class B 47dBuV/m
1GHz – 3GHz Below class B
Product designed to meet class A industrial requirements without shielding. Contact us regarding class B.
Product is available with EMI filter glass (suffix E) and foil encapsulation (suffix F) for EMI critical applications.

8 – Electro Static Discharge Test

Method Samples HT level 1kV 3kV 5kV 9kV Notes
Contact Discharge 50 Spurious Pixels No No Yes Yes
Module Reset No No No Yes
Permanent Damage No No No No
Method Samples HT level 4kV 8kV 12kV 16kV Notes
Air Discharge 50 Spurious Pixels No No Yes Yes
Module Reset No No No Yes
Permanent Damage No No No No

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9 – Mechanical Drawing

Dimensions are in mm. When an EMI filter glass is fitted, the thickness increases by 1.0mm maximum.
Mounting pins connect the TFT panel frame to the PCB for placement accuracy, shielding and fixing.
By design, excess pressure to the TFT panel during mounting causes the pin fixing to fail before the TFT.
When the USB connector CN8 is removed for space critical applications, the part number suffix ‘U’ is omitted.

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10 – Connector Location

Dimensions are in mm.

11 – Connector Assignment Pin 1 is a square pad on the PCB. DIL pin 2 is opposite to pin 1 on the other row.
CN1: RS232 CN2: POWER CN3:AS1 / I2C / SPI + I/O Ports
Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal
1 NC / Tx+ 2 DTR / Rx- 1 Vcc1 1 Vcc1/Vcc2* 2 SCL, SCK, K24
3 TXD 4 CTS 2 /PZ * 3 SI, /SS, K25 4 SDA, MOSI, K26
5 RXD 6 RTS 3 GND 5 GND 6 /IRQ1, MOSI, K27
7 DSR/Rx+ 8 NC / Tx- *O/C 20V FET 7 SO, /IRQ2, K28 8 /RESET
9 GND 10 Vcc1* 9 MB, K29 10 HB, K30
*when J47 soldered *selectable via jumper on front next pins 1 & 2

CN4: ADC / PWM / AUDIO + I/O Ports CN5: USB / SDHC Expansion CN6: DBG
Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal
1 ADC1, K16 2 ADC2, K17 1 DA2 2 DA3 9 GND 10 CD 1 Vcc2
3 GND 4 Vcc1/Vcc2* 3 CDA 4 Vcc2 11 GND 12 Vcc1 2 GND
5 PWM1, K18 6 PWM2, K19 5 CK 6 GND 13 USB- 14 USB+ 3 DRXD
7 ATX, K20 8 ARX, K21 7 DA0 8 DA1 15 CNX 16 GND 4 DTXD
9 ACH, K22 10 AFS, K23
*selectable via jumper on front next pin 1&2 Enable USB on CN5 or J6 by linking J1 and J5 on back of PCB.

CN7: I/O Ports CN12: RS4 CN13: ADC CN15: USB

Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal
1 Vcc1 2 GND 11 K6 12 K7 1 SDO 1 GND 1 Vcc1
3 Vcc2 4 GND 13 K8 14 K9 2 GND 2 ADT0 2 USB
5 K0 6 K1 15 K10 16 K11 3 SDI 3 ADT3 3 USB
7 K2 8 K3 17 K12 18 K13 4 Vcc1 4 ADT1/2 4 CNX
9 K4 10 K5 19 K14 20 K15 3v3 logic 5 ADT1/2 5 GND

Vcc1 is the un-fused 5V PSU input Vcc2 is the fused internal regulated 3V3 logic supply CN13 for touch test only

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12 - Connector Function
Pin Signal Function
CN1-1 NC / Tx+ / TxRx+ Not connected in -K612 version. RS422 -K611 versions - transmit positive. RS485 TxRx+
CN1-2 DTR Rx- RS232 flow control output. RS422 -K611 versions - receive negative
CN1-3 TXD RS232 transmit output
CN1-4 CTS RS232 flow control input
CN1-5 RXD RS232 receive input
CN1-6 RTS RS232 flow control output
CN1-7 DSR / Rx+ RS232 flow control input. RS422 -K611 versions - receive positive
CN1-8 NC / Tx- / TxRx- Not connected in -K612 versions. RS422 -K611 versions - transmit negative. RS485 TxRx-
CN1-9 GND 0V
CN1-10 Vcc1 5V input / output when J47 is soldered
CN2-1 Vcc1 5V input / output
CN2-2 /PZ Open drain buzzer output
CN2-3 GND 0V
CN3-1 Vcc1/Vcc2 5V input / output or 3V3 output depending on jumper
CN3-2 SCL, SCK, K24 SCL I2C clock, SCK SPI clock or K24 user I/O
CN3-3 SI, /SS, K25 Serial input AS1, Slave Select SPI or K25 user I/O
CN3-4 SDA, MOSI, K26 SDA I2C data , MOSI SPI data or K26 user I/O
CN3-5 GND 0V
CN3-6 /IRQ1, MOSI, K27 /IRQ1 I2C interrupt request, MOSI SPI data or K27 user I/O
CN3-7 SO, /IRQ2, K28 Serial output AS1, /IRQ2 SPI or K28 user I/O
CN3-8 /RESET Master reset - active LOW
CN3-9 MB, K29 Module busy output (AS1) or K29 user I/O
CN3-10 HB, K30 Host busy input (AS1) or K30 user I/O
CN4-1 ADC1, K16 ADC channel 1 input or K16 user I/O
CN4-2 ADC2, K17 ADC channel 2 input or K17 user I/O
CN4-3 GND 0V
CN4-4 Vcc1/Vcc2 5V input / output or 3V3 output depending on jumper
CN4-5 PWM1, K18 PWM channel 1 output or K18 user I/O
CN4-6 PWM2, K19 PWM channel 2 output or K19 user I/O
CN4-7 ATX, K20 AC97 transmit or K20 user I/O
CN4-8 ARX, K21 AC97 receive or K21 user I/O
CN4-9 ACK, K22 AC97 clock or K22 user I/O
CN4-10 AFS, K23 AC97 frame select or K23 user I/O
CN5-1 DA2 SD card data 2
CN5-2 DA3 SD card data 3
CN5-3 CDA SD card command
CN5-4 Vcc2 3V3 output only
CN5-5 CK SD card clock
CN5-6 GND 0V
CN5-7 DA0 SD card data 0
CN5-8 DA1 SD card data 1
CN5-9 GND 0V
CN5-10 CD SD card detect
CN5-11 GND 0V
CN5-12 Vcc1 5V input / output
CN5-13 USB- USB D-
CN5-14 USB+ USB D+
CN5-15 CNX USB connector attach (not used)
CN5-16 GND 0V
CN6-1 Vcc2 3V3 output only
CN6-2 GND 0V
CN6-3 DRXD Debug (DBG) receive input
CN6-4 DTXD Debug (DBG) transmit output

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12 - Connector Function contd.
Pin Signal Function
CN7-1 Vcc1 5V input / output
CN7-2 GND 0V
CN7-3 Vcc2 3V3 output only
CN7-4 GND 0V
CN7-5 K0 AS2 transmit or K0 user I/O
CN7-6 K1 AS2 receive or K1 user I/O
CN7-7 K2 User I/O
CN7-8 K3 User I/O
CN7-9 K4 User I/O
CN7-10 K5 User I/O
CN7-11 K6 User I/O
CN7-12 K7 User I/O with link option for PWM4
CN7-13 K8 User I/O
CN7-14 K9 PWM3 or User I/O
CN7-15 K10 User I/O
CN7-16 K11 User I/O
CN7-17 K12 User I/O
CN7-18 K13 User I/O
CN7-19 K14 User I/O
CN7-20 K15 User I/O
CN12-1 TXDO RS485 3V3 level transmit output can be used when RS485/422 ICs not fitted
CN12-2 GND 0V
CN12-3 RXDI RS485 3V3 level receive input can be used when RS485/422 ICs not fitted
CN12-4 Vcc1 5V input / output
CN13-1 GND 0V
CN13-2 ADT0 Resistive touchscreen ADC channel0
CN13-3 ADT3 Resistive touchscreen ADC channel3
CN13-4 ADT1/2 Resistive touchscreen ADC channel1/2
CN13-5 ADT1/2 Resistive touchscreen ADC channel1/2
CN15-1 Vcc1 5V input / output
CN15-2 USB- USB D-
CN15-3 USB+ USB D+
CN15-4 CNX USB connector attach (not used)
CN15-5 GND 0V

13- Jumper Settings

BT1 Battery Connector Apply solder bump to center pad before fitting holder. CR2032 battery positive up
BATT1 RTC supply Apply right angle connector top side soldered for RTC backup during power off.
J24 LED backlight When the backlight is software disabled, 30VDC at 20mA can be externally supplied
J4 RTS Solder 1 and 2 for RTS
J8 RS485 Half Duplex Solder 1 and 2 for Full Duplex, solder 2 and 3 for Half Duplex
J11 SPI link Solder all four links in the array to connect the SPI interface to CN3.
J14 WP Write protect EEP Solder to prevent data update of EEPROM non-volatile memory where fitted.
J15 RTS+RS4/DTR Solder 1 and 2 for RTS and RS485 if fitted, solder 2 and 3 for DTR when RS485 not fitted
J16 CTS+RS4/DSR Solder 1 and 2 for CTS and RS485 if fitted, solder 2 and 3 for DSR when RS485 not fitted
J17 Watchdog Timeout Open = 600ms (default). Link 1 and 2 = 1200ms. Link 2 and 3 = 150ms.
J18 WP Write protect NAND Solder to prevent data update of NAND memory
J19 Mounting Hole Link to connect mounting hole plating to 0V.
J33 Touch Orientation Solder 1 and 2 for standard touch. Solder 2 and 3 for external touch using CN13 or CN14.
J34 Touch Orientation Solder 2 and 3 for standard touch. Solder 1 and 2 for external touch using CN13 or CN14.
J46 CN1 Pin10 Vcc1 Solder this jumper to connect the 5V supply to Pin 10 on CN1
J53 CN8 USB Supply Linked by default. Disconnect to prevent USB supply powering module.
J55 CN8 USB Frame Linked by default. Disconnect to prevent USB cable screen connection to 0V
LK1/LK2 TFT Frame GND Soldered by default to connect the metal frame of the TFT to 0V
LK3/LK4 TFT Frame GND Soldered by default to connect the metal frame of the TFT to 0V
Note: RTS/CTS or DTR/DSR can be selected, not both. When RS485 fitted in model K611A1xx then only RTS/CTS are possible.
Other jumpers are for factory product configuration and should not be adjusted without approval.

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14 - Power On, Reset, Watchdog and Brownout Protection
At POWER ON the internal and external 3V3 supply will rise in under 20ms to supply the CPU and peripheral circuits.
The firmware must load into RAM from an SDHC card or NAND memory and send a watchdog strobe pulse to the independent
supervisor chip within the time period set by J17 otherwise the total system will be internally reset. Modules using the Linux
operating system have a supervisor with extended wake up period of 5 seconds before the first watchdog strobe is required.
On /RESET, the CPU and peripheral supply is disconnected until /RESET raised above it’s HIGH threshold voltage.
During power off and /RESET, the RTC can be maintained by a connected backup battery or separate power source.
The supervisor has a brown out detection circuit set at 2.9VDC and will reset the system if the Vcc1 supply has fallen below 3.4V.

15 - I/O Ports K0 to K30

Many I/O ports have dual functions as a general purpose logic level inputs / outputs or a fixed function interface.
During reset and at power on all I/O ports are pulled high so it is important to provide an inverting circuit to ensure a low condition
where required. Pull up resistors can be activated for each input and interrupts assigned for counting and other trigger functions
by the firmware.
RC Filter
Symbol
Many I/O include RC filters close to their connectors to reduce EMI noise 47R-100R
and protect against static discharge. These may cause rounded edges
where fast clocks are required so the filter component values can be Connector CPU
modified as a semi-custom solution. The maximum output sink current 47pF - 100pF
for each I/O is 10mA depending on the filter series resistance.
0V
16 - Asynchronous Communication AS1, AS2, DBG
The asynchronous logic level (3V3) interfaces have a maximum baud rate of 1M bits per second subject to inter-connection.
Optional buffers can be fitted for connection to systems where open collector drive mode is required at 3V3 or 5V logic levels.
The baud rate, data orientation, stop bits, handshaking, buffer size and associated interrupts can be configured by the firmware.
AS1 output MB - Module Busy and input HB - Host Busy support hardware handshaking between master and slave.

START D7 D0 START D7 D0 START D7 D0

SI/SO
Data 1 Data 2 Data 3 Buffer Full
MB/HB

CN3 Interface AS1 AS1D CPU AS1D

SI 3
Open collector bus
AS1I
SO 7 AS1O
drivers are fitted as suffix option S
HB 9 PHB (e.g. -K611TUS)
MB 10 PMB
These have pull ups to 5V or 3V3
0V 5 0V according to the Vcc setup.
Vcc 1 Vcc1 in/out
Vcc2 out

CN7 Interface AS2 CPU CN6 Interface DBG CPU

SI 6 AS2I DRXD 3 DBGI

SO 5 AS2O DTXD 4 DBGO

0V 4 0V 0V 2 0V

AS2 and DBG can be used as debug ports or general purpose asynchronous interfaces depending
on the installed firmware.

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17 – RS232 Communication RS2
The RS232 interface has a maximum baud rate of 1M bits per second subject to inter-connection.
The interface buffer IC provides a limited negative and positive supply (-3V,+7V) suitable for short distance, low load applications.
The baud rate, data orientation, stop bits, handshaking, buffer size and associated interrupts can be configured by the firmware.
The pin out of CN1 is designed to directly connect to a PC serial port via IDC cable and connectors. CTS and RTS or DTR and
DSR can be selected depending on the required handshaking method.

START D7 D0 START D7 D0 START D7 D0

RXD/TXD
Data 1 Data 2 Data 3 Buffer Full
CTS/RTS

CN1 Interface RS2 232 IC CPU RS232 IC

RXD 5 B RS2I The part number suffix K612 indicates
TXD 3 U RS2O an RS232 level shift inverter buffer is
CTS 4 J16, 1+2 F PCTS fitted.
RTS 6 F PRTS
J15, 1+2
DSR 7 J16, 2+3
E J47 can be disconnected when
DTR 2 R CN1 is connected to a 9 way
J15, 2+3
0V 9 0V
Vcc1 D-type connector via a 10 way ribbon
5V 10
J47 cable and the power supply line is not
used.
J47 can be disconnected when CN1 is connected to a 9 way
D-type connector via a 10 way ribbon cable and the power supply line is not used.

18 – RS485 / RS422 Communication RS4

A half duplex two wire RS485 or four wire full duplex RS422 interface are provided on CN1 using a differential driver ICs.
RS485/422 can be used at the same time as RS232 RXD/TXD/CTS/RTS.
The RS4 UART is available on CN12 in products suffix -K612 at 3V3 logic level.

START D7 D0 STOP START D7 D0 STOP START D7 D0 STOP

Rx/Tx
Data 1 Data 2 Data 3

In half duplex mode the Tx connections are used to send and receive data.
In full duplex mode, data can be received on the Rx lines and sent on the Tx lines independent of each other.
The Tx lines are high impedance when not used.
Care must be taken not to exceed the maximum loading of 8 devices per line. Please consult us if a higher loading is required.

CN1 Interface RS4 IC CPU CN12

Tx+ 1 T Vcc1 4
Tx- 8 X RS4O 1 TX
R14 D DC
R13 3 RS4I 3 RX
Rx+ 7 2
R 1 J8
Rx- 2 X
0V 9 D 0V 2 0V
5V 10 Vcc1
J47

When using full duplex RS422 jumper J8 1&2 are joined and for half duplex RS485, J8 2&3 are joined.
R13 and R14 are 1K ohm. Line termination should be external.

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19 – I2C Communication
2
The I C interface operates in slave or master mode as a twin wire interface. The maximum speed is 400K bits per second subject
to inter-connection. Optional buffers can be fitted for connection to systems where open collector drive is required at 3V3 or 5V.
Addr Addr
MSB LSB R/W ACK MSB LSB ACK MSB LSB ACK
SDA

SCL 1 7 8 9 1 8 9 1 8 9

START SLA+W Data 1 Data n STOP

A START condition is signaled by driving SDA low while SCL is high. A STOP condition is signaled by driving SDA high while SCL
is high. After a START condition is detected by the slave followed by ‘SLA+W’ with the 7 bit address and Read/Write from the
master, the slave signals acceptance by raising the ACK bit. When a STOP condition is detected the data received is processed.
The /IRQ can be used by a slave device to signal the host that data is available for read. When not active, the port is set to input
and when active the port is set to output low.

CN3 Interface I2C I2CD CPU I2CD

SCL 2 SCL Open collector I2C bus
SDA 4 SDA drivers are fitted as suffix
/IRQ 6 IRQ option W or S
MB 9 PH (e.g. -K611TUS)
HB 10 PM
0V 5 0V These pull up to 5V or
Vcc 1 3V3 according to the
Vcc1 in/out
Vcc2 setting of Vcc.
out
20 - SPI Interface
The SPI interface requires jumper J11 pads 1-2,3-4,5-6 and 7-8 are linked. Optional open collector buffers can be fitted for
operation in systems that require 3V3 or 5V interface. The maximum speed is 1M bits per second subject to inter-connection.
The order of data bits and the rising or falling edge of clock can be defined in software

In slave mode, the /SS (slave select) signal is used as a device select and must be low when clocking data in/out. Internal display
receive / transmit logic is reset and resynchronized on the rising edge of /SS. Data is clocked into input MOSI and out of output
MISO simultaneously on the software selected edge of SCK. The MB port can be enabled to signal the module is busy.
In master mode the /SS or other I/O ports can be software configured as slave select to interface to multiple devices.
Data is clocked out of output MOSI and in to input MISO simultaneously on the software selected edge of SCK.
The example below shows clocking on the rising edge of SCK.

/SS

SCK

MOSI D0 D7 D0 D7

MISO

CN3 Interface SPI SPID Link CPU

J11 SPID
SCK 2 SCK
MOSI 4 MOSI Open collector bus
MISO 6 MISO drivers are fitted as suffix option S
/SS 3 /SS (e.g. -K611TUS)
/IRQ 6 /IRQ
HB 10 PH These have pull ups to 5V or 3V3
MB 9 PM according to the Vcc setup.
0V 5 0V
Vcc 1 Vcc1 in/out
Vcc2 out

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21- USB 2.0 Device Interface
The USB interface operates as a USB Device for CN5 CN15 CN8 Interface USB CPU
J1
connection to a host such as a PC. An internal filter 14 3 3 D+
provides ESD protection and noise suppression. 13 2 2 D-
When using the pre-fitted connector CN8, it is not J5
J48 filter
recommended to link J1 and J5 which connect CN5 Vcc1 12 1 1 Vcc1
or CN15 otherwise line imbalance could occur. 15 4 4 CNX
Depending on the firmware, a software driver will 16 5 5 0V
0V
require installation on the host. Please refer to the J49
web for USB 2.0 specification details.
Disconnect J48 to stop the USB host supply powering the module and link J49 to connect the CN8 USB screen to the module 0V.

22- CN4 Interface AC97, ADC, PWM

CN4 Interface CN4 CPU
ADC1 2 AD4
. ADC2 4 AD5 The AC97 interface requires lower values due to the
PWM1 6 PW2 high speed clock. Please contact us for further
PWM2 3 PW3
ATX 6 TX97
information when using this bus.
ARX 9 RX97
ACK 10 CK97 The solder jumper on the front of the module adjacent
AFS 5 FS97 to CN4 allows Vcc1 (5V) or Vcc2(3V3) to be
0V 1 0V connected to pin 4 depending on user requirement.
Vcc Vcc1 in/out
4
Vcc2 out

22.1- AC97 Audio Interface

The AC97 high speed interface can connects to a compatible codec to provide high quality stereo audio input and output.
As the clock speed is typically 40MHz and it may be necessary to use a ferrite sleeve on the connecting ribbon cable when using
the ports as an audio bus. Please refer to the web for further details on the AC97 protocol and timing.

22.2- Analogue to Digital Conversion ADC1/ ADC2

The ADC reference voltage is connected to the 3V3 supply via an LC filter. The ADCs have a 10 bit resolution producing
conversion values of between 0 for 0V and 1023 for 3V3 with a tolerance of 5. Since the value at 0V may not be 0, it is important
to take this into consideration when designing your analogue interface circuit if a zero value is important. The maximum sample
rate is 200kHz and is available for processing according to the firmware configuration. Calibration values can be retained in the
host or stored in the on board EEPROM.

22.3- Pulse Width Modulation PWM1/ PWM2/ PWM3

The 3 PWM ports support independent 160Hz to 1MHz operating frequency with adjustable phase delay between each PWM.
The MARK-SPACE duty cycle ratios are specified with an accuracy of 0.1% from 0.0% to 99.9%.

MARK
SPACE PHASE DELAY
The idle state as MARK or SPACE can be defined by
firmware or software. At power on and during reset,
PWM1 x1 the ports are pulled high by resistors in the CPU.
PWM2 x2

PWM3

24- Piezo Buzzer / Relay Drive - /PZ and Fuse F1 Vcc1 CN1,3,4,5,7
CN2
The /PZ pin on CN2 is connected to a 30V nFET sink to GND. Fuse 1A
It is important to use CN2 for the return connection if a current greater Vcc1 1 VInt
than 200mA is required and an external reverse diode if /PZ 2
an inductive load is used. The maximum current is 400mA. CPU
A 1206 package fast blow fuse (F1) rated at 1A protects the 0V 3
internal supply. This is mounted on the rear of the PCB for user
replacement if required. FET 10K

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itron SMART TFT Modules TU800X480C-RT Range
25- Resistive Touch Panel
The resistive touch panel uses a glass substrate with ITO coating and micro spacers to separate an overlay also coated with ITO.
Conductive bars on each layer allow an X and Y voltage to be applied across each layer in turn while the other layer is connected
to ADC inputs to measure the potential difference where a touch occurs. The firmware can adjust sample rate, de-bounce and
acceptance area. It is important to calibrate each touch screen and store offset values in the host or on board EEPROM.
Use a neoprene or silicon gasket between the enclosure front panel and the touch panel to prevent false touches.
The touch panel ADC inputs can be externally connected via CN13 or CN14 as ADC3-ADC6.

Touch Parameter Min. Value Unit Note

Activation Force 80 gf Applied with a 0.8mm rubber stylus
Acquisition Rate 25 kHz ADC acquisition event X or Y every 200us
ESD Protection 5,000 VDC 15kV static protection diodes between all 4 electrodes and 0V.
Lifetime 1,000,000 Touches Test applied a 0.8mm rubber stylus with 250gf at 2 times per second.

26 – Product Image

Front Side

Rear Side

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itron SMART TFT Modules TU800X480C-RT Range
27 – Packing
Modules are packed in single or dual antistatic carbon coated card
sleeves dependent on connectors being fitted on user request.
The sleeves are then packed in a sub box containing 5 or 10 modules. Antistatic
and these are then dispatched in shipping boxes. Sleeve or
Products may be packed in anti-static bubble bags when the selected Bag Sub Box
connector or other sub-assembly does not fit the standard sleeves.

Shipping Box

28 – Handling and Usage Precautions

Please follow the appropriate product specification and other documents for proper usage, safe handling and operation
standards for maximum performance.

TFT panels are made of glass and contain liquid crystal materials
• Please avoid breaking the TFT panel to prevent injury from sharp glass particles.
• It is recommended to allow sufficient open space surrounding the TFT panel to avoid possible damage.
• Please design the mounting of the TFT module to have within 0.5 mm warping tolerance to avoid any forces that may
damage the display due to PCB distortion causing a breakdown of the electrical circuit leading to TFT module failure.
Conducting voltage
• Avoid touching conductive electrical parts with other conductive materials because the TFT-module may be damaged.
• Even when electric power is turned off, it may take more than one minute for the electrical current to discharge.
Cable connection
• Do not unplug the power and/or data cables of TFT modules during operation because unrecoverable damage may
result.
• Sending input signals to the TFT module during a power off condition sometimes causes I/O port damage.
• It is recommended to use a 30 cm or shorter signal cable to prevent functional failures subject to port application.
Electrostatic charge
• TFT modules require electrostatic free packaging and protection from electrostatic charges during handling and usage.
Structure
• During operation, TFT panels and TFT modules generate heat. Please consider sufficient heat radiation dissipation.
• We prefer to use UL grade materials or components in conjunction with TFT modules.
• Wrap and twist motion causes stress and may break the TFT or TFT module components.
Please adhere to allowances within 0.5mm at the point of attachment.
Power
• Apply regulated power to the TFT module within the specified voltages to protect from failures.
• A TFT module may consume an in rush current equal to twice the typical current at power-on due to capacitor
charging.
We recommend using a power supply capable of quick starting.
• TFT-module needs a specified voltage at the point of connection. Please use an adequate power cable to avoid a
decrease in voltage. We recommend the provision of a fuse since the onboard TFT module fuse is SMT soldered.
Operating consideration
• The LED backlight will decrease in brightness during extended operation. If a fixed pattern illuminates on a TFT panel
for an extended period, this will result in a retained ghost image. Please consider a screen safer to reduce this effect.
• We recommend using a signal cable 30cm or less to avoid noise with a ferrite fitted to reduce emission.
Storage and operating environment
• Please use TFT-modules under the recommended specified environmental conditions. Salty, sulfur and dusty
environments may damage the TFT module even during storage.
Disposal
• When discarding TFTs or TFT modules, please adhere to governmental related laws or regulations.
Others
• Although the TFT modules are designed to be protected from electrical noise, please plan your circuitry to exclude as
much noise as possible.
• Do not reconstruct or repair the TFT module without our authorization. We cannot assure the quality or reliability of
unauthorized repaired TFT modules.

Notice:
･ We do not authorize the use of any patents that may be inherent in these specifications.
･ Neither whole nor partial copying of these specifications are permitted without our approval.
If necessary, please ask for assistance from our sales management.
･ This product is not specifically designed for military, aerospace, medical or other life-critical applications.
If you choose to use this product for these applications, please consult us prior to the project design phase.

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itron SMART TFT Modules TU800X480C-RT Range
QUICK REFERENCE DATASHEET

Features
* 7.0 inch TFT
* 800x480 pixels
* 262K colours
* LED backlighting
* 4 Wire Resistive Touch
* Single 5VDC Supply
* ARM9 CPU
* 64M byte RAM
* 128M byte NAND
* 8K EEPROM
* 3V3/5V Logic
* 3 Async UART, I2C, SPI
* RS232, RS485 / RS422
* Up to 31 user I/O
* USB 2.0 Device
* 2 ADCs
* Up to 3 PWMs
* AC97 Audio Bus
* Real Time Clock / Alarm
* itronOS+ / LinuxOS

Optical Characteristics Value

Display Area (X x Y mm) 152mmx91mm – 7.0 inch diagonal
Display Format (X x Y) 800 x 480 pixels
Dot Size/Pitch (X x Y mm) 0.19mm x 0.19mm
RGB Colours 262,144
Display Type Transmissive
Prime Viewing Angle 6 o’clock (colour inversion at 12 o’clock)
Visual Parameters Symbol Min Typ Max Unit Condition
Contrast Ratio CR 250 350 - - At optimized viewing angle
Wx 0.26 0.31 0.36 - Θ=0° Φ=0°
Color Chromaticity White
Wy 0.28 0.33 0.38 - Θ=0° Φ=0°
Brightness - 280 300 - cd/m² Center of Display
LED Backlight Lifetime - 20,000 - - Hours 50% of brightness @ 25°C
Electrical Parameters Symbol Min Typ Max Unit Condition
Supply Voltage VCC1 4.5 5.0 5.5 VDC GND = 0V
5V Input ICC1 580 620 650 mA Vcc1=5V - All pixels ON
Power Supply Supply Current Icc2 250 270 320 mA Vcc1=5V - LED backlight off
Icc3 50 60 70 mA Vcc1=5V – Reset LOW
3V3 Output Supply Voltage VCC2 3.2 3.3 3.4 VDC GND = 0V
Power Supply Supply Current ICC2 - - 200 mA VCC1=5V

Applicable Products
Part Number Touch RS232 RS485 RS422 AS1, I2C, SPI CN8 OpSystem
TU800X480C-K611A1R Resistive Yes Yes Yes 3V3 logic No itronOS+
TU800X480C-K611A1RU Resistive Yes Yes Yes 3V3 logic Yes itronOS+
TU800X480C-K611A1RUS Resistive Yes Yes Yes 5V/3V3 logic Yes itronOS+
TU800X480C-K612A1R Resistive Yes No No 3V3 logic No itronOS+
TU800X480C-K612A1RU Resistive Yes No No 3V3 logic Yes itronOS+
TU800X480C-K612A1RUS Resistive Yes No No 5V/3V3 logic Yes itronOS+
TU800X480C-K618A1RU Resistive Yes Yes No 3V3 logic Yes itronOS+
TU800X480C-K611A1RUL Resistive Yes Yes Yes 3V3 logic Yes Linux
TU800X480C-K612A1RUL Resistive Yes No No 3V3 logic Yes Linux
Suffix E Product has EMI filter glass fitted between touch and TFT panels- e.g. UES
Suffix F Product has EMI foil fitted on the rear and sides of the module- e.g. UFL

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