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Lecture 16: Basic CPU Design: Today's Topics: Single-Cycle CPU Multi-Cycle CPU

This document discusses the design of basic CPU architectures. It covers single-cycle and multi-cycle CPU designs, and describes the key components of a CPU including instruction memory, registers, an ALU, and data memory. It explains how different instruction types are implemented, such as R-type, load/store, and branch instructions. Clocking methodology is also discussed, with latches being used to separate a single-cycle design into multiple pipeline stages in a multi-cycle design.

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67 views12 pages

Lecture 16: Basic CPU Design: Today's Topics: Single-Cycle CPU Multi-Cycle CPU

This document discusses the design of basic CPU architectures. It covers single-cycle and multi-cycle CPU designs, and describes the key components of a CPU including instruction memory, registers, an ALU, and data memory. It explains how different instruction types are implemented, such as R-type, load/store, and branch instructions. Clocking methodology is also discussed, with latches being used to separate a single-cycle design into multiple pipeline stages in a multi-cycle design.

Uploaded by

giga movies
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lecture 16: Basic CPU Design

• Today’s topics:

 Single-cycle CPU
 Multi-cycle CPU

1
Basic MIPS Architecture

• Now that we understand clocks and storage of states,


we’ll design a simple CPU that executes:

 basic math (add, sub, and, or, slt)


 memory access (lw and sw)
 branch and jump instructions (beq and j)

2
Implementation Overview

• We need memory
 to store instructions
 to store data
 for now, let’s make them separate units

• We need registers, ALU, and a whole lot of control logic

• CPU operations common to all instructions:


 use the program counter (PC) to pull instruction out
of instruction memory
 read register values

3
View from 30,000 Feet

Note: we haven’t bothered


showing multiplexors

• What is the role of the Add units? Source: H&P textbook

• Explain the inputs to the data memory unit


• Explain the inputs to the ALU
• Explain the inputs to the register unit 4
Clocking Methodology

Source: H&P textbook


• Which of the above units need a clock?
• What is being saved (latched) on the rising edge of the clock?
Keep in mind that the latched value remains there for an entire cycle
5
Implementing R-type Instructions

• Instructions of the form add $t1, $t2, $t3


• Explain the role of each signal

Source: H&P textbook

6
Implementing Loads/Stores

• Instructions of the form lw $t1, 8($t2) and sw $t1, 8($t2)

Where does this input come from?

7
Source: H&P textbook
Implementing J-type Instructions

• Instructions of the form beq $t1, $t2, offset

Source: H&P textbook 8


View from 10,000 Feet

9
Source: H&P textbook
View from 5,000 Feet

10
Source: H&P textbook
Latches and Clocks in a Single-Cycle Design

Instr Reg Data


PC ALU Addr
Mem File Memory

• The entire instruction executes in a single cycle


• Green blocks are latches
• At the rising edge, a new PC is recorded
• At the rising edge, the result of the previous cycle is recorded
• At the falling edge, the address of LW/SW is recorded so
we can access the data memory in the 2nd half of the cycle
11
Multi-Stage Circuit

• Instead of executing the entire instruction in a single


cycle (a single stage), let’s break up the execution into
multiple stages, each separated by a latch

Instr Reg Data


PC L2 L3 ALU L4 L5
Mem File Memory

Reg
File
12

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