Modeling of Local Oxidation Processes
Introduction
• Isolation Processes in the VLSI Technology
• Main Aspects of LOCOS simulation
• Athena Oxidation Models
• Several Examples of LOCOS structures
• Calibration of LOCOS effects using VWF
• Field Oxide Thinning Effect
• Pad Oxide Punch Through Effect
• Integrated Topography and In-Wafer Simulation of Self-Aligned LOCOS/
Trench technology (SALOT)
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Isolation Processes in the VLSI Technology
• Separate devices in VLSI circuits should be effectively isolated from each
other
• One of the main aspects of miniaturization is shrinkage of isolation
areas without degradation of isolation characteristics (leakage current,
parasitic threshold
voltage, etc.)
• Review of various isolation technologies can be found in:
S.Wolf “Silicon Processing for the VLSI Era”, Vol.2, Chap.2. (Lattice Press, 1990)
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Isolation Processes in the VLSI Technology (con’t)
• LOCOS and its numerous variations
• Non-LOCOS Isolation
• Trench and refill
• Selective Epitaxy Growth (SEG)
• Silicon-On-Insulator (SOI)
• Combination methods: LOCOS with trench, SOI with LOCOS, etc.
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Main aspects of LOCOS Simulation
• The oxide thickness and shape
• The bird’s beak length and shape
• The redistribution of the channel-stop dopant
• Stress induced in silicon during the LOCOS process
• Athena successfully handles all four aspects for variety of LOCOS structures
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Athena Oxidation Models
• Compress (stresses are not taken into account)
• Can be used for all cases but may fail to accurately predict shape and dimensions of
LOCOS
• Viscous (Stress in oxide and nitride are included)
• Capable of predicting actual bird’s beak shapes and stress induced effects
• Needs serious parameter calibration efforts
• Much slower than compress method
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Examples of LOCOS Structures
• Semi-recessed and fully recessed LOCOS (Figure 1)
• Poly-buffered LOCOS (PBL) (Figure 2 and 3)
• Sealed-Interface Local Oxidation (SILO) (Figure 4)
• Sidewall-Masked Isolation (SWAMI) (Figure5 and 6)
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Examples of LOCOS Structures
Figure 1. Semi-recessed and fully recessed LOCOS.
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Examples of LOCOS Structures
Figure 2. Poly-buffered LOCOS initial and final structure.
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Examples of LOCOS Structures
Figure 3. Poly-buffered LOCOS.
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Examples of LOCOS Structures
Figure 4. Initial and final SILO structure.
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Examples of LOCOS Structures
Figure 5. Initial and final SWAMI structure.
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Examples of LOCOS Structures
Figure 6. Stresses in the SWAMI process.
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Calibration of LOCOS Effects Using VWF
• Several effects typical in LOCOS cannot be simulated without taking
stress into account
• Decreasing of bird’s beak length (BBL) with increasing of nitride thickness
• Thinning of isolation oxide with narrowing of mask window
• Pad-oxide punch through for narrow patterned nitride
• Global calibration of the model parameters using VWF is needed to
predict these effects for different combination of process parameters
(e.g.. temperature, nitride thickness and width, pad oxide thickness)
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Calibration of LOCOS Effects Using VWF (con’t)
• Some calibration results were published in “Simulation Standard”,
August, 1995
• Figure 7 shows target parameters which can be used in calibration
• Calibration parameters include
• Mechanical properties of oxide and nitride: viscosity, Young modulus, etc.
• Empirical parameters of stress-dependent model:
• Vd - activation volumes for oxidant diffusivity
• Vc - activation volume for viscosity
• Vr - activation volume for oxidation rate
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Geometrical parameters of Birds Beak.
Figure 7. Geometrical parameters of Birds Beak.
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Calibration of LOCOS Effects Using VWF (con’t)
• It was found by independent experiments that temperature dependence of
oxide and nitride viscosity could be presented as follows
material oxide visc.0=5.1 visc.E=3.48!
material nitride visc.0=5.96e5 visc.E=2.5625!
• Response Surface Models for normalized nitride deflection and
normalized BBL were build using a structural Design of Experiment
• Split parameters were oxidation temperature T, nitride thickness Tnit, as
well as model parameters Vd, Vc, and Vr
• One of the Response Surface Model (RSM) sections is shown in Figure 8
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RSM for Normalized Bird’s Beak Length
Figure 8. RSM for normalized Bird’s beak length.
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Calibration of LOCOS Effects Using VWF (con’t)
• The following shows how BBL and nitride deflection depend on nitride
thickness
• It is seen that the RSM simulation results obtained with default model
parameters do not match experimental points
• VWF Production Tools allow to manual variations of the input parameters
of the RSM with instant graphics of the output.
• Figure 10 shows that even using manual calibration much better
agreement with experimental points could be achieved
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Regression Model Overlay
Figure 9. Default Values of Viscouse model parameters.
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Regression Model Overlay
Figure 10. Optimized Values of Viscouse model parameters.
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Field Oxide Thinning Effect
• Higher chip density of modern ULSI technology demands shrinkage of
isolation areas
• The field oxide thinning effect shown in Figure 11 brings about increasing
concern to technology designers
• It is seen that the narrower nitride window the more stress-induced
retardation of the oxidation rate occurs in the center of the field area
• Figure 12 shows that simulation accurately predicts this effect
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Field Oxide Thinning Effect
Figure 11. Field oxide thinning effect.
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Field Oxide Thinning Effect
Figure 12. Field oxide thinning effect for different nitride thicknesses. Experiment for nitride
thickness 0.1 micron (P.Coulman et.al., Proc. of 2nd Int. Symp. on VLSI Sci. & Tech., p.759, 1989.)
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Pad Oxide Punch-through Effect
• It was found experimentally that bird’s beak deflection is quite sensitive
to patterned nitride width
• It has a minimum when nitride width decreased to ~0.6 microns and then
suddenly increases when nitride width decreases further
(Figures 13 and 14)
• This effect could be explained as follows
• The highest stresses are built where the highest angle (or curvature) of deflection occurs
• These stresses retard the local oxidation process
• When oxidation continues the position of maximum stresses moves toward center of the
nitride
• In case of a narrow nitride the stresses are overcome by oxidant diffusion at some
moment after which stresses diminish rapidly and oxide is growing without any obstacles
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Pad Oxide Punch-Through Effect
Figure 13. Pad oxide punch-through effect.
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Pad Oxide Punch-Through Effect
Figure 14. Normalized nitride deflection versus patterned nitride width for
different nitride thicknesses (1000 C, 90 minutes, pad oxide 0.015 micron).
Experiment: P.U. Kendale et.al., IEDM Tech. Digest, p.479, 1993.
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Integrated Topography and In-Wafer Simulation of Self-Aligned
LOCOS Trench (SALOT) Technology
• STEP 1. The initial stack of pad oxide (11nm)/ polysilicon(70 nm) /Silicon
nitride (200 nm) is defined the same way as for conventional PBL process
• STEP 2. The width of the narrow field region is only 0.3 microns, therefore
stress-dependent viscous oxidation model is used here to predict the
Field Oxide Thinning Effect for this structure. The mesh used and result of
the oxidation are shown in Figure 15
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SALOT Technology: PBL Isolation
Figure 15. PBL isolation.
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Integrated Topography and In-Wafer Simulation of SALOT
Technology (con’t)
• To accurately simulate subsequent trench formation steps structure was
completely re-meshed using DevEdit (Figure 16)
• STEP 3. Polysilicon spacers were formed using CVD deposition with
subsequent anisotropic etching.
• STEP 4. To achieve self-aligned trench only in the narrow region other
areas were masked off (Figure 17)
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SALOT Technology: Trench Grid Formation
Figure 16. Grid prepared for trench formation.
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SALOT Technology: Poly-Si Spacer and Trench Masking
Figure 17. Poly-Si spacer and trench masking.
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Integrated Topography and In-Wafer Simulation of SALOT
Technology (con’t)
• STEP 5: plasma etching of exposed LOCOS (Figure 18). It was simulated
using the plasma etching module of Athena
• The module calculates energy-angular distribution of ions emerging from
plasma using a Monte Carlo calculation. The etch rate in each point is
proportional to the ion flux with shadowing and mask erosion taken into
account
• The width and shape of etch opening depend on plasma characteristics
(temperature, density, etc) as well as on position and shape of the
spacers
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SALOT Technology: After Anisotropic Etching of LOCOS
Figure 18. After anisotropic etching of LOCOS.
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Integrated Topography and In-Wafer Simulation of SALOT
Technology (con’t)
• STEP 6 is photo mask removal and plasma etching of the 300 nm trench
in silicon (Figure 19)
• In order to illustrate advanced capabilities of Athena a sidewall implant
step has be added (Figure 20)
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SALOT Technology: Plasma Etching of Trench
Figure 19. Plasma etching of trench.
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SALOT Technology: Side Wall Implantation
Figure 20. Grid adaptation for angled implant into trench.
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Integrated Topography and In-Wafer Simulation of SALOT
Technology (con’t)
• STEP 7. Thermal oxidation of the trench with moderate diffusion of just
implanted impurity (Figure 21)
• STEP 8. The trench is filled with oxide. Simple conformal deposition was
used in the simulation (Figure 22)
• STEP 9. Planarization of the field oxide SALOT process using Chemical
Mechanical Polishing (CMP). Silicon nitride is served as a masking layer
• This step was simulated using CMP module of Athena with polishing rate
of nitride 3 times smaller than that of oxide. (Figure 23)
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SALOT Technology: Trench Oxidation
Figure 21. Grid adaptation after trench oxidation.
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SALOT Technology: Trenched Filled with CVD Oxide
Figure 22.Trenched filled with CVD oxide.
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SALOT Technology: Planarization Using CMP
Figure 23. Planarization using CMP.
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Conclusion
• Athena could be successfully used for simulation of different LOCOS
geometries
• Stress-dependent model should be used to predict some small CD effects
• The model should be extensively calibrated
• It is shown that VWF could be successfully used for such calibration
Modeling of Local Oxidation Processes - 42 -
