IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO.

7, JULY 2006 573

Fabrication and Characterization of Field-Plated

Buried-Gate SiC MESFETs
Kristoffer Andersson, Mattias Südow, Per-Åke Nilsson, Einar Sveinbjörnsson, Hans Hjelmgren, Member, IEEE,
Joakim Nilsson, Johan Ståhl, Herbert Zirath, and Niklas Rorsman

Abstract—Silicon carbide (SiC) MESFETs were fabricated us- have been presented for AlGaN/GaN HEMT technology. The
ing a standard SiC MESFET structure with the application of the FP reduces the peak electric field at the gate, enabling both
“buried-channel” and field-plate (FP) techniques in the process. higher operating breakdown voltage [5] and reduced disper-
FPs combined with a buried-gate are shown to be favorable con-
cerning output power density and power-added efficiency (PAE), sion [6], leading to higher output power densities and PAE.
due to higher breakdown voltage and decreased output conduc- Physical simulations have indicated similar effects for SiC
tance. A very high power density of 7.8 W/mm was measured MESFETs [7].
on-wafer at 3 GHz for a two-finger 400-µm gate periphery SiC This letter describes the process and results for SiC
MESFET. The PAE for this device was 70% at class AB bias. MESFETs fabricated using a standard SiC MESFET structure
Two-tone measurements at 3 GHz ± 100 kHz indicate an optimum
FP length for high linearity operation. with the application of the buried-gate (or “buried-channel”)
and integrated FP techniques to SiC MESFET fabrication.
Index Terms—Buried-gate, field-plate (FP), microwave power,
silicon carbide (SiC) MESFET.
II. D EVICE F ABRICATION
I. I NTRODUCTION The MESFETs were made on 4H-SiC semi-insulating wafers
with a buffer/channel/cap epi stack grown by Cree, Inc. The
T HERE ARE increasing demands for higher RF power,
more efficiency, broader bandwidths, and smaller more
compact devices for communication and radar applica-
buffer is p-doped (NA = 5 · 1015 cm−3 ) and 0.34 µm thick.
The channel and cap layers are n-doped (ND = 2.7 · 1017 and
tions. Silicon carbide (SiC) has high thermal conductivity 1.6 · 1019 cm−3 ) with thicknesses of 0.34 and 0.33 µm, respec-
(3.5 W/cm · K), high breakdown voltage (3 MV/cm), and high tively. Details of the process have been described previously
electron saturation velocity (2.1 · 107 cm/s), making it suitable [8]. In short, the process includes mesa etching for channel
for these applications. definition and device isolation, Ni contacts, Ti/Pt/Au gates,
During the development of SiC MESFET technology, sev- Au pads, passivation, air bridges, and an optional via-hole
eral trapping problems have been identified. These trapping grounding step. Gate patterning is made using e-beam lithog-
effects result in lower output power density and power-added raphy, whereas the other steps are patterned with standard
efficiency (PAE) than expected. Previously, the vanadium- contact photolithography. Etching is made using an inductively
doped semi-insulating SiC substrate attracted much attention coupled plasma (ICP) with a fluorine-based plasma. MESFETs
in explaining the deterioration of the SiC MESFET microwave with a gate length of 400 nm and varying gate peripheries
performance [1]. The larger part of the problems associated were made.
with the substrate was solved by the introduction of vanadium- To create the FP structure used in this work, the gate areas
free (high-purity) substrates. Recently, the attention has shifted of the transistors were made as follows: First, a thermal oxide,
more toward surface traps, which cause gate-lag effects. In [2], with a thickness of 1400 Å, was grown on top of the channel
a buried-gate approach was shown to result in less trapping, area. An opening where the gate should be placed was etched
resulting in a reduction in current instability and higher output through this oxide and continued down into the SiC channel.
power density. In [3], an undoped spacer layer was shown This step defined the gate length, and the drain current of the
to give nearly ideal gate-lag ratio, resulting in improved mi- device could be determined by the etch depth into the SiC
crowave power performance. channel [3]. Second, the Ti/Pt/Au gate was deposited on top
Field-plates (FPs) are used in Si and III–V technologies [4] to of the opening, and an overlap toward the drain side gave an FP.
enhance the breakdown of the devices. Recently, similar studies The FP length was varied from 50 to 450 nm. The overlap of
the gate on the source side is 50 nm for all devices. A cross
Manuscript received February 24, 2006; revised April 19, 2006. This work section of the device is shown in Fig. 1. To get the correct
was supported by the Swedish Agency for Innovation Systems (VINNOVA). etch depth, the current level between source and drain contacts
The review of this letter was arranged by Editor K. Kornegay. was measured during the etching process. The etching was
K. Andersson, M. Südow, P.-Å. Nilsson, E. Sveinbjörnsson, H. Hjelmgren,
H. Zirath, and N. Rorsman are with the Microwave Electronics Labora- then stopped at a specific current value, which was determined
tory, Chalmers University of Technology, 412 96 Göteborg, Sweden (e-mail: from physical device simulations with Synopsys/ISE-TCAD.
kristoffer.andersson@chalmers.se). The simulations began with finding the etch depth that would
J. Nilsson and J. Ståhl are with the Ericsson Microwave Systems AB, 431 84
Mölndal, Sweden. give the targeted pinch-off voltage and drain current of the
Digital Object Identifier 10.1109/LED.2006.877285 completely processed transistor. This etch depth was then used
0741-3106/$20.00 © 2006 IEEE

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 574 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 7, JULY 2006

TABLE I
EQUIVALENT CIRCUIT PARAMETERS (ECPS), AVERAGE TRANSIT
FREQUENCY (fT ), MAXIMUM FREQUENCY OF OSCILLATIONS (fmax ),
OUTPUT POWER AT 1- AND 3-dB COMPRESSIONS (P1 dB AND P3 dB ),
SMALL SIGNAL GAIN (Gp0 ), AND MAXIMUM PAE (PAEmax ) FOR
THE D IFFERENT FP L ENGTHS FOR A T WO -F INGER 400-µm G ATE
PERIPHERY SiC MESFET AT VDS = 60 V AND VGS = −17 V.
THE ECPS ARE EXTRACTED FROM S-PARAMETERS AT
VDS = 40 V AND VGS AT MAXIMUM fT . ALL VALUES
ARE AVERAGES TAKEN FROM FOUR DEVICES

Fig. 1. IDS versus VDS for a two-finger 100-µm gate periphery SiC
MESFET. The top curve is for VGS = 0 V, and the step is −4 V. The inset
shows a cross section of the buried-channel and FP SiC MESFET.

in the simulations to determine the corresponding current level

between drain and source, thus the etch stop criteria. Although
this method requires a carefully calibrated simulation input
desk, it has several advantages; e.g., we do not have to know
the exact etching rate and thickness of the channel layer.

III. M EASUREMENTS
A. DC
Both static and dynamic current–voltage (I–V ) were mea-
sured. The saturated drain-to-source current is 370 mA/mm
with a pinch voltage Vp of −18 V (Fig. 1). The dc
transconductance gm is 31 mS/mm. The gate-lag ratio, de-
fined as IDSS(pulsed) /IDSS(DC) , was 98% and 86% at VDS = Fig. 2. Pout , Gp , and PAE versus Pin for a two-finger 400-µm gate pe-
riphery SiC MESFET. The device was biased in deep class AB (VDS = 65 V,
1 and 10 V, respectively, when pulsing from VDS = 15 V and VGS = −19 V).
VGS below Vp . The 0.5-µs-wide pulses were separated by 1 ms.
Gate–drain reverse breakdown measurements were per-
by vacuum. Measured transistors had a gate periphery of 2 ×
formed for the different FP sizes. It increased from 190 to
200 µm2 and 10 × 100 µm2 . The load and source impedances
> 200 V for FP lengths of 50 and 150 nm, respectively.
were tuned for maximum output power and a Gp of 12–15 dB,
respectively.
B. S-Parameters The highest continuous-wave (CW) output power density
S-parameters were measured on-wafer from 50 MHz to (7.8 W/mm) was measured for a two-finger 400-µm gate pe-
45 GHz for several groups of MESFETs. Measured transis- riphery SiC MESFET with an FP of 450 nm at VDS = 65 V
tors had a gate periphery of 2 × 200 µm. From measured and VGS = −19 V with a maximum PAE of 70% (Fig. 2).
S-parameters, extrinsic fT and fmax [maximum available gain For a 1-mm MESFET with an FP of 250 nm, the maximum
(MAG = 1)] were calculated (Table I). The FP causes a re- CW output power density was 5.2 W/mm at VDS = 65 V and
duction in high-frequency performance due to the increased VGS = −17 V with a PAE of 36%.
gate associated capacitances. However, the negative impact of The influence of FP length on microwave power performance
FPs on fT is almost negligible (less than 8% reduction). fmax was investigated by load–pull and power sweep measurements.
is somewhat higher for wider FPs. This is mainly due to a The measurements were performed in class AB at a VDS of
reduction of output conductance for wide FPs (Table I). 40–65 V. The average (from four device groups) maximum
output power at 1- and 3-dB compressions (P1 dB and P3 dB ),
small signal gain (Gp0 ), and maximum PAE (PAEmax ) for the
C. Microwave Power Measurements
different FPs are presented in Table I. The FP is favorable for
Load–pull and power sweep measurements were performed all parameters.
on-wafer at 3 GHz with a temperature-controlled chuck (Sum- To verify the results, measurements on the identical ten-
mit 10 000 and Temptronic). The chuck had a temperature of finger 1-mm gate periphery SiC MESFET were performed in
25 ◦ C. The wafer (thickness 360 µm) has a backside metal- two different load–pull systems [at Chalmers University and
ization of Ti/Au. The wafer is only mounted to the heat sink Ericsson Microwave Systems AB (EMW)]. At EMW, CW

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 ANDERSSON et al.: FABRICATION AND CHARACTERIZATION OF FIELD-PLATED BURIED-GATE SiC MESFETs 575

lengths were fabricated and characterized. The output power

density at 1-dB compression increased from 5.0 to 6.0 (20%),
and the maximum PAE increased from 56% to 66% when the
FP length increased from 50 to 450 nm. These improvements
are explained by the increase in breakdown voltage and de-
crease in output conductance. The combination of buried-gates
and FPs resulted in a very high power density of 7.8 W/mm at
3 GHz. This is, to our knowledge, among the highest reported
output power densities for small SiC MESFETs. The PAE for
this device was 70% at class AB bias. Two-tone measurements
at 3 GHz ± 100 kHz indicate an optimum FP length for high
linearity operation. An OIP3 of 39.8 dBm was measured for
a for a two-finger 400-µm gate periphery SiC MESFET at
VDS = 60 V.

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