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VHDL Coin Change System Design

The document describes a VHDL code for a coin changer machine. It contains an entity declaration for the coin changer with inputs for a clock, button, coin insertion, and coin value and outputs for change and returned coins. It also contains the architecture for the coin changer which defines 3 states - storage, selection, and expulsion. It uses processes to update the state based on inputs and outputs based on the current state. A testbench is also included which instantiates the coin changer component and provides test inputs to simulate operation.

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Manuel Ruiz
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45 views4 pages

VHDL Coin Change System Design

The document describes a VHDL code for a coin changer machine. It contains an entity declaration for the coin changer with inputs for a clock, button, coin insertion, and coin value and outputs for change and returned coins. It also contains the architecture for the coin changer which defines 3 states - storage, selection, and expulsion. It uses processes to update the state based on inputs and outputs based on the current state. A testbench is also included which instantiates the coin changer component and provides test inputs to simulate operation.

Uploaded by

Manuel Ruiz
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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SOURCE – CAMBIO_MONEDA

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity cambio_moneda is

Port (clk, boton, moneda_ins: IN STD_LOGIC;

moneda: in STD_LOGIC_VECTOR(4 downto 0);

cambio: out STD_LOGIC;

vuelta: out STD_LOGIC_VECTOR(4 downto 0));

end cambio_moneda;

architecture Behavioral of cambio_moneda is

type estado is (almacenamiento, seleccion, expulsion);

signal ep, pe: estado;

signal cantidad: std_logic_vector(4 downto 0):="00000";

constant precio: std_logic_vector(4 downto 0):="10010";

begin

P1:process(moneda_ins, boton, ep)

begin

case ep is

when almacenamiento =>

cambio <= '0';

vuelta <= "00000";

cantidad <= cantidad + moneda;

if (boton = '1')then pe<=seleccion;


end if;

when seleccion =>

vuelta <= cantidad-precio;

if(cantidad >= precio) then pe<=expulsion;

end if;

when expulsion =>

cambio <='1';

cantidad <="00101";

pe <= almacenamiento;

end case;

end process;

P2:process(clk)

begin

if(clk = '1' and clk'event)then ep <= pe; end if;

end process;

end Behavioral

Testbench

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.std_logic_unsigned.all;

use IEEE.numeric_std.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;
entity cambio_monedaTB is

-- Port ( );

end cambio_monedaTB;

architecture Behavioral of cambio_monedaTB is component cambio_moneda is

PORT( clk : IN std_logic;

boton : IN std_logic;

moneda_ins: IN std_logic;

moneda : IN std_logic_vector(4 downto 0);

cambio : OUT std_logic;

vuelta : OUT std_logic_vector(4 downto 0));

end component

-- Entradas

signal clk : std_logic := '0';

signal boton, moneda_ins : std_logic := '0';

signal moneda : std_logic_vector(4 downto 0) := (others=>'0')

-- Salidas

signal cambio1 : std_logic:='0';

signal vuelta : std_logic_vector(4 downto 0):="00000";

constant periodo: time:=40 ns;

begin

uut: cambio_moneda

PORT MAP(clk => clk,

boton => boton,

moneda_ins => moneda_ins,

moneda => moneda,

cambio => cambio1,

vuelta => vuelta);

clk <= not clk after periodo/2;

tb: process

begin

moneda <= "00101";

moneda_ins <= not moneda_ins;

wait for periodo;

end process;

tb1: process

begin
boton <='0';

wait for periodo*1.2;

boton <='1';

wait for periodo;

end process;

end Behavioral;

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