PD - 94712

IRFR3709Z
IRFU3709Z
Applications HEXFET® Power MOSFET
l High Frequency Synchronous Buck
Converters for Computer Processor Power VDSS RDS(on) max Qg
l High Frequency Isolated DC-DC
30V 6.5m: 17nC
Converters with Synchronous Rectification
for Telecom and Industrial Use
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current D-Pak I-Pak
IRFR3709Z IRFU3709Z

Absolute Maximum Ratings

Parameter Max. Units
VDS Drain-to-Source Voltage 30 V
VGS Gate-to-Source Voltage ± 20
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 86 f A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 61 f
IDM Pulsed Drain Current c 340
PD @TC = 25°C Maximum Power Dissipation 79 W
PD @TC = 100°C Maximum Power Dissipation 39
Linear Derating Factor 0.53 W/°C
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case)

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.9 °C/W
RθJA Junction-to-Ambient (PCB Mount) g ––– 50
RθJA Junction-to-Ambient ––– 110

Notes  through … are on page 11

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IRFR/U3709Z
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
BVDSS Drain-to-Source Breakdown Voltage 30 ––– ––– V VGS = 0V, ID = 250µA
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 22 ––– mV/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 5.2 6.5 mΩ VGS = 10V, ID = 15A e
––– 6.5 8.2 VGS = 4.5V, ID = 12A e
VGS(th) Gate Threshold Voltage 1.35 1.80 2.25 V VDS = VGS, ID = 250µA
∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -5.6 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA VDS = 24V, VGS = 0V
––– ––– 150 VDS = 24V, VGS = 0V, TJ = 150°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
gfs Forward Transconductance 51 ––– ––– S VDS = 15V, ID = 12A
Qg Total Gate Charge ––– 17 26
Qgs1 Pre-Vth Gate-to-Source Charge ––– 4.7 ––– VDS = 15V
Qgs2 Post-Vth Gate-to-Source Charge ––– 1.6 ––– nC VGS = 4.5V
Qgd Gate-to-Drain Charge ––– 5.7 ––– ID = 12A
Qgodr Gate Charge Overdrive ––– 5.0 ––– See Fig. 16
Qsw Switch Charge (Qgs2 + Qgd) ––– 7.3 –––
Qoss Output Charge ––– 10 ––– nC VDS = 16V, VGS = 0V
td(on) Turn-On Delay Time ––– 12 ––– VDD = 16V, VGS = 4.5V e
tr Rise Time ––– 12 ––– ID = 12A
td(off) Turn-Off Delay Time ––– 15 ––– ns Clamped Inductive Load
tf Fall Time ––– 3.9 –––
Ciss Input Capacitance ––– 2330 ––– VGS = 0V
Coss Output Capacitance ––– 460 ––– pF VDS = 15V
Crss Reverse Transfer Capacitance ––– 230 ––– ƒ = 1.0MHz

Avalanche Characteristics
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy d ––– 100 mJ
IAR Avalanche Current c ––– 12 A
EAR Repetitive Avalanche Energy c ––– 7.9 mJ

Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 86 f MOSFET symbol D

(Body Diode) A showing the

ISM Pulsed Source Current ––– ––– 340 integral reverse G

(Body Diode)c p-n junction diode.

S

VSD Diode Forward Voltage ––– ––– 1.0 V TJ = 25°C, IS = 12A, VGS = 0V e
trr Reverse Recovery Time ––– 29 44 ns TJ = 25°C, IF = 12A, VDD = 15V
Qrr Reverse Recovery Charge ––– 25 37 nC di/dt = 100A/µs e
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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10000 10000
VGS VGS
TOP 10V TOP 10V
5.0V 5.0V
1000 4.5V 4.5V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

3.5V 1000 3.5V
3.0V 3.0V
2.7V 2.7V
100 2.5V 2.5V
BOTTOM 2.25V BOTTOM 2.25V
100

10

10
1
2.25V
2.25V 1
0.1
20µs PULSE WIDTH 20µs PULSE WIDTH
Tj = 25°C Tj = 175°C
0.01 0.1
0.1 1 10 100 0.1 1 10 100

VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.0
RDS(on) , Drain-to-Source On Resistance

ID = 30A
VGS = 10V
ID, Drain-to-Source Current (Α)

100
1.5
(Normalized)

T J = 175°C
10

1.0
T J = 25°C
1

VDS = 15V
20µs PULSE WIDTH
0.1 0.5
0 1 2 3 4 5 6 7 8 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

vs. Temperature
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 IRFR/U3709Z

100000 6.0
VGS = 0V, f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED ID= 12A
C rss = C gd VDS= 24V

VGS, Gate-to-Source Voltage (V)

5.0
10000 C oss = C ds + C gd VDS= 15V
C, Capacitance(pF)

4.0
Ciss

1000 Coss 3.0

Crss
2.0
100

1.0

10 0.0
1 10 100 0 5 10 15 20 25
VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000 1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

100
T J = 175°C
100

10
100µsec

10
T J = 25°C
1 1msec
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse 10msec
0 1
0.0 0.5 1.0 1.5 2.0 2.5 0 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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100 2.5

90

VGS(th) Gate threshold Voltage (V)

Limited By Package
80 2.0
ID, Drain Current (A)

70

60 1.5
ID = 250µA
50

40 1.0

30

20 0.5

10
0.0
0
-75 -50 -25 0 25 50 75 100 125 150 175
25 50 75 100 125 150 175
T C , Case Temperature (°C) T J , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Fig 10. Threshold Voltage vs. Temperature
Case Temperature

10
Thermal Response ( Z thJC )

1 D = 0.50

0.20
0.10
0.1 0.05
R1
R1
R2
R2
R3
R3 Ri (°C/W) τi (sec)
τJ τC
0.02 τJ τ
0.810 0.000260
τ1 τ2 τ3
0.01 τ1 τ2 τ3 0.640 0.001697
Ci= τi/Ri 0.451 0.021259
0.01 SINGLE PULSE Ci= τi/Ri
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRFR/U3709Z
15V 450

EAS , Single Pulse Avalanche Energy (mJ)

ID
400
TOP 6.6A
L DRIVER
VDS
350 8.4A
BOTTOM 12A
300
RG D.U.T +
V
- DD
IAS A 250
VGS
20V
tp 0.01Ω
200

Fig 12a. Unclamped Inductive Test Circuit 150

100
V(BR)DSS
50
tp
0
25 50 75 100 125 150 175

Starting T J , Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

vs. Drain Current
LD
I AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD -

D.U.T
Current Regulator
Same Type as D.U.T. VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ

12V .2µF
.3µF
Fig 14a. Switching Time Test Circuit
+
V
D.U.T. - DS VDS
90%
VGS

3mA

10%
IG ID VGS
Current Sampling Resistors

td(on) tr td(off) tf
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
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 IRFR/U3709Z

Driver Gate Drive

D.U.T Period D=
P.W.
Period
+ P.W.

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance
D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚
-
„ +
Recovery
Current
Body Diode Forward
Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• ISD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

Id
Vds

Vgs

Vgs(th)

Qgs1 Qgs2 Qgd Qgodr

Fig 16. Gate Charge Waveform

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IRFR/U3709Z
Power MOSFET Selection for Non-Isolated DC/DC Converters

Control FET Synchronous FET

Special attention has been given to the power losses The power loss equation for Q2 is approximated
in the switching elements of the circuit - Q1 and Q2. by;
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the Ploss = Pconduction + Pdrive + Poutput
*
MOSFET, but these conduction losses are only about
one half of the total losses.

Power losses in the control switch Q1 are given

( 2
Ploss = Irms × Rds(on) )
by; + (Qg × Vg × f )
Q 
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput +  oss × Vin × f + (Qrr × Vin × f )
 2 
This can be expanded and approximated by;
*dissipated primarily in Q1.
Ploss = (Irms × Rds(on ) )
2

For the synchronous MOSFET Q2, Rds(on) is an im-

 Qgd   Qgs 2  portant characteristic; however, once again the im-
+I× × Vin × f  +  I × × Vin × f portance of gate charge must not be overlooked since
 ig   ig  it impacts three critical areas. Under light load the

+ (Qg × Vg × f )
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
 Qoss
+ × Vin × f  verse recovery charge Qrr both generate losses that
 2  are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
This simplified loss equation includes the terms Qgs2 MOSFETs’ susceptibility to Cdv/dt turn on.
and Qoss which are new to Power MOSFET data sheets. The drain of Q2 is connected to the switching node
Qgs2 is a sub element of traditional gate-source of the converter and therefore sees transitions be-
charge that is included in all MOSFET data sheets. tween ground and Vin. As Q1 turns on and off there is
The importance of splitting this gate-source charge a rate of change of drain voltage dV/dt which is ca-
into two sub elements, Qgs1 and Qgs2, can be seen from pacitively coupled to the gate of Q2 and can induce
Fig 16. a voltage spike on the gate that is sufficient to turn
Qgs2 indicates the charge that must be supplied by the MOSFET on, resulting in shoot-through current .
the gate driver between the time that the threshold The ratio of Qgd/Qgs1 must be minimized to reduce the
voltage has been reached and the time the drain cur- potential for Cdv/dt turn on.
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
Figure A: Qoss Characteristic
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 IRFR/U3709Z
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)

2.38 (.094)
6.73 (.265) 2.19 (.086)
6.35 (.250) 1.14 (.045)
0.89 (.035)
-A-
5.46 (.215) 1.27 (.050) 0.58 (.023)
5.21 (.205) 0.88 (.035) 0.46 (.018)

6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235) 10.42 (.410)
1.02 (.040) 9.40 (.370) LEAD ASSIGNMENTS
1.64 (.025) 1 2 3
1 - GATE
0.51 (.020) 2 - DRAIN
-B- MIN. 3 - SOURCE
1.52 (.060) 4 - DRAIN
1.15 (.045)
0.89 (.035)
3X
0.64 (.025) 0.58 (.023)
1.14 (.045) 0.46 (.018)
2X 0.25 (.010) M A M B
0.76 (.030)

2.28 (.090) NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
4.57 (.180) 2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).

D-Pak (TO-252AA) Part Marking Information

Notes: T his part marking information applies to devices produced before 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 9U1P INT ERNAT IONAL DAT E CODE
RECTIFIER IRFU120
YEAR = 0
LOGO 016
WEEK = 16
9U 1P

AS S EMBLY
LOT CODE

Notes : T his part marking information applies to devices produced after 02/26/2001

EXAMPLE: T HIS IS AN IRFR120

PART NUMBER
WIT H AS S EMBLY INT ERNAT IONAL
LOT CODE 1234 RECT IFIER IRFU120 DAT E CODE
AS S EMBLED ON WW 16, 1999 LOGO 916A YEAR 9 = 1999
IN T HE AS S EMBLY LINE "A" 12 34 WEEK 16
LINE A
AS S EMBLY
LOT CODE

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IRFR/U3709Z
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)

6.73 (.265) 2.38 (.094)

6.35 (.250) 2.19 (.086)
-A-
1.27 (.050) 0.58 (.023)
5.46 (.215)
0.88 (.035) 0.46 (.018)
5.21 (.205)
LEAD ASSIGNMENTS
4 1 - GATE
6.45 (.245) 2 - DRAIN
5.68 (.224) 3 - SOURCE
1.52 (.060) 6.22 (.245) 4 - DRAIN
1.15 (.045) 5.97 (.235)

1 2 3

-B- NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2.28 (.090) 9.65 (.380) 2 CONTROLLING DIMENSION : INCH.
1.91 (.075) 8.89 (.350) 3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).

1.14 (.045) 1.14 (.045)

3X 0.89 (.035)
0.76 (.030) 3X 0.89 (.035)
0.64 (.025)

2.28 (.090) 0.25 (.010) M A M B 0.58 (.023)

0.46 (.018)
2X

I-Pak (TO-251AA) Part Marking Information

Notes : T his part marking information applies to devices produced before 02/26/2001

EXAMPLE: T HIS IS AN IRFR120

INTERNATIONAL DAT E CODE
WIT H AS S EMBLY
RECT IFIER IRFU120
LOT CODE 9U1P YEAR = 0
LOGO 016
WEEK = 16
9U 1P

AS S EMBLY
LOT CODE

Notes : T his part marking information applies to devices produced after 02/26/2001

EXAMPLE: T HIS IS AN IRFR120 PART NUMBER

INT ERNAT IONAL
WIT H AS S EMBLY
RECT IFIER IRFU120 DAT E CODE
LOT CODE 5678
LOGO 919A YEAR 9 = 1999
AS S EMBLED ON WW 19, 1999
56 78 WEEK 19
IN T HE AS S EMBLY LINE "A"
LINE A
AS S EMBLY
LOT CODE

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 IRFR/U3709Z
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Notes:
 Repetitive rating; pulse width limited by „ Calculated continuous current based on maximum allowable
max. junction temperature. junction temperature. Package limitation current is 30A.
‚ Starting TJ = 25°C, L = 1.4mH, RG = 25Ω, … When mounted on 1" square PCB (FR-4 or G-10 Material).
IAS = 12A. For recommended footprint and soldering techniques refer to
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%. application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/03
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/