ELE 302T

ELECTRONIC
MANUFACTURING AND
PROTOTYPING

Lecture 3-6:
PACKAGING
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2
Microsystem Products

3
 4
Microsystem technologies
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6
 Introduction to Electronic Packaging
• Electronic Packaging:

• Housing and interconnection of integrated circuits

to form electronic systems

• Electronic Packaging must provide

• Circuit support and protection

• Heat dissipation

• Signal distribution

• Manufacturability and serviceability

• Power distribution 7
 Functions of the Package

• Packages protect chip from damaging external influences like:

Moisture
Dust
Vibration
Shock
Lightning
Magnets, etc.

• Lead frame allows electrical signals

to be sent to semiconductor devices and
to be received from semiconductor devices

8
Functions of the Package

• Packages effectively release the heat generated by the

chip during its operation.

• Packages allow for enlargement of terminals size that

makes the chips much easier to handle.

9
Hierarchy of Interconnection Levels
• Level 0
• Gate-to-gate interconnections on the silicon die
• Level 1
• Connections from the chip to its package
• Level 2
• PCB, from component to component or to external
connector
• Level 3
• Connections between PCBs, including backplanes or
motherboards
• Level 4
• Connections between sub-assemblies, for example a rack
• Level 5
• Connections between physically separate systems, for
example an Ethernet LAN 10
 Two Types of Packages for VLSI Devices
• Hermetic Ceramic Packages:
• Chip resides in a vacuum tight enclosure decoupled from
external environment.
• Usually designed for high performance applications
• Some cost penalties might be there

11
 Two Types of Packages for VLSI Devices
• Plastic Packages:
• Chip is encapsulated with epoxy based resin materials
• Not completely decoupled from external environment
• Extremely cost competitive
• Popularity persists due to rapid advances in plastic
technology

12
Three Breakthroughs in Chip Packaging
Technology

13
Through (Thru) Hole Mounting

14
Through-Hole Benefits and Drawbacks
• The pins of the components go through the
previously drilled PCB holes
• Benefits
• Easy to solder, either automatically
(wave) or by hand
• Easy to de-solder and test
• Implement interconnections between
upper and lower layers (vias) in
non-plated hole technologies
• Drawbacks
• Signals must necessarily go through all
PCB layers
• Low density due to minimum pin
diameter and only one-sided mounting
15
Surface-Mount Technology (SMD)

16
SMD Benefits and Drawbacks
• Pins of the devices are mounted
directly onto the surface of the
PCB
• Benefits
• Much higher density: pins
can be thinner, devices can
be mounted on both sides of
the PCB, components do not
block signals in inner layers
• Higher degree in the
automation of the mounting
process
• Less parasitic inductance
and capacitance – Reduced
costs (½ to ¼) and size (¼ to
17
one tenth)
SMD Drawbacks

• Drawbacks

• Poor manual solderability and reparability

• Reliability issues due to thermal/mechanical stress

during soldering and operation (different thermal
expansion coefficients)

• Classic verification procedures no longer valid

18
Chip Scale Packages (CSP)

Chip Scale Package, or CSP, based on IPC/JEDEC

J-STD-012 definition, is a single-die, direct surface mountable
package with an area of no more than 1.2 times the original
die area

19
CSP Benefits and Drawbacks

• CSP is not a new mounting technology, is an evolution of

SMD
• The passive components surrounding the chips must also
be miniaturized (resistors, decoupling capacitors)
• Benefits
• CSP is the only way to achieve pervasive and ubiquitous
computing
• Further improvement in high-speed performance
• Drawbacks
• Difficulty of PCB fabrication and mounting due to minute
pin pitches (0.5 mm)
• Long-term reliability not studied
• Not serviceable 20
Three Packaging Technologies: Summary
Through Hole Surface Mount CSP / WLP

TSOP CSP/WLP
25 mil pitch Area array
Limited by perimeter 0.8 - 0.5 mm
leads Limited by
substrate
DIP wiring
100 mil pitch
Limited by through hole
spacing mil=(1/1000) inch=(1/40)mm 21
A Typical Low-Density SMD Process from
Silicon Wafer to Package

22
VLSI Assembly Technologies
Wafer Backgrinding
Die Preparation

Adhesive Die Bonding

Eutectic Die Bonding

Wire Bonding, TAB,

Flip Chip

Transfer molding

Ink Marking
Laser Marking

Deflash-Trim-Form
23
Singulate
First Step of Packaging: The Silicon Wafer
• The problem: How to ensure chip will
work before packaging it?
• Solution: Test it. But this is not easy to
achieve…
• Probing pads 150 µm away
• Area array pads
• Powering the chip
• Removing the heat it generates
• Testing it in a reasonable time
• Only a limited testing (if any) is usually
performed, full testing is done after
24
packaging
Wafer Preparation and Dicing
• Wafers are mounted on a laminating tape that adheres to
the back of the wafer.
• It holds the wafer throughout the dicing and the die
attaching process.

25
 Wafer Backgrinding

• Process of grinding the backside of the wafer to the correct

wafer thickness prior to assembly

• Wafers undergo a cleaning and surface lamination process

prior to backgrinding

• Grinding wheel parameters

• speed, spindle coolant water temperature and flow rate,

initial and final wafer thickness, and feed speeds

• Continuous washing of the wafer is done during

backgrinding to remove debris.

26
Wafer Preparation and Dicing
• Die-sawing machine using a diamond saw blade saws the
wafer into individual die/pellet on the adhesive backing tape.
• Deionized water and CO2 bubbles are dispensed on the wafer
to remove silicon dust/debris besides lubricating and cooling
down the blade

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Die Preparation
• Wafer Mounting:
• frame loading,
• wafer loading,
• application of tape to the
wafer and wafer frame
• cutting of excess tape
• unloading of mounted
wafer
• Wafer Saw:
• alignment, cutting by
resin-bonded diamond
wheel, cleaning
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Die Attach

• Die attach machine picks

up the “good” die utilizing
wafer mapping method
and deposit it on the
frame.
• Potting of die attach
materials like gold or
lead-tin based solder
wires or silver epoxy
paste on the frame is
required prior to die
bonding process.
29
Chip Attachment to the Package Substrate
• Die attachment compound should provide
• Electrical grounding
• Thermal dissipation
• There are three alternatives
• Soft Solder Die Attach: Uses a solder material as a wire
preform and melted onto the hot lead frame surface as a
liquid solder dot to bond the die to the lead frame.
• Epoxy Die Attach: Most commonly used method with
Ag-loaded polymers or polyimide or silicone-based
materials.
• Metal-filled glasses: Less used as high temperatures30
Chip-Package Connection:
Wire Bonding
• Connections are made from the
chip to the pad frame via thin wires
• Typically 100x100 µm metal
pads on 200 µm pitch
• Mechanical bonding of one pin
at a time (sequential)
• Wires are made of low resistivity
alloys or doped metals
• Gold and aluminum
• Copper and silver
• Typically 25 µm diameter for
logic devices 31
Die Bonding
• Process of attaching Si chip
to the die pad or die cavity of
the support structure.
• Adhesive Die Attach:
• Uses adhesives such as D/A adhesive as the grainy material
polyimide, epoxy and between die & die pad
silver-filled glass as die
attach material
• Eutectic Die Attach:
• Uses a eutectic alloy to
attach the die to the
cavity.
Normal Eutectic Die Attach and with
• Au-Si eutectic alloy is Balling
used most commonly eutectic alloy - melts & freezes at temp lower
32
than individual melting point
Die Interconnection: Wire Bonding

• The wire is generally made

up of one of the following:

• Gold

• Aluminum

• Copper

• Two main classes of wire

bonding:

• Ball bonding

• Wedge bonding
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Wire Bonding (Ball-Bonding)
• A gold ball is first formed by
melting the end of the wire.

• Free-air ball brought into

contact with the bond pad

• Adequate amounts of
pressure, heat, and ultrasonic
forces are then applied.

• Wire is run to the

corresponding finger of the
lead-frame,

• Forms a gradual arc or "loop"

between the bond pad and
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the lead-finger
 Wire Bonding
• Either Au or Al
wires are used
depending on
application.
• Bonded one at a
time, wire is fed
through a
ceramic capillary.
• With a good
combination of
temperature and
ultrasonic energy,
a good metalized
wire bond is
formed.
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Wire Bonding (Wedge Bonding)

• A clamped wire is brought in

contact with the bond pad.

• Ultrasonic energy and

pressure are applied.

• Wire is then run to the

corresponding lead finger,
and again pressed.

• Second bond is again formed

by applying ultrasonic energy
to the wire
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 Drawbacks of Wire Bonding

• Slow process
• One pin at a time
• Speeds from 4 to 10 wires
per second
• Pads are limited to the chip
periphery
• Low pad density and
reduced pad pitch
• Up to approx 500 pads
• Electrical limitations
• High inductance (~1nH) of
wires (~10nH plus pins)
• Crosstalk between
adjacent wires 37
Chip-Package Connection: TAB
• Tape automated bonding
• Interconnections are patterned on a multilayer polymer
tape
• Tape is positioned above the `bare die' so that the metal
tracks (on the polymer tape) correspond to the bonding
sites on the die
• The bare chip is then encapsulated ("glob topped") with
epoxy or plastic.

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Tape Automated Bonding (TAB)

• Advantages over wire

bonding

• Smaller and closer pads:

higher density, up to 850
pins

• Better electrical
characteristics

• Faster procedure but

more expensive
machinery

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Chip-Package Connection: Flip-Chip
• Chip is “soldered” to the package substrate using the solder
balls “bumps” that have been grown over the die pads

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• Controlled Collapse Chip Connection, C4
Flip Chip

• The term “Flip-chip” refers to

an electronic component or
semiconductor device that
can be mounted directly onto
a substrate, board, or carrier
in a ‘face-down’manner.

• Electrical connection is
achieved through conductive
bumps built on the surface of
the chips, which is why the
mounting process is
‘facedown’in nature.
41
Flip Chip –Advantages and Drawbacks
• Most preferred process for high end ICs due to high frequency
of operation, small size and/or many I/O pins
• Many advantages:
• Improved density: pad pitch and size is not better than in
wire bonding, but I/O pads can be distributed all over the
die, not just in the borders
• Reduced inductance (~0.1 nH) due to the elimination of
wires and better power/ground behavior
• Faster process, all the pads are soldered at the same time
• Some drawbacks
• Alignment is critical (and blind), although there is some
tolerance due to its self-alignment property
• Mechanical stress due to different thermal expansion 42
coefficients of the silicon and the package substrate
Molding
• To encapsulate the whole wire bonded die against exposure
to contamination and other physical damages.
• Mold compound is a combination of materials to form a
protective plastic to cover or encapsulate a semiconductor
device or integrated circuit.

43
Transfer or Injection Molding
• Molding compound is first
preheated prior to its loading into
the molding chamber
• After pre-heating, the mold
compound is forced by a hydraulic
plunger into the pot where it
reaches the melting temperature
and becomes fluid.
• The plunger continues to force the
fluid mold compound into the
runners of the mold chase.
• These runners serve as canals
where the fluid mold compound
travels until it reaches the mold
cavities, which contain the
leadframes or BGA substrates for
encapsulation. 44
Molding
• Cavities are filled up in a 'Christmas
tree' fashion

• In conventional equipment, cavities

that are nearest the runner gates
get filled up first. The first cavity
experiences the highest filling
velocity.

• The filling velocity decreases as the

first cavity is filled.

• Subsequent cavities are filled with

increasing velocities until the last
cavity, which has the second
highest filling velocity. 45
Molding
• Consists of resin, filler particles, typically crushed quartz or
quartz beads, a catalyst, flame retardants like organobromines
or organophosphates, an adhesion promoter and a mold
release agent in the form of a pressed cylinder
• Not a hermetic (air tight) seal, but provides protection against
moisture and corrosion.
• Upper and lower plates come together to form the mold cavity
for the semiconductor package.

46
Molding
• After the mold injection occurs, CURING of mold compound to
complete the polymer crosslinking that hardens the material is
needed.
• CURING is Done at temperatures around 175°C for an hour.
• Warpage: a problem during both mold injection and curing
• As package may contain one or more semiconductor chips,
lead frame, wires, solder bumps, polymer substrate, and also
ceramic materials, choice of mold compound that can best
hold these materials together is a critical factor.

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Solder Plating
• This step provides a layer of Tin Lead solder on the lead
frame for making easier the PCB assembly process.
• Lead free finishing with Tin Bismuth plating or Tin Copper
dipping can also be used.

48
 Package Sealing

• Process of encapsulating a hermetic package, usually by

capping or putting a lid over the base or body of the package

• Method of sealing is dependent on type of package.

• Ceramic DIPs, or cerdips, are sealed by topping the base of

the package with a cap using seal glass.

• Seal glass, like any glass, is a super-cooled liquid with very

high viscosity when cooled below its glass transition
temperature.

• A seal glass may be classified as vitreous or Devitrifying

(make hard or crystalline)
49
 Marking and Lead Trim/Form

• Coding process using a laser-based

machine that writes customer's
corporate and product identification
code on a packaged device.
• Finally the leads are cut and formed
mechanically to the specified shape

50
Marking
• Process of putting identification, traceability, and distinguishing
marks on the package of an IC.
• Most common Ink marking process for semiconductor
products is Pad printing.
• Pad printing is transferring an ink pattern from plate,
• Plate is a flat block with pattern depressions that are filled
with ink
• Pattern is transferred to the package using a silicone
rubber stamp pad.
• Laser marking refers to the process of engraving marks on the
marking surface using a laser beam.
• Many types of lasers: in the semiconductor industry:
• CO2 laser
• YAG. (neodymium-doped Yttrium Aluminium Garnet -
Y3Al5O12 laser
• Diode lasers 51
 Deflash/Trim/Form/Singulation (DTFS)
• Deflash - removal of flashes from the package of the newly
molded parts.
• Flashes are excess plastic material sticking out of the
package edges right after molding.
• Trim - cutting of the dambars* that short the leads together.
• Form - forming of the leads into the correct shape and
position.
• Singulation - cutting of the tie bars that attach the individual
units to the lead-frame, resulting in the individual separation
of each unit from the lead-frame.

*dambars: a feature on lead-frames, for plastic molded packages that blocks (dams) the flow of
52
the plastic compound to the external lead areas of the lead-frame during the molding cycle.
 Categories of Package Type
• ‰By material
• Ceramic
• Epoxy mounding compound (EMC) ‰
• By inner interconnection (chip-to-package)
• Wire bonding (W/B)
• Control collapsed chip connection(C4), flip-chip bonding(FC)
• Tab automatic bonding (TAB) ‰
• By outer interconnection (package-to-PCB)
• Pin through hole (PTH)
• Surface mount technology (SMT) ‰
• By chip carrier material
• Leadframe
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• Substrate
54
Through-hole package
Leads are soldered to pads on PCB for electrical and
mechanical connection

Acronym Full name Remark

SIP Single in-line package
2.5 mm pin spacing, rows 7.6/ 15 mm
DIP Dual in-line package
apart.
CDIP Ceramic DIP
Glass sealed
CERDIP
ceramic DIP
Quadruple in-line
QIP staggered (zig-zag) pins.
package
SDIP Skinny DIP 0.1” pin spacing, rows 0.3” apart
ZIP Zig-zag in-line package
MDIP Molded DIP
PDIP Plastic DIP 55
Surface mount
Acronym Full name
CCGA Ceramic Column Grid Array]
CGA Column Grid Array[3]
CERPACK Ceramic package [4]
CQGP[

LLP Lead-Less lead-frame Package

LGA Land Grid Array[3]

LTCC Low temperature co-fired ceramic[7]
MCM Multi-Chip Module[8]
Micro Surface Mount Device extended
MICRO SMDXT
technology[9] 56
 Chip carrier
Rectangular package with contacts on all four edges.
Leaded chip carriers have metal leads wrapped around the edge
of the package, in the shape of a letter J.
Leadless chip carriers have metal pads on the edges.

Acronym Full name

BCC Bump Chip Carrier [3]
CLCC Ceramic Leadless Chip Carrier [1]
LCC Leadless Chip Carrier [3]
LCC Leaded Chip Carrier [3]
LCCC Leaded Ceramic Chip Carrier [3]
DLCC Dual Lead-Less Chip Carrier (Ceramic) [3]
PLCC Plastic Leaded Chip Carrier [1][3] 57
Pin grid arrays

Acronym Full name

OPGA Organic Pin Grid Array
FCPGA Flip-chip Pin Grid Array [3]
PAC Pin Array Cartridge [10]
PGA Pin grid array
CPGA Ceramic Pin Grid Array [3]

58
 Acronym Full name
- Flat pack
CFP Ceramic Flat Pack [3]
CQFP Ceramic Quad Flat-Pack, similar to
BQFP Bumpered Quad Flat Pack [3]
DFN Dual Flat Pack
ETQFP Exposed Thin Quad Flat Package [11]
PQFN Power Quad Flat-Pack Flat
PQFP Plastic Quad Flat Package [1][3] packages
LQFP Low-profile Quad Flat Package [3]
QFN Quad Flat No Leads
QFP Quad Flat Package [1][3]
MQFP Metric Quad Flat Pack
HVQFN Heat-sink Very-thin Quad Flat-pack No-leads
SIDEBRAZE -
TQFP Thin Quad Flat Pack [1][3]
TQFN Thin Quad Flat No-Lead
VQFP Very-thin Quad Flat Pack [3] 59

ODFN Optical Dual Flat No-Lead

Small outline packages
Acronym Full name
SOP Small Outline Package [1]
CSOP Ceramic Small Outline Package
MSOP Mini Small-Outline Package
PSOP Plastic Small-Outline Package [3]
PSON Plastic Small-Outline No-Lead Package
QSOP Quarter-Size Small-Outline Package
SOIC Small Outline Integrated Circuit
SSOP Shrink Small-Outline Package [3]
TSOP Thin Small-Outline Package [3]
TSSOP Thin Shrink Small Outline Package [3]
TVSOP Thin Very Small-Outline Package [3]
µMAX -
WSON Very Thin Small Outline No Lead Package 60
Chip-scale packages
Acronym Full name Remark
Chip Scale
CSP size < 1.2 size of Si chip [16][17]
Package
True Chip Size
TCSP Package is same size as silicon [18]
Package
True Die Size
TDSP Same as TCSP [18]
Package
MICRO
- CSP by National Semiconductor [19]
SMD
COB Chip-on-board Bare silicon chip without a package.
COB, where chip is mounted directly
COF Chip-on-flex
to a flex circuit.
COB, where a chip is mounted
COG Chip-on-glass 61
directly to a piece of glass - LCD
Ball grid array a square or rectangular array
of solder balls on one surface
Acronym Full name
FBGA Fine Pitch Ball Grid Array
LBGA Low Profile Ball Grid Array
TEPBGA Thermally Enhanced Plastic Ball Grid Array
CBGA Ceramic Ball Grid Array [3]
OBGA Organic Ball Grid Array [3]
TFBGA Thin Fine Pitch Ball Grid Array [3]
PBGA Plastic Ball Grid Array [3]
MAP-BG
Mold Array Process - Ball Grid Array [2]
A
UCSP Micro (μ) Chip Scale Package
μBGA Micro-Ball Grid Array
LFBGA Low Profile Fine Pitch Ball Grid Array [3]
TBGA Thin Ball Grid Array [3]
SBGA Super Ball Grid Array [3] 62
UFBGA Ultra Fine Ball Grid Aarray [3]
63
64
65
66
67
Types of Packages

68
 Types of Packages - Hermetic Packages

• Chip resides in the cavity

of the package.

• Package base material is

ceramic usually Al2O3 or
AlN.

• Chip and package are

connected by fine Al wire.

• Hermetic sealing is
completed by a cap
(ceramic/metal) lidded
(covered) to the package.
69
Types of Packages - Plastic Packages

• Chip is attached to the

package of the lead frame.

• Frame is made of etched or

stamped thin metal(Fe-Ni or
Cu alloys).

• Interconnections are made by

fine gold wire.

• Encapsulation is carried out

by Transfer-molding using
epoxy resin.

70
 Rent’s Rule
• An empirical
relationship
between the gate
count and the I/O
(Terminal) Count
in a Chip.

• Number (I/O
Count ) =αN β =α
(Number of
gates)β

Typically: α=
4.5 β= 0.5
71
System on Chip ( SoC ) versus
System in Package (SiP)

• SoC – technology that allows

a system to be built on one
silicon chip

• SiP – technology that

combines multiple number of
readymade chips and
encases them in one package
as one system.

72
SiP Categories

73
74
75
76
3D Packaging: Introduction

• 3 D Packages score over

conventional packages in
• Size and Weight
• Silicon Efficiency
• Interconnect Usability and
Accessibility
• Delay
• Noise
• Power Consumption
• Speed
• higher reliability Four-die stack
• higher performance including two spacers
77
Types of 3D Packages
• Stacked Die Packages:
• Consists of bare die stacked and
interconnected using wire bond
and flip-chip connections in one
standard CSP
• Stacked-Packages:
• consist of stacked, pre-tested PiP structure with 4 stacks
packages or a mix of KGD and
packages. These are
interconnected using wire bond,
flip chip or solder balls on one
CSP
• They can be:
• Package-in-Package(PiP)
PoP structure with 4 stacks
• Package-on-Package(PoP)
78
3 D Packaging: Advantages -I
The shift from conventional single chip packages to 3D
technology, leads to substantial size and weight reductions:

79
 3 D Packaging: Advantages -II

• Increase in
Silicon
Efficiency.
• Interconnect
Usability and
• Accessibility.

80
 3 D Packaging: Advantages -III

• Delay
Reduction
• Noise
Reduction
• Power
Reduction
• Speed Increase

81
 3 D Packaging: Limitations

There are trade-offs which need to be taken into

account when using 3D technology in system design:
• Thermal Management
• Design complexity
• Cost
• Time to Delivery
• Design Software

82
Electrical Considerations: Introduction

• The choice of a package for IC:

• Depends on the electrical and thermal operating conditions

• Electrical operating conditions of IC are different for:

• Signals and

• Power.

83
Electrical Considerations: The Signal
Environment
• Signal's electrical environment: arrangement of conductors and
dielectrics.
• Electrically, each path represents a transmission line
• with certain characteristic impedance and time delay
• Inductances of bond wires and package pins
• Leads possess substantial inductance and capacitance.
• Strong inductive and capacitive coupling between leads
• Major issues:
• Signal Delay,
• Signal Reflection and
• Noise Reduction. 84
Electrical Considerations: The Signal
Environment
• Signal Delay
• High speed operation requires lower interconnect delays.
• The maximum achievable operating frequency is inverse of
the critical delay path.
• In package construction, a short signal line (bonding wire
length plus lead length) in small dielectric material, typically
polyimide resin, is preferable.
• An excessively small dielectric constant of the surrounding
material, however induces signal reflections that degrade
operating speed.

85
Electrical Considerations: The Signal
Environment
• Signal Reflection:
• Mismatched impedances
cause signal reflections
when a signal is
transmitted via a Stripline conductor
transmission line.
• Important when signal
lines are long
• Multilayered packages like
stripline structures and
microstrip structures provide
better impedance matching
Microstrip conductor
86
Electrical Considerations: The Signal
Environment
• Noise:
• Cross-Talk noise
• Simultaneous switching
noise:
• Cross Talk Noise: Line is Cross Talk on Adjacent Lines
undesirably affected by
another line due to
electromagnetic coupling
• Simultaneous Switching
Noise: Occurs when many
output buffers switch
simultaneously
Simultaneous Switching Noise 87
Electrical Considerations: The Power
Environment

• Inductances in the power circuit cause instability of

the potentials at the power and ground terminals of
the chip:

• Power Supply Droop

• Ground Bounce

88
Electrical Considerations
• Desirable Electrical Characteristics:
• Low ground resistance (minimum power supply voltage
drop)
• Minimum Self Inductance of signal leads (short signal
leads)
• Minimum power supply spiking due to simultaneous
switching of signal lines.
• Minimum Mutual Inductance and Cross Talk (short
paralleled signal runs)
• Minimum Capacitive loading (short signal runs near a
ground plane)
• Maximum use of Matched Impedances (avoid signal
reflection) 89
 Thermal Management

• Efficient and cost-effective removal of dissipated thermal

energy from the device to assure its reliable performance over
the long term.
• Effects of Increasing Temperatures:
• Device physics is strongly influenced by the junction
temperature
• Corrosion and interfacial diffusion mechanisms
• Approximately a 10°C increase in temperature reduces the
mean time to failure by a factor of two

90
 Thermal Management (Thermal
Resistance)
• Internal or junction temperature=ambient temperature + an
offset proportional to the internal power dissipation P.
• Tjunction= Tambient+ θJA.P
• Constant of proportionality θJAis called the thermal resistance
• Current Trends: Total power is increasing due to:
• improper scaling,
• higher packing density, and
• lower chip size
• Maximum ambient being as high as 60 °C
• Maximum junction temperatures from 105 °C to 65 °C
91
• The total thermal resistance of the package must decrease:
Thermal Management
• A Simplified Heat transfer model:
• Heat is transferred from chip to
surface of package by
conduction
• from package to the ambient
by convection and radiation:
• θJA= θJC + θCA
= ((Tj-Tc) + (Tc-Ta))/P
θJC is mainly a function of package
materials and geometry
θCA depends on package geometry,
the package orientation and
conditions of ambient. 92
Thermal Considerations
• Conduction dominates heat transfer from chip to package
surface.
• One Dimensional Fourier’s equation gives:
Q = (T1–T2)*κ*(S/L)
• In the actual package: P = (Tj–Tc)*κ*(S/L)
• θJC= (Tj–Tc)/P = L/(κ*S)
• VLSI packages have a high packing density (small S)
• So high thermal conductivity components such as Cu alloys
lead frames, AlN substrates and thermo-conductive molding
compounds are particularly important as they increase overall
package κ value.
• Thinner packages (low L) are also important. 93
Thermal Considerations
• Convection: Heat transfer from the package surface to the
ambient is mostly by convection, given by Newton’s Cooling
Law:
• Q = h*A*(Tc–Ta)
• θCA= (Tc–Ta)/P = 1/(h*A)
• θCA is reduced through increased conduction and larger
package surface area.
• The application system constructions are:
• forced air convections,
• liquid coolants in place of air coolings and
• additional heat sinks attached to the package surface.
94
Thermal Considerations
• Radiation helps transfer of heat from the package surface to
the ambient (small contribution)
• According to Stefan-Boltzmann Law:
• Eb= ε*σ*T4
• The heat radiated is:Q = σ*f*A*(T14 –T24) Where f is given by:
• f = 1/((1/ε1)+(1/ε2)-1)
• When T1-T2<<T1 & T1-T2<<T2,then with Tm=(T1+T2)/2:
• Q = 4*σ*f*Tm3*A*(T1-T2) = h*r*A*(T1-T2)
• Therefore: θrad= (T1-T2)/Q = 1/(h*r*A)
• In actual applications black dyed packages and external heat
sinks are preferred since they increase hr values
95
Thermal Management: Thermal Profiles

• In the thermal design and characterization of device

packages, it is often necessary to know the temperature
profiles for known power dissipation and boundary conditions.
• Further, this information may be needed for steady state and
transient conditions.
• Computer-based software are most extensively used in this
area.
• Experimental methods are also used.

96
Common Failure Mechanisms and
Reliability Tests

• Chip Crack: Occurrence of fracture anywhere in the die

• Major Causes:
• TCE mismatch of components
• Operation to note: Chip Bonding
• Test Type: Temperature Cycling
• Typical Conditions: -65 °C - +150 °C

97
Common Failure Mechanisms and
Reliability Tests
• Wire Liftoff: Includes Ball
Bond Lifting and Wedge Bond Ball Bond Lifting
Lifting
• Major Causes:
• poor bonding,
• Bonding pad
contamination
• Test Conditions: Test Contaminated Bond Pads
Type: Temperature
Cycling,
Cratered*
• 150 °C -175 °C
Bond Pad 98
(with some dip)
Common Failure Mechanisms and
Reliability Tests
• Wire Break: Breakage along the span of the wire
• Major Causes:
• Poor Bonding,
• Stress from molding resin
• Test Type: Temperature Cycling, Vibration
• Typical Conditions: -65 °C –150 °C

99
Common Failure Mechanisms and
Reliability Tests
• Malfunction: Non-conformance to electrical specifications due
to component degradation caused by stresses on the die
surface
• Major Causes: TCE mismatch of components
• Operation to note:
• Chip Bonding –Encapsulation
• Test Type: PCT (Pressure Cooker Test) with bias, Typical
Conditions: 130 °C, 85% RH, 7V; 125 °C, 7V

RH-relative humidity
100