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Analog Integrated Circuits & Technology
(EC 305)
(5th semester mini project report)
A report on:
Differential amplifier with passive load and its detail analysis.
Submitted By:
Manzil Hoque (18-1-4-069)
Under the supervision of,
Dr. Koushik Guha
&
Dr. Brinda Bhowmick
Electronics and Communication Engineering,
National Institute of Technology Silchar
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ABSTRACT
The objective of this report is to discuss about differential amplifier with passive load. Differential
amplifiers are the basic building block in the analog circuit design. The characteristics of the differential
amplifier are measured by differential gain, Common mode Rejection Ratio, and Gain-Bandwidth product.
In this report a high-performance differential amplifier is designed using different approaches and a
comparison is made between them. This work presents the optimized architecture of a differential amplifier.
As we know, the design and analysis of differential amplifiers makes extensive use of the material on single-
stage amplifiers. We will follow the study of differential amplifiers with examples of practical multistage
amplifiers, again in both MOS and bipolar technologies.
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1. Introduction
The differential-pair or differential-amplifier configuration is the most widely used building block in
analog integrated-circuit design. For instance, the input stage of every op amp is a differential amplifier.
Also, the BJT differential amplifier is the basis of a very-high-speed logic circuit family, A difference
amplifier is one that responds to the difference between the two signals applied at its input and ideally
rejects signals that are common to the two inputs.
There are two reasons why differential amplifiers are so well suited for IC fabrication: First, as we
shall shortly see, the performance of the differential pair depends critically on the matching between the two
sides of the circuit. Integrated-circuit fabrication is capable of providing matched devices whose parameters
track over wide ranges of changes in environmental conditions.
The second reason for preferring differential amplifiers is that the differential configuration enables us to
bias the amplifier and to couple amplifier stages together without the need for bypass and coupling
capacitors such as those utilized in the design of discrete-circuit amplifiers. This is another reason why
differential circuit are ideally suited for IC fabrication where large capacitors are impossible to fabricate
economically.
2. The MOS Differential Pair
The MOS Differential Pair consists of two matched transistors,
Q1 and Q2, whose sources are joined together and biased by a
constant-current source I.
It is usually implemented by a MOSFET circuit that it has
infinite output resistance. we will explain the essence of the
differential pair operation utilizing simple resistive loads.
Whatever type of load is used, it is essential that the MOSFETs
not enter the triode region of operation.
Figure 1 The basic MOS differential-pair configuration
2.1 Operation with common mode input voltage
In the common mode input voltage the gate terminals are joined together and connected to a voltage
VCM , i.e. VG1=VG2=VCM. Since Q1 & Q2 are matched, iD1 =iD2 = I/2 .So, voltage at sources will be, VS=VCM-VGS
Neglecting channel length modulation VGS and I/2 are related as
In terms of over drive voltage VOV=VGS-Vt
Voltage at each drain will be,
I
vD1 =vD2 = VDD - 2 RD
Figure:2 The MOS differential pair with a common-mode
input voltage VCM
The differential pair works properly for a certain range of V CM known as input common-mode range. The
highest value and the lowest value of VCM is given as,
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2.2 Operation with Differential input voltage
In this we apply a difference or differential input voltage by grounding the gate of Q2 (i.e., setting
vG2 = 0) and applying a signal vid to the gate of Q1. By applying KVL we get, Vid =VGS1 –VGS2.
The differential pair responds to difference-mode or differential input signals by providing a
corresponding differential output signal between the two drains.
To cause entire bias i.e, the current to flow in only one of the transistors, VGS1 should have a value
that corresponds to iD1=I and VGS2 is reduced to value equal to threshold voltage Vt, so vs= -Vt
As current flows completely through Q1
Thus, value of Vid for which entire bias current
flows through Q1 is
vid max = vGS1+vs = √2VOV
Figure 8.4 The MOS differential pair with a differential
If Vid is increased beyond √2VOV, iD1 remains equal to I, vGS1 remains equal to Vt +√2VOV and vs increases
correspondingly. Similarly, the entire bias current can be made to flow through Q2 keeping Q1 off by
varying Vid in the range
To use differential amplifier as linear amplifier V id is kept small. Thus, current in one transistor increase by ΔI
proportional to Vid and current in another transistor decrease by same amount.
2.3 Large-Signal Operation
In the drain currents iD1 and iD2 in terms of the
input differential signal vid=vG1–vG2. The
derivation assumes that the differential pair is
perfectly matched and neglects channel-length
modulation (λ = 0). we simply assume that the
circuit maintains Q1 and Q2 in the saturation region
of operation at all times.
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Figure 5 The MOSFET differential pair for the purpose of deriving the
transfer characteristics, iD1 and iD2 versus vid = vG1 – vG2.
We can express iD1 and iD2 in terms of vid and
Vov , where Vov =VGS-Vt
These two equations describe the effect of applying a differential
input signal vid on the currents iD1 and iD2. They can be used to
obtain the normalized plots, iD1 /I and iD2 /I versus vid /VOV.
Figure 6 Normalized plots of the currents in a MOSFET differential pair.
Note that VOV is the overdrive voltage at which Q1 and Q2 operate when
conducting drain currents equal to I/ 2, the equilibrium situation.
3. Small-Signal Operation of the MOS Differential Pair
Understanding gained of the basic operation of the differential pair and consider in some detail its
operation as a linear amplifier.
3.1 Differential Gain
Figure 8.8 Small-signal analysis of the MOS differential amplifier. (a) The circuit with a common-mode
voltage applied to set the dc bias voltage at the gates and with vid applied in a complementary (or balanced)
manner. (b) The circuit prepared for small-signal analysis. (c) An alternative way of looking at the small signal
operation of the circuit.
Input voltages of the MOS differential amplifier shown in the figure,
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Here, VCM denotes a common-mode dc voltage within the input common-mode range of the differential amplifier. Typically, VCM is
at the middle value of the power supply. The amplifier output can be taken either between one of the drains and ground or
between the two drains. In the first case, the resulting single-ended outputs vo1 and vo2 will be riding on top of the dc voltages at
the drains, This is not the case when the output is taken between the two drains; the resulting differential out put vod
(having a 0-V dc component) will be entirely a signal component
If the output is taken in a single-ended fashion, the resulting gain becomes
Alternatively, if the output is taken differentially, the gain becomes
Thus, another advantage of taking the output differentially is an increase in gain by a factor of 2 (6 dB). However, that although
differential outputs are preferred, a single ended output is needed in some applications.
3.2 The Differential Half-Circuit
The performance of amplifier can be
determined by considering only half the circuit
when a symmetrical differential amplifier is fed
with a differential signal in a balanced manner.
The equivalent differential half-circuit has a
grounded source. The differential gain Ad can be
determined directly from the half-circuit.
The differential gain Ad for the half-circuit shown
is Ad =gm ( R D ∥r 0 )
3. 3 Common-Mode Gain and Common-Mode
Rejection Ratio (CMRR) :
MOS differential amplifier biased with a current source having an output resistance R SS is shown in figure
1(a). The dc voltage at the input is defined by V CM and an incremental signal vicm applied to both input
terminals. The transistors Q1and Q 2 operates at a bias current of I /2. The virtual ground that develops on the
common-source terminal results in a zero signal current through R SS and has no effect on the value of Ad .
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To determine the response of the differential common-mode signals. This can be achieved by
amplifier to the common-mode input signal vicm , considering only half the differential amplifier as
consider the circuit in Fig. 1(b). The circuit is shown in the figure.
obviously symmetrical, and thus the two v icm
transistors will carry equal signal currents, The current i is given by ⅈ=
denoted i. But the differential output voltage 1 ∕ gm +2 RSS
equals to zero and then making common mode
gain zero which shows that the circuit still rejects
Effect of R D Mismatch:
The common-mode voltages at the two drains will no longer be equal when the two drain resistances exhibit
a mismatch Δ R D . If the load of Q 1is R D and that of Q 2 is ( R ¿ ¿ D+ Δ R D )¿, the common mode gain is
−R D Δ R D .
( )( )
2 R SS R D
Common-Mode Rejection Ratio (CMRR) :
The ratio of the magnitude of its differential gain | A d| to the
magnitude of
its common-
mode gain | A cm|.
This ratio is termed common-mode rejection ratio (CMRR). It is
measure amplifying differential-mode signals and rejecting
common-mode interference.
Effect of gm Mismatch on CMRR :
Another possible mismatch between the two halves of the MOS
differential pair is a mismatch in gm of the two transistors. Thus the
common-mode gain resulting from a mismatch Δ g m can be given as
RD Δ gm
Acm = ( )( )
2 RSS gm
Then the corresponding CMRR will be
4. THE BJT DIFFERENTIAL PAIR
Figure 7.12 shows the basic BJT differential-pair
configuration. It is very similar to the MOSFET circuit and
consists of two matched transistors, Q1 and Q2, whose
emitters are joined together and biased by a constant-
current source I. Although each collector is shown
connected to the positive supply voltage VCC through a
resistance RC, this connection is not essential to the
operation of the differential pair—that is, in some
applications the two collectors may be connected to current
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sources rather than resistive loads. It is essential, though, that the collector circuits be such that Q1 and Q2
never enter saturation.
4.1 Basic Operation
In the BJT differential pair the two bases joined together and connected to a commonmode voltage Vcm. the current I will
remain constant and from symmetry that I will divide equally between the two devices.
4.2 Input Common Mode Range
The allowable range of is determined at the upper end by and leaving the active mode and entering
saturation. Thus,
The lower end of the range is determined by the need to provide a certain minimum
voltage across the current source I to ensure its proper operation. Thus,
4.3 Large - Signal Operation
After doing general analysis of the BJT differential pair we get the current components as,
A small signal can switch the current from one side of the BJT differential pair to the other means
that the BJT differential pair can be used as a fast current switch.
Transfer characteristics of the BJT differential pair assuming α=1 is shown,
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4.4 Small-Signal Operation
In this figure we can see the BJT
differential pair with a difference voltage signal
vid applied between the two bases. Which means
the dc level at the input or the common-mode
input voltage has been established. Now we can
either ground one of the two input terminals and
applying vid to the other input terminal or the
differential amplifier may be fed from the output
of another differential amplifier. In the second
case, the voltage at one of the input terminals will
be VCM + vid/2 while that at the other input
terminal will be VCM − vid/2.
Figure A. The currents and voltages in the differential
amplifier when a small differential input signal vid is applied
The Collector Currents When vid is Applied
Thus the total base–emitter voltages will be,
Here gm transconductance of Q1 and of Q2, which are equal and given by,
Input Differential Resistance
Differential Voltage Gain
For small difference input voltages (vid<<2 VT ; i.e., vid smaller than about 20 mV), the collector currents
are given by
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Therefore, the total voltages at the collectors will be
Just like in the MOS case, the output voltage signal of a bipolar differential amplifier can be taken
differentially (i.e., between the two collectors, vod = vc2 – vc1). The differential gain of the differential
amplifier will be
For the differential amplifier with resistances in the emitter leads (Fig. C), the differential gain is given by
The voltage gain is equal to the ratio of the total resistance in the collector circuit (2RC) to the total
resistance in the emitter circuit (2re +2Re).
The Differential Half-Circuit
As in the MOS case, the differential gain of the BJT differential amplifier can be obtained by
considering its differential half-circuit.
The circuit is equivalent to the two common-emitter amplifiers shown below where each of the two
transistors is biased at an emitter current of I/2. The finite output resistance REE of the current source will
have no effect on the operation. The equivalent circuit in above figure is valid for differential operation only.
If we take the common-emitter transistor fed with +vid /2 as the differential half-circuit and replace the
transistor with its low-frequency, equivalent-circuit model. In evaluating the model parameters r0 , gm, and
ro, we must recall that the half-circuit is biased at I/2. The voltage gain of the differential amplifier is equal
to the voltage gain of the half-circuit—that is, vo1/(vid / 2).
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The input differential resistance of the differential amplifier is twice that of the half-circuit—
that is, 2rπ . Including ro will modify the gain expression as Ad = gm (RC || ro )
4.5 Common-Mode Gain and CMRR
Below Figure shows a bipolar differential amplifier with an input common-mode signal vicm. Here
REE is the output resistance of the bias current source I. The voltages that result from vicm at the collectors of
Q1 and Q2,V01 and V02 and between the two collectors, Vod. Toward that end, we make use of
thecommon-mode half-circuits shown below. The signal vo1and vo2 that appears at the collector of Q1 and Q2
respectively in response to vicm will be,
Figure: (a) The differential amplifier fed by a common-mode input signal vicm. (b) Equivalent
“half-circuits” for common-mode calculations.
The common-mode gain will be,
The common-mode rejection ratio can now be found from
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Figure: (a) Definition of the input common-mode resistance Ricm. (b) The equivalent common-mode
half-circuit.
Common-Mode Input Resistance
5. Conclusion
The differential-pair or differential-amplifier configuration is the most widely used building block in
analog IC design. The input stage of every op amp is a differential amplifier. There are two reasons for
preferring differential to single- ended amplifiers: Differential amplifiers are insensitive to interference, and
they do not need bypass and coupling capacitors. In this report, we have done the analysis of a differential
amplifier to determine differential gain, differential input resistance, frequency response of differential gain,
and so on is facilitated by employing the differential half-circuit, which is a common-source (common-
emitter) transistor biased at I/2.Also, the different topologies of differential amplifiers have been discussed
and analyzed in terms of gain, gain bandwidth product, and CMRR.
REFERENCES
[1] Microelectronic circuits by Adel S. Sedra and Kenneth C. Smith 6th edition
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