SN54F32, SN74F32

QUADRUPLE 2-INPUT POSITIVE-OR GATES

SDFS044B – MARCH 1987 – REVISED MAY 1999

D Package Options Include Plastic SN54F32 . . . J PACKAGE

Small-Outline (D) Packages, Ceramic Chip SN74F32 . . . D OR N PACKAGE
(TOP VIEW)
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
1A 1 14 VCC
1B 2 13 4B
description
1Y 3 12 4A
These devices contain four independent 2-input 2A 4 11 4Y
OR gates. They perform the Boolean functions 2B 5 10 3B
Y = A + B or Y = A • B in positive logic. 2Y 6 9 3A
GND 7 8 3Y
The SN54F32 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F32 is characterized for SN54F32 . . . FK PACKAGE
operation from 0°C to 70°C. (TOP VIEW)

VCC
NC
1B
1A

4B
FUNCTION TABLE
(each gate)
INPUTS 3 2 1 20 19
OUTPUT 1Y 4 18 4A
A B Y
NC 5 17 NC
H X H 2A 6 16 4Y
X H H NC 7 15 NC
L L L 2B 8 14 3B
9 10 11 12 13

2Y

3Y
3A
NC
GND
NC – No internal connection

logic symbol†
1
1A ≥1 3
2 1Y
1B
4
2A 6
5 2Y
2B
9
3A 8
10 3Y
3B
12
4A 11
13 4Y
4B

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.

logic diagram, each gate (positive logic)

A
Y
B

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  1999, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MAY 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

recommended operating conditions (see Note 3)

SN54F32 SN74F32
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IIK Input clamp current –18 –18 mA
IOH High-level output current –1 –1 mA
IOL Low-level output current 20 20 mA
TA Operating free-air temperature –55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN54F32 SN74F32
PARAMETER TEST CONDITIONS UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V, IOH = –1 mA 2.5 3.4 2.5 3.4
VOH V
VCC = 4.75 V, IOH = –1 mA 2.7
VOL VCC = 4.5 V, IOL = 20 mA 0.3 0.5 0.3 0.5 V
II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL VCC = 5.5 V, VI = 0.5 V –0.6 –0.6 mA
IOS§ VCC = 5.5 V, VO = 0 –60 –150 –60 –150 mA
ICCH¶ VCC = 5.5 V 6.1 9.2 6.1 9.2 mA
ICCL VCC = 5.5 V, VI = 0 10.3 15.5 10.3 15.5 mA
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
¶ ICCH is measured with one input per gate at 4.5 V and all others grounded.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MAY 1999

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 1)
VCC = 5 V,
FROM TO SN54F32 SN74F32
PARAMETER TA = 25°C UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
tPLH 2.2 3.8 5.6 2.2 7.5 2.2 6.6
A or B Y ns
tPHL 2.2 3.6 5.3 1.7 7.5 2.2 6.3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MAY 1999

PARAMETER MEASUREMENT INFORMATION

7V
From Output 500 Ω S1 Open
TEST S1
From Output Test
Under Test Point Under Test tPLH/tPHL Open
CL CL tPLZ/tPZL 7V
500 Ω (see Note A) 500 Ω
(see Note A) tPHZ/tPZH Open
Open Collector 7V

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS

3V
Timing Input 1.5 V
tw 0V
th
3V tsu
3V
Input 1.5 V 1.5 V
Data Input 1.5 V 1.5 V
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

3V 3V
Output
Input 1.5 V 1.5 V 1.5 V 1.5 V
Control
0V 0V

tPLH tPHL tPZL tPLZ

Output
VOH Waveform 1 ≈ 3.5 V
In-Phase 1.5 V 1.5 V 1.5 V
S1 at 7 V VOL + 0.3 V
Output
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
Output
VOH VOH
Out-of-Phase Waveform 2 VOH – 0.3 V
1.5 V 1.5 V 1.5 V
Output S1 at GND
VOL ≈0V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns,
duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 9-Oct-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9758801Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9758801Q2A
SNJ54F
32FK
5962-9758801QCA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9758801QC
A
SNJ54F32J
5962-9758801QDA ACTIVE CFP W 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9758801QD
A
SNJ54F32W
SN54F32J ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 SN54F32J

SN74F32D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F32

& no Sb/Br)
SN74F32DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F32
& no Sb/Br)
SN74F32DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F32
& no Sb/Br)
SN74F32DRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F32
& no Sb/Br)
SN74F32DRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F32
& no Sb/Br)
SN74F32N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74F32N
& no Sb/Br)
SN74F32NE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74F32N
& no Sb/Br)
SN74F32NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74F32
& no Sb/Br)
SNJ54F32FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9758801Q2A
SNJ54F
32FK
SNJ54F32J ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9758801QC
A
SNJ54F32J

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 9-Oct-2020

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SNJ54F32W ACTIVE CFP W 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9758801QD
A
SNJ54F32W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54F32, SN74F32 :

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 9-Oct-2020

• Catalog: SN74F32
• Military: SN54F32

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Dec-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74F32DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74F32NSR SO NS 14 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Dec-2014

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74F32DR SOIC D 14 2500 367.0 367.0 38.0
SN74F32NSR SO NS 14 2000 367.0 367.0 38.0

Pack Materials-Page 2
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
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