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EECS 141: First Midterm Exam, Fall '96

1) The document is the first midterm exam for EECS 141: Digital Integrated Circuits at UC Berkeley from Fall 1996. It contains two problems assessing students' knowledge of transistor parameters, inverter design, and logic gate implementation. 2) Problem 1 involves analyzing an NMOS inverter circuit and assessing how changes in transistor threshold voltages affect its voltage output and switching characteristics. Problem 2 examines the logic function of a given circuit and designing pull-up and pull-down networks to implement the function in complementary CMOS style. 3) Students are asked to show their work, use provided transistor parameters, and qualitatively analyze how design changes impact various circuit properties like power dissipation and switching times.

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Maan Al-Adwany
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125 views7 pages

EECS 141: First Midterm Exam, Fall '96

1) The document is the first midterm exam for EECS 141: Digital Integrated Circuits at UC Berkeley from Fall 1996. It contains two problems assessing students' knowledge of transistor parameters, inverter design, and logic gate implementation. 2) Problem 1 involves analyzing an NMOS inverter circuit and assessing how changes in transistor threshold voltages affect its voltage output and switching characteristics. Problem 2 examines the logic function of a given circuit and designing pull-up and pull-down networks to implement the function in complementary CMOS style. 3) Students are asked to show their work, use provided transistor parameters, and qualitatively analyze how design changes impact various circuit properties like power dissipation and switching times.

Uploaded by

Maan Al-Adwany
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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University of California at Berkeley

Department of Electrical Engineering and Computer Science

EECS 141: First Midterm Exam, Fall '96


Renu Mehra 26th Sept. 1996

Please PRINT your name and sign below. Also, write your name in each sheet before you
start. Use the space provided to answer all questions. You can use the back side of the sheet if
needed. Show your work for full credit.

Name:
(last) (first)

Signature:

Transistor parameters:

NMOS PMOS

VT0 0.7 -0.7

k'n, k'p 20 µA/V2 60 µA/V2

Ld 0 µm 0 µm

Neglect body effect and channel-length modulation.

Grades

Problem #1

Problem #2

Total

EECS 141: Digital Integrated Circuits, Fall '96 1


Name:

Problem 1. Bill needs to implement an inverter in an NMOS only process. He decides to use a
saturated enhancement mode load as shown in the figure below. The total load capacitance on
the inverter is 3pF.
5V

M1
W/L=0.5

Out

M2 CL = 3pF
in
W/L=4.75

1(a) Find the VOL of the above circuit.

VOL:

1(b) Bill finds out that the NMOS process he is using has a variation of +0.5V in the threshold
voltages (VT) of its devices and that devices in the same chip can have different thresholds.
What threshold voltages of M 1 and M2 will give the highest VOL?

VT1: VT2:

EECS 141: First midterm exam, 26th Sept. '96 2


Name:

1(c) Find the VOL of the inverter with threshold voltages computed in part (b).

V OL:

1(d) Explain qualitatively how the following properties of the inverter are affected as the
threshold voltages change from part (a) to part (b). If you are unsure of your VOL values,
assume that it increases by 0.1V from part (a) to part (c). Identify what changes in the dif-
ferent parameters led to your conclusions.

Increase/
Why?
Decrease?

Static power
dissipation

Dynamic power
dissipation

EECS 141: First midterm exam, 26th Sept. '96 3


Name:

Increase/
Why?
Decrease?

tpHL

1(e) In an attempt to reduce improve VOL, Bill decides to double the size of the NMOS pull-
down transistor. Explain qualitatively how his decision affects the following properties and
identify what changes in the different parameters led to your conclusions. The threshold
voltages are the same as in part (a).

Increase/
Why?
Decrease?

Static power dis-


sipation

Dynamic power
dissipation

tpHL

EECS 141: First midterm exam, 26th Sept. '96 4


Name:

Problem 2.
V DD

Out
C C C C

B B B B

A A

2(a) Determine the logic function of the above circuit. Identify the function.

Out =

2(b) Does the size of the PMOS transistor affect the functionality of the circuit? Briefly explain
why or why not?

EECS 141: First midterm exam, 26th Sept. '96 5


Name:

2(c) What is the static power consumption of the circuit?

2(d) Derive the pull-up and pull-down networks to implement the above logic in complemen-
tary CMOS logic style. You can assume that both the inputs and their complements are
available. Use 10 transistors or less in each of the pull-up and pull-down networks.

EECS 141: First midterm exam, 26th Sept. '96 6


Name:

2(e) Find W/L ratios of the devices in your network so that the tpLH and tpHL of your gate are
the same as that of a CMOS NAND gate with W/L = 2 for both the NMOS and PMOS tran-
sistors.

EECS 141: First midterm exam, 26th Sept. '96 7

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