Chapter 4.5.

High Frequency Passive Devices

1
 Outline

Inductors
Transmission lines
Varactors
MIM Capacitors
Resistors

2
Types of integrated inductors (Yoon, RFIC-2003)

In silicon ICs:
● Spiral
● Multi-layer shunted
● Symmetrical spiral Stacked Helical Stacked MEMS

● Stacked helical

3
Types of inductors: by number of terminals

2-terminal

3-terminal (t-coil)

transformers

symmetrical transformers
(baluns)

4
 Inductor integration issues
Low quality factor (Q)

Large chip area (high cost)

Limited application frequency range:

lower bound limited by size and Q

upper bound (SRF=Self-Resonant-Frequency)

limited by dielectric thickness

Cross-talk through silicon substrate

GOAL is to AIM HIGH: high Q and high SRF

5
2-terminal inductor layout & cross-section

Main FOMs
● Inductance L
● Quality factor Q
● SRF
● PQF

6
 Inductance L
Inductance: induces and stores magnetic field
total flux
Greenhouse Equation L=
current

n n n
L=Self Inductance ∑ Li  + Mutual Inductance ∑ ∑ M ij 
i=1 i=1 j=2  j≠i 
Lj3
Mij

Lj2 Li3
Lj4
Li1

Lj1

M>0 M<0 M=0

7
 Inductor Q
recommended range
Q describes energy
efficiency:
stored energy
Q=
dissipated energy

Conventional definition:

PQF SRF
ℑ−Y11 
Qeff =
ℜY11 

8
0.13 µm CMOS two-terminal inductor meas.
−1
ℑ[ Y11  ] ℑ[−Y11 ]
Leff = Qeff =
 ℜ[ Y11 ]

9
Loss mechanisms in inductors (Dubuc et al, IMS2002)
loss in
metal
loss in
substrate

10
 Metal loss: series resistance Rs
DC-loss due to thin metal
and planar geometry

Frequency-dependent
cross-section due to skin
effect (B induced by
conductor itself) J=JpJe where

Non-uniform current density ∇×Jp=0; ∇×Je=j B; ∇ Je=0

due to proximity effect (B Jp = potential current
induced by neighbours) Je = eddy current

11
 Metal loss: techniques to reduce it

Multiple metal layers shunted (reduces PQF and SRF)

Thicker metal (needs process change)

More conductive metal i.e. Cu instead of AlCu (needs

process change)

Use narrower inner turns to reduce eddy current loss and

wider outer turns to reduce DC resistance (increases PQF
and SRF)

12
 Substrate loss

Ip = potential current in
substrate, induced by
electric field
sub
Jp = sub E=− sub ∇ 
2
where ∇ =0

Ieddy= eddy current in

substrate, induced by
magnetic field causes
inductance and resistance
loss ∇ ×Jeddysub= j sub B

13
Propagation modes (Dubuc et al, IMS2002)

14
Substrate loss: techniques to reduce it
Minimize electric coupling to substrate (Id) (also increases
SRF and PQF):
small inductor area
increase dielectric thickness (process change ?)
low-k dielectric (process change)
Reduce eddy currents in substrate
pattern shield (reduces PQF, SRF)
Reduce both eddy and potential currents in sub.
increase substrate  ( =>0) (process change)
Place sub contacts 30 m .. 50 m from inductor
15
HF inductor equivalent circuits: simple 

T
W S

16
Equivalent circuit model equations: simple 
Cao Y. et al., JSSC March 2003
6 0 n2 d2avg
L (see t-line-over-substrate equations) L≈
11d−7davg
n = number of turns
d = outer diameter of inductor
davg = arithmetic mean of inner and outer diameter
0 = 4 10-13 H/m is the permeability of vacuum
l
Rs has DC and AC (frequency dependent) terms RDC =
Wt
s is the conductivity of the metal l
R AC=
=
1
f 

W  1−exp
 
−t

17
Equivalent circuit model equations (ii): simple π
1 ox
Coxi (oxide capacitance) Cox= l W
2 h

2 ox
Cp (overlap capacitance) Cp=n W hM9−M8

Csi, Rsubi: substrate network, describe losses in the

silicon substrate, similar to the Csub-Rsub network of the
MOSFET and SiGe HBT.
Rsubi Csi=r 0×Rsu

where Rsu in is the substrate resistivity, i=1..2

18
HF inductor equivalent circuit: 2-π

19
Parameter extraction (2-terminal  circuit)
● At low frequency (0.5 GHz to 1 GHz) extract directly:
−1
ℑ[−Y 12 ] R=ℜ[−Y12−1 ]
L=

−1
Rsub1=ℜ[Y 11Y12  ] Rsub2=ℜ[Y 22Y12 −1 ]

−1 −1
[−ℑ[Y 11Y12  ]] [−ℑ[Y 22 Y12 −1 ]]−1
COX1= COX2=
 

r 0×Rsu
Csi=
Rsubi

20
 Parameter extraction (2-terminal circuit)

● At high frequency (5 GHz to beyond SRF) :

calculate (and/or optimize):
CP from imag(Y12),
skin effect parameters Lf, Rf from real(Y12),
Csubi from imag (Yii+Y12)

21
Scaling of inductors to mm-wave frequencies
Scale size and frequency: f->f×S, W->W/S, l->l/S, d->d/S, h-
2
>h/S, t=ct.

L≈
2 2
6 0 n davg
11d−7davg
L
≈
[ ]
60 n 2 davg
S
S d davg
11 −7
Small footprint to minimize loss in silicon S S
1 ox Cox 1 l W ox
Cox= lW =
2 h S 2S S h
2 S
Cp
Cp=n W 2  ox
hM9−M8 S
=n  
W ox
S hM9−M8
S
1 1
SRF≈ S×SRF=
2   LCOXCp 

2
L COX Cp

S S
 
S
Scaling of inductors to mm-wave frequencies
Vertical stacking and magnetic coupling to
Increase inductance/area
reduce loss in substrate

Outcome
Inductors/transformers can be as small and inexpensive as
transistors
As in MOSFETs, series resistance does not scale
Q remains the same, but at fS l

l S
l  R AC=
S
RDC =
Wt
RDC =
W
S
t
W
S 
 1−exp
−t
  
 140 pH Planar Spiral Inductor in 90-nm CMOS

d = 29 m, n = 2.25
S = 2 m, W = 2 µm
t = 3 m Measured vs. ASITIC simulated Leff
and Qeff

Slide 24
3-terminal inductor layout

25
3-terminal inductor equivalent circuit
P3

Rt

CP Lt
k

L11 R11 L22 R22

P1 P2
C OX1 C OX1C OX2 C OX2
2 2 2

2xRs1 Cs1/2 2xRs2 Cs2/2

2 R s1 ×R s2 C s1 C s2
R s1 R s2 2
26
 Model parameter extraction
ℑ [ Z11 ] ℑ[ Z22 ]
L11= L22= R11=ℜ[Z11 ] R22 =ℜ[ Z22 ]
 

−ℑ [ Z12 ] −ℑ[ Z21 ]

M= = Rt=ℜ[ Z12 ]=ℜ[ Z21 ]
 

ℑ[Z11 Z22−Z 12−Z21 ] ℑ[Z 11Z22 −Z12−Z 21 ]

Ldiff = Qdiff =
 ℜ[Z11Z 22−Z12 −Z21 ]

M
k=
 L11× L22
Coxi, Rsubi, Csi are extracted from the 2-terminal equivalent.

27
Single-ended vs. diff.-mode inductance

Ldiff =L11L222M=2.2 nH

Lsingle=L11=L22=0.67nH

● Strong mismatch can occur in either differential mode

or single-ended/common-mode if tight coupling in 3-term
inductors exists.
● Use 3-terminal inductors only inside the chip, not in
output buffer.
● Watch out for sign of M! Ldiff should be larger than 2L11.

28
 HF inductor layout design
High SRF: narrow metal, wide spacing, minimum diameter

High Q : wide, thick metal, shunted metal layers

Large L/ area and SRF: large diameter, narrow metal,

stacked, series-connected metal layers

Substrate p-taps in 25-50 µm proximity

Minimize size in differential ckts.: use one center-tapped

differential inductor, rather than two inductors (but lower
overall SRF)

29
High Q & high SRF inductor design tips
Small diameter
Narrow (narrower in inner turns), (W)
thick, (T)
widely spaced (S)
top metal -only (stacked structure for peaking inductors)
windings on
thick dielectric (h)
with low permittivity (OX)

30
i1
Transformers
i 2
n1 : n2

M
v1 L L2 v2 20 µm
1
2.5 µm
width

P2+

P1+ P1 -

31
 3-D stacked transformer modelling
ASITIC modeling
procedure
1. Use “pix” on bottom coil
alone to find COX, CSUB, 20 µm
RSUB, R2, L2 2.5 µm
width
2. Calculate CSUB
3. Use “pix” on top coil
alone to find R1 and L1
4. Use “pix” on top coil
with bottom coil
grounded to get C12
5. Use “k” command on
both coils together to
find coupling. 32
Transformers in SiGe BiCMOS and 90nm CMOS
1:1
vertically 34 µm 1:1 vertically
stacked stacked
SiGe transformer in
BiCMOS 90-nm CMOS
transformer n=2, W= 2µm,
n=2, t=3µm S=2µm, t=3µm
Baluns (symmetrical transformers)

RS11 CS11 RS12 CS12 RS13 CS13

COX11 COX12 COX13

P1+ LP/2 RP/2 LP/2 RP/2 P1-

C11 k C22 k C33

LS/2 RS/2 LS/2 RS/2

P2+ P2-
COX21 COX22 COX23

RS21 CS21 RS22 CS22 RS23 CS23

 Outline

Inductors

Transmission lines

Varactors

MIM Capacitors

Resistors

35
Transmission lines
M8

Oxide
M1
Si substrate

µ-strip

M8

Oxide

Si substrate

CPW

36
 Interconnect as Transmission Lines

Layout-view of T-line test structures

Ls1Ls2=l
0
2 
ln
8h W

W 4h 
Passivation
M8 Signal M8
M7 W=11um M7
M6 M6
M5 IMD M5
M4 h M4
M3 M3
M2 M2
M1 ground M1
FOX
Si substrate ground

Passivation
M8 Signal M8
M7 W=10um M7
M6 M6
M5 IMD M5
M4 M4
M3 M3
M2 M2
M1 M1
FOX
Si substrate ground

X-section of T-line w/i and w/o gnd metal

 Transmission lines
Show up in ICs:

by design: as circuit matching elements (preferably as

Metal-Oxide-Metal – MOM lines), or

inevitably, as interconnect (as Metal-Oxide-Silicon lines)

In Si ICs, -strip or GCPW have lower loss than CPW

Use M1, M2 or M1+M2, M1+M2+M3 ground planes

Loss mechanisms similar to inductors (no proximity effect)

38
Transmission line params and models
Most important HF performance parameters:

Characteristic impedance: Z0

Attenuation (/mm): 

Group delay (/mm): 

Use simulator built-in models for GaAs, InP, Si M-O-M strip

lines (ADS > Hspice > Spectre)

Use lumped scalable RLC model for Metal-Over-Silicon lines

Can be extracted from measurements or EM simulations

39
 T-line de-embedding technique
Goal: Remove impact of pad parasitics

Test structures: long (1.2/0.6 mm) and short (200/100

µm) lines

How? 1-step de-embedding based on ABCD and Y

matrices

Outcome: Determine ZC, γ, α, τG, εeff of intrinsic line

from ABCD matrix.

40
 T-line param. extraction from ABCD matrix
Impedance of line of
characteristic Z L j ZO tan d
impedance Z0 Zin =ZO where = j 
Z O j ZL tan d
terminated on ZL

∣ ∣ ∣ ∣∣ ∣∣ ∣
csh d Z O sh d csh d ZO sh d
∣ ∣
A B=
C D
sh d
ZO
csh d
v1
i1
= sh d
ZO
csh d
v
× 2
−i2

Z O=
B
C
=
acshA
d
or =
ash  BC
d
where d = 1 mm
2

in dB =8.688 ℜ =

∂
∂
×d  
reff =
c
d
where c=3×108
m
s

41
 Simple lumped ckt. model without skin effect
− 1  cosh −1 ( A ) 
2
L B
Signal line = LC ≈ 2  
C C ω   

GND

Oxide Passivation L/2 R/2 L/2 R/2

P1 P2
C OX

Rs Cs
P1 Z1 P2
Z1

Z2
L/2 R/2 L/2 R/2

P1 P2

Gd Cd
 Extracting the lumped circuit parameters
Simulate (in HFSS) a line with l>=10m to find ABCD params.

Find L/C and LC (high freq.)

G may be considered negligible

Optimize Lf,Rf, & Rm (skin) to fit  &  of model to HFSS simulation

or measurements

Compare simulations of 100m or longer lines to verify scalability

Example: Modelled vs. mea. 3.6-mm µstrip line

Fitted RLGC model

 Comparable SiGe vs. CMOS µstrip lines

3.6mm long

CMOS-line attenuation getting slightly worse in new nodes

0.4 dB/mm @50GHz, 0.5 dB/mm@ 65GHz, 0.66 dB/mm@ 94GHz,
T-line loss in thin and thick metal BEOLs

46
 Outline

Inductors

Transmission lines

Varactors

MIM Capacitors

Resistors

47
 Variable capacitance devices: Varactors
Figures of merit
capacitance ratio:
CMAX/CMIN

quality factor Q
linearity
Applications
VCO
Implementation
p-n junction
accumulation-mode MOS
capacitor
 Common-sense rules
Accumulation-mode MOS (AMOS) varactors have higher Q
and larger tuning range than pn junction varactors
If varactor model is not available, build a rudimentary model:
use MOSFET with S/D tied together
Add gate resistance externally, as for MOSFET
Calculate CMAX= COX×W×L + 2Cov

CMIN = CMAX/2
Smaller varactors (W and Wf) have higher Q's at a given
frequency
Extraction of simplified equivalent circuit

gate

n+ n+ p+
STI STI STI
p-well
n-well

p- substrate

−1 −1

Cvar =
[ ℑ[−Y 12 ]]
Cnw=
−1
[ℑZ21 ]
 
R=RGRCH=ℜZ11Z22−Z12−Z21  Rsub =ℜZ21 

50
Meas. vs. sim. Cvar(V) for 1.2V, 130nm device

51
 90nm AMOS varactors: Ceff

10x2µm L=0.25µm

Scales well with Wf and L.

Physical model matches measurements of Ceff well:

Captures dependence on Wf and L.

Captures bias dependence.
 90-nm AMOS varactors: Qeff∝1/(Ceff Reff)

L=0.25µm

10x2µm

Decreases with Wf.

Decreases with L (due to L-indep. R term).

Extracted model limited by measurement accuracy (Rch).
Meas. 65-nm GP AMOS varactor at 94 GHz
Double-sided gate

• Ldrawn=60nm, Wf=0.55μm, Wtotal=27.5μm, CVAR=1.53fF/μm

• C variation: 25fF – 42fF, Q: 6 – 8 at 94 GHz
 45-nm LP CMOS AMOS n-well varactor

112×700nm×45nm

• Ldrawn=45nm, W f=0.7μm, W total=78.4μm, CVAR=1.07fF/μm

• C variation: 58fF – 84fF, Q= 6-8.5 at 94 GHz
 MIM Capacitor
Figures of merit
Capacitance per area
Quality factor Q
Capacitance to
substrate
Issues with reliability
Very good linearity
Applications
VCOs
Low-noise amplifiers
mixers
 Measured vs. Modelled Characteristics
2.5 1000
° Metal 8 Metal 8 Metal
Capacitance(pF)

Q-Factor
2.0 Q 100 CTM
CBM
Metal 7
DA-MiM
1.5 10
Metal 6
C

1.0 1 Cross-sectional view of DA

MiM_Cap
0 10 20 30 40 50
Frequency (GHz) LCTM RCTM CMiM RCBM LCBM
° °
CBM
CTM CO
X
DN
W

Csub Rsub

° SUB
Equivalent circuit used for MiM_Cap
model
 HF MIM capacitor equiv. ckt.

use reversed-
biased n-well
for good
substrate
isolation

58
 MOM capacitor

Uses the fringing capacitance between dense metals

Requires no additional process option (comes for “free”)
Lower Q than a MIM capacitor
Extraction of simplified ckt. for MIM/MOM cap
L R C

CT CB
C OX

Rs Cs
CT CB
Z1

Z2
L R C

CT C OX CB

−1 −1

Cmim =
[ ℑ[−Y 12 ]]
R=RTOPRBO =ℜZ11Z22−Z12−Z21 
 Rs Cs

−1
[ ℑZ21 ] Rsub =ℜZ21 
COX=

60
 HF resistor equivalent circuit

W-plug RCO RCO

Rend Rsheet Rend CoSi

STI

T-circuit imposes use of Z parameters.

2-circuit is more accurate for long resistors but is in

most cases not necessary.
61
 HF resistor equivalent circuit extraction

ℑZ 11Z22−Z12−Z21  R=ℜZ11Z22−Z12−Z21 

L=

−1
[ ℑZ21 ] Rsub =ℜZ21 
COX=
 62
 RF pads

Top metal only

Reversed-biased salicided n-well or metal-1 grounded
n-well

63
 Using ASITIC to calculate HF equiv. ckt.
parasitic elements of passive components
MIM caps, poly resistors, varactors have identical substrate
network (Rsub, Csub)

Use ASITIC to −model the substrate network for a metal

line of similar width and length,

MIM caps and poly resistors are realized in the oxide, above the
silicon substrate

Use ASITIC to −model Cox, L, R for a metal line of similar

width and length and located at the same distance from the
substrate as the MIM cap or poly resistor
64
 Summary
Inductors and transformers: main design components available to
HF circuit designers
Unlike transistors, they are almost insensitive to process variation
Inductors and transformers are scalable to at least 200 GHz
Modelling of passives as critical as the transistor model
In Si HF ICs t-line matching should be avoided < 100 GHz
because of large area
Varactors, capacitors and resistors have RLC parasitics which
must be accurately modelled at HF