IRFP460A, SiHFP460A

Vishay Siliconix

Power MOSFET

FEATURES
PRODUCT SUMMARY
• Low Gate Charge Qg Results in Simple Drive
VDS (V) 500
Requirement Available

RDS(on) (Ω) VGS = 10 V 0.27

• Improved Gate, Avalanche and Dynamic dV/dt RoHS*
Qg (Max.) (nC) 105 Ruggedness COMPLIANT

Qgs (nC) 26 • Fully Characterized Capacitance and Avalanche Voltage

Qgd (nC) 42 and Current
Configuration Single • Effective Coss Specified
D
• Compliant to RoHS Directive 2002/95/EC

TO-247 APPLICATIONS
• Switch Mode Power Supply (SMPS)
• Uninterruptable Power Supply
G • High Speed Power Switching

TYPICAL SMPS TOPOLOGIES

S
D • Full Bridge
G S
• PFC Boost
N-Channel MOSFET

ORDERING INFORMATION
Package TO-247
IRFP460APbF
Lead (Pb)-free
SiHFP460A-E3
IRFP460A
SnPb
SiHFP460A

ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted

PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 500
V
Gate-Source Voltage VGS ± 30
TC = 25 °C 20
Continuous Drain Current VGS at 10 V ID
TC = 100 °C 13 A
Pulsed Drain Currenta IDM 80
Linear Derating Factor 2.2 W/°C
Single Pulse Avalanche Energyb EAS 960 mJ
Repetitive Avalanche Currenta IAR 20 A
Repetitive Avalanche Energya EAR 28 mJ
Maximum Power Dissipation TC = 25 °C PD 280 W
Peak Diode Recovery dV/dtc dV/dt 3.8 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150
°C
Soldering Recommendations (Peak Temperature) for 10 s 300d
10 lbf · in
Mounting Torque 6-32 or M3 screw
1.1 N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 4.3 mH, Rg = 25 Ω, IAS = 20 A (see fig. 12).
c. ISD ≤ 20 A, dI/dt ≤ 125 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91234 www.vishay.com
S09-1284-Rev. B, 13-Jul-09 1
IRFP460A, SiHFP460A
Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - 40
Case-to-Sink, Flat, Greased Surface RthCS 0.24 - °C/W
Maximum Junction-to-Case (Drain) RthJC - 0.45

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 500 - - V
VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.61 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V
Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA
VDS = 500 V, VGS = 0 V - - 25
Zero Gate Voltage Drain Current IDSS µA
VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-Source On-State Resistance RDS(on) VGS = 10 V ID = 12 Ab - - 0.27 Ω
Forward Transconductance gfs VDS = 50 V, ID = 12 Ab 11 - - S
Dynamic
Input Capacitance Ciss - 3100 -
VGS = 0 V,
Output Capacitance Coss VDS = 25 V, - 480 -
f = 1.0 MHz, see fig. 5
Reverse Transfer Capacitance Crss - 18 -
pF
VDS = 1.0 V, f = 1.0 MHz 4430
Output Capacitance Coss
VGS = 0 V VDS = 400 V, f = 1.0 MHz 130
Effective Output Capacitance Coss eff. VDS = 0 V to 400 Vc 140
Total Gate Charge Qg - - 105
ID = 20 A, VDS = 400 V,
Gate-Source Charge Qgs VGS = 10 V - - 26 nC
see fig. 6 and 13b
Gate-Drain Charge Qgd - - 42
Turn-On Delay Time td(on) - 18 -
Rise Time tr - 55 -
VDD = 250 V, ID = 20 A, ns
Turn-Off Delay Time td(off) RG = 4.3 Ω, RD = 13 Ω, see fig. 10b - 45 -
Fall Time tf - 39 -
Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current IS MOSFET symbol D - - 20

showing the A
integral reverse
Pulsed Diode Forward Currenta
G
ISM p - n junction diode - - 80
S

Body Diode Voltage VSD TJ = 25 °C, IS = 20A, VGS = 0 Vb - - 1.8 V

Body Diode Reverse Recovery Time trr - 480 710 ns
TJ = 25 °C, IF = 20 A, dI/dt = 100 A/µsb
Body Diode Reverse Recovery Charge Qrr - 5.0 7.5 µC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS.

www.vishay.com Document Number: 91234

2 S09-1284-Rev. B, 13-Jul-09
 IRFP460A, SiHFP460A
Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

102 102
VGS
Top 15 V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

10 V
8.0 V 150 °C
7.0 V
10 6.0 V 10
5.5 V
5.0 V 25 °C
Bottom 4.5 V

1 1
4.5 V

20 µs Pulse Width 20 µs Pulse Width

TC = 25 °C VDS = 50 V
0.1 0.1
0.1 1 10 102 4.0 5.0 6.0 7.0 8.0 9.0

91234_01 VDS, Drain-to-Source Voltage (V) 91234_03 VGS, Gate-to-Source Voltage (V)

Fig. 1 - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics

102
RDS(on), Drain-to-Source On Resistance

3.0
VGS ID = 20 A
Top 15 V VGS = 10 V
ID, Drain-to-Source Current (A)

10 V 2.5
8.0 V
7.0 V
6.0 V 2.0
(Normalized)

5.5 V
5.0 V
Bottom 4.5 V
10 1.5

4.5 V 1.0

0.5
20 µs Pulse Width
TC = 150 °C
1 0.0
1 10 102 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160

91234_02 VDS, Drain-to-Source Voltage (V) 91234_04 TJ, Junction Temperature (°C)

Fig. 2 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 91234 www.vishay.com

S09-1284-Rev. B, 13-Jul-09 3
IRFP460A, SiHFP460A
Vishay Siliconix

105 102
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted

ISD, Reverse Drain Current (A)

Crss = Cgd
104 Coss = Cds + Cgd
150 °C
Capacitance (pF)

Ciss 10
25 °C
103

102
Coss
1

10
Crss
VGS = 0 V
1 0.1
1 10 102 103 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

91234_05 VDS, Drain-to-Source Voltage (V) 91234_07 VSD, Source-to-Drain Voltage (V)

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage

20 103
ID = 20 A Operation in this area limited
VGS, Gate-to-Source Voltage (V)

VDS = 400 V by RDS(on)

16
ID, Drain Current (A)

VDS = 250 V
102
12 VDS = 100 V
10 µs

8 100 µs
10

4 1 ms
TC = 25 °C
For test circuit TJ = 150 °C
see figure 13 10 ms
Single Pulse
0 1
0 20 40 60 80 100 10 102 103 104

91234_06 QG, Total Gate Charge (nC) 91234_08 VDS, Drain-to-Source Voltage (V)

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area

www.vishay.com Document Number: 91234

4 S09-1284-Rev. B, 13-Jul-09
 IRFP460A, SiHFP460A
Vishay Siliconix

RD
VDS

VGS
D.U.T.
20 RG
+
- VDD

10 V
ID, Drain Current (A)

15
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

10 Fig. 10a - Switching Time Test Circuit

VDS
5
90 %

0
25 50 75 100 125 150
10 %
91234_09 TC, Case Temperature (°C) VGS
td(on) tr td(off) tf

Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms

1
Thermal Response (ZthJC)

D = 0.5

0.1 0.2
0.1
0.05 PDM

0.02
10-2 0.01 Single Pulse t1
(Thermal Response) t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-3
10-5 10-4 10-3 10-2 0.1 1

91234_11 t1, Rectangular Pulse Duration (S)

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

VDS
15 V
tp

L Driver
VDS

RG D.U.T. +
- VDD
A
IAS IAS
20 V
tp 0.01 Ω

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

Document Number: 91234 www.vishay.com

S09-1284-Rev. B, 13-Jul-09 5
IRFP460A, SiHFP460A
Vishay Siliconix
EAS, Single Pulse Avalanche Energy (mJ)

2400 620
ID
Top 8.9 A

VDSav, Avalanche Voltage (V)

2000 13 A
Bottom 20 A 600
1600

1200 580

800
560
400

0 540
25 50 75 100 125 150 0 4 8 12 16 20

91234_12c Starting TJ, Junction Temperature (°C) 91234_12d IAV, Avalanche Current (A)

Fig. 12c - Maximum Avalanche Energy vs. Drain Current Fig. 12d - Typical Drain-to-Source Voltage vs.
Avalanche Current

Current regulator
Same type as D.U.T.

QG 50 kΩ
10 V 12 V 0.2 µF
0.3 µF

QGS QGD +
VDS
D.U.T. -

VG
VGS

3 mA

Charge
IG ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

www.vishay.com Document Number: 91234

6 S09-1284-Rev. B, 13-Jul-09
 IRFP460A, SiHFP460A
Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

RG • dV/dt controlled by RG +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor "D"
• D.U.T. - device under test

Driver gate drive

P.W.
Period D=
P.W. Period

VGS = 10 V*

D.U.T. ISD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

* VGS = 5 V for logic level devices

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91234.

Document Number: 91234 www.vishay.com

S09-1284-Rev. B, 13-Jul-09 7
 Package Information
www.vishay.com
Vishay Siliconix
TO-247AC (High Voltage)
VERSION 1: FACILITY CODE = 9

MILLIMETERS MILLIMETERS
DIM. MIN. MAX. NOTES DIM. MIN. MAX. NOTES
A 4.83 5.21 D1 16.25 16.85 5
A1 2.29 2.55 D2 0.56 0.76
A2 1.50 2.49 E 15.50 15.87 4
b 1.12 1.33 E1 13.46 14.16 5
b1 1.12 1.28 E2 4.52 5.49 3
b2 1.91 2.39 6 e 5.44 BSC
b3 1.91 2.34 L 14.90 15.40
b4 2.87 3.22 6, 8 L1 3.96 4.16 6
b5 2.87 3.18 ØP 3.56 3.65 7
c 0.55 0.69 6 Ø P1 7.19 ref.
c1 0.55 0.65 Q 5.31 5.69
D 20.40 20.70 4 S 5.54 5.74
Notes
(1) Package reference: JEDEC® TO247, variation AC
(2) All dimensions are in mm
(3) Slot required, notch may be rounded
(4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the
outermost extremes of the plastic body
(5) Thermal pad contour optional with dimensions D1 and E1
(6) Lead finish uncontrolled in L1
(7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm
(8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4
dimension at maximum material condition

Revision: 19-Oct-2020 1 Document Number: 91360

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Package Information
www.vishay.com
Vishay Siliconix
VERSION 2: FACILITY CODE = Y
A A
4
E 7 ØP (Datum B)
B
E/2 S A2 Ø k M DBM
3 R/2 ØP1
A
D2
Q

4 4
2xR
D D1
(2)

1 2 3 D 4
Thermal pad
5 L1

C L 4
E1
See view B A
0.01 M D B M
2 x b2 C View A - A
2x e
3xb
b4 A1
0.10 M C A M
(b1, b3, b5)
Planting Base metal
Lead Assignments
1. Gate D DE E
2. Drain
3. Source (c) c1
C C
4. Drain
(b, b2, b4)
(4)
Section C - C, D - D, E - E
View B

MILLIMETERS MILLIMETERS
DIM. MIN. MAX. NOTES DIM. MIN. MAX. NOTES
A 4.58 5.31 D2 0.51 1.30
A1 2.21 2.59 E 15.29 15.87
A2 1.17 2.49 E1 13.72 -
b 0.99 1.40 e 5.46 BSC
b1 0.99 1.35 Øk 0.254
b2 1.53 2.39 L 14.20 16.25
b3 1.65 2.37 L1 3.71 4.29
b4 2.42 3.43 ØP 3.51 3.66
b5 2.59 3.38 Ø P1 - 7.39
c 0.38 0.86 Q 5.31 5.69
c1 0.38 0.76 R 4.52 5.49
D 19.71 20.82 S 5.51 BSC
D1 13.08 -
Notes
(1) Dimensioning and tolerancing per ASME Y14.5M-1994
(2) Contour of slot optional
(3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
(4) Thermal pad contour optional with dimensions D1 and E1
(5) Lead finish uncontrolled in L1
(6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")
(7) Outline conforms to JEDEC outline TO-247 with exception of dimension c

Revision: 19-Oct-2020 2 Document Number: 91360

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Package Information
www.vishay.com
Vishay Siliconix
VERSION 3: FACILITY CODE = N
A
A

D2
B E P1
R/2 P
N A2

K M D BM
R

D1
D

D
L1

L
b4 C E1
b2 e A1
b 0.01 M D B M

0.10 M C A M
b1, b3, b5
Base metal

c1
c

b, b2, b4
Plating

MILLIMETERS MILLIMETERS
DIM. MIN. MAX. DIM. MIN. MAX.
A 4.65 5.31 D2 0.51 1.35
A1 2.21 2.59 E 15.29 15.87
A2 1.17 1.37 E1 13.46 -
b 0.99 1.40 e 5.46 BSC
b1 0.99 1.35 k 0.254
b2 1.65 2.39 L 14.20 16.10
b3 1.65 2.34 L1 3.71 4.29
b4 2.59 3.43 N 7.62 BSC
b5 2.59 3.38 P 3.56 3.66
c 0.38 0.89 P1 - 7.39
c1 0.38 0.84 Q 5.31 5.69
D 19.71 20.70 R 4.52 5.49
D1 13.08 - S 5.51 BSC
ECN: E20-0545-Rev. F, 19-Oct-2020
DWG: 5971
Notes
(1) Dimensioning and tolerancing per ASME Y14.5M-1994
(2) Contour of slot optional
(3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
(4) Thermal pad contour optional with dimensions D1 and E1
(5) Lead finish uncontrolled in L1
(6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")

Revision: 19-Oct-2020 3 Document Number: 91360

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Revision: 01-Jan-2019 1 Document Number: 91000