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91 views2 pages

17EC63

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Kalyan Hv
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Save trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com GBS Scinlshils USN h Semester B.E. Degree Examination, June/July 2018. VLSI Design ‘Time: he. an 80 Note: Answer any FIVE full questions, choosing one full question frogege mite. ‘Module-1 1a. Discuss the working of pMOS enhancement mode transistor fperation@ith neat diagrams. b. Explain the CMOS inverter DC characteristics hig! (06 Marks) ightiggfne operation. ‘io Marks) oR 2a. With neat diagrams discuss the nMOS fabrication process 9 Marks) Explain the following (Channel length modulation Gi) Noise Margin or marks) Mos 3 a, Discuss the CMOS design style withrdiog (05 Marks) 1b Draw the stick ing 108 logic: costars rth an. oxgmple to each, (06 Marks) c ©. Discuss the different contact or 4a. With adiagram derive apeN@aafeion J9r shect resistance and mention the R, values of metal, and n transistor chagglls for ichnology. (05 Marks) be. Derive an equation for igs time and fall time with respect to CMOS inverter. (@8 Marks) ©, Draw the circuit agtick Wagram for 2 /p NOR gate using CMOS logic. (3 Marks) 5a. Explai field) Constant vollage scaling models with a diagram and sealing effect table. coe marks) b. Disc sms associated in VLSI design. How do you reduce them? (05 Marks) c. Discuss ss architectures. (05 Marks) oR 6 a Discuss WWMsign of a 4-bit adder. (7 Mars) ‘With relevant diagram discuss Manchester carry chain operation. (05 Marks) eo Qgotaigge cary select adder with a diagram, (04 Marks) Modute-4 uss the programmable logic array with its structure and floor plan. (0s Marks) ,igcuss the architectural issue’ related to VEST sub system design, (ooatarks) iscuss the design of Data selectors. (os Marks) 10f2 BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiative Save trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com OR 8 a, Explain the architecture of field programmable gate array. (10 Ma b. Discuss the FPGA abstractions with a diagram, Mas ee ee apr 8. Discuss the ASM chart for fip fp with ts NAND los, =Z) (aan) oR 10 a. Explain logic verification process with its functional equivaler (06 Marks) b. Discuss the design for manufacturability. (6 Marks) ¢ Discuss the Ad-hoc testing, (4 Marks) 2of2 BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiative

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