United States Patent (19) 11) Patent Number: 4,864,547

Krsna (45) Date of Patent: Sep. 5, 1989

(54) REGULATED ULTRASONIC GENERATOR FOREIGN PATENT DOCUMENTS
75 Inventor: Steve Krsna, Wrightstown, N.J. 0187282 7/1986 European Pat. Off. .
0274136 7/1988 European Pat. Off. .
73) Assignee: Crestek, Inc., Trenton, N.J. OTHER PUBLICATIONS
(21) Appl. No.: 865,255 Sun Luin Kuo, "Half-Bridge Transistor Inverter for
DC Power Conversion,' IEEE Transactions on Indus
(22 Filed: May 20, 1986 trial Electronics and Control Instrumentation, IECI-21:4
(11/74).
511 Int. Cl." ............................................. G10K11/00 Primary Examiner-Thomas H. Taroza
(52) a u a was a 367/137; 310/317 Assistant Examiner-Tod Swann
58 Field of Search ................ 367/137, 138; 310/317, Attorney, Agent, or Firm-Limbach, Limbach & Sutton
310/316, 118; 73/642,596,602; 363/55, 56,58,
93, 132; 318/118 57 ABSTRACT
A regulated ultrasonic generator operable for supplying
(56) References Cited a driving signal to an ultrasonic transducer is disclosed.
U.S. PATENT DOCUMENTS The generator includes: a power supply; a bridge in
2,778,002 1/1957 Howry ................................ 367/137
verter circuit for generating a power signal having two
3,460,025 8/1969 De Prisco .
alternating components of opposite potential; a timing
3,491,250 1/1970 Shob . circuit for generating a timing signal equal in frequency
3,582,733 6/1971 Brubaker ........................ 310/316X to the desired frequency of the power signal; a bridge
3,622,960 1 1/1971 Malba et al. ........................ 367/137 driver circuit for periodically generating base drive
3,715,649 2/1973 Ravas. signals for switching on the bridge inverter circuit; a
3,715,710 2/1973 Berstein et al. ..................... 367/137 bridge modulating circuit for controlling the amount of
3,979,660 9/1976 Moore. time during each cycle that the bridge inverter circuit is
4,044,297 8/1977 Nobur et al. ................... 310/317 X on so as to regulate the power content of the power
4,271,705 6/1981 Crostack ............................. 367/137 signal; and means for supplying the power signal to the
4,277,710 7/1981 Harwood et al. .............. 318/118 X ultrasonic transducer.
4,282,452 8/1981 Hassler et al. ...................... 367/137
4,347,592 8/1982 Langeraar ... ... 367/138
4,504,762 3/1985 Meyer et al. ........................ 367/137 28 Claims, 8 Drawing Sheets

DUTY CYCLE
CONTROLLER 32
DUTY CYCLE
FREQUENCY ADUST
ADST
28
POWER AMPLITUDE ADJUST
CONTROLLER
SELECT
20
FULL/HALF BRIDGE TRANSFORMER ULTRASONIC
WAVE SWITCH INVERTER TRANSDUCER
U.S. Patent Sep 5, 1989 Sheet 1 of 8 4,864,547

29

09 92
U.S. Patent Sep. 5, 1989 Sheet 2 of 8 4.864,547
06

89
U.S. Patent Sep. 5, 1989 Sheet 3 of 8 4,864,547

98
U.S. Patent Sep. 5, 1989 Sheet 5 of 8 4,864,547
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U.S. Patent 4,864,547

55
U.S. Patent Sep. 5, 1989 Sheet 8 of 8 4,864,547

INVERSE TIMING SIGNALU

MODULATOR SIGNAL JULIUUJ UUUU
CHANNE A CONTROL
SIGNAL Jl l l l l l l Il
CHANNEL B CONTROL
SIGNAL - -- - -- l l
POWER SIGNAL \\ N-N \ \\
SOFT START CONTROL SIGNAL -
MODULATOR SIGNAL

POWER SIGNAL N

DUTY CYCLE CONTROL SIGNAL

CHANNE A CONTROL SIGNAL l l- - -
CHANNEL. B CONTROL SIGNAL fl l l l

FIG-0.
 4,864,547 2
1.
SUMMARY OF THE INVENTION
REGULATED ULTRASONIC GENERATOR
In accordance with the illustrated preferred embodi
BACKGROUND OF THE INVENTION ment, the present invention provides a regulated ultra
1. Field of the Invention
sonic generator operable for supplying a driving signal
This invention relates generally to ultrasonic cleaning to an ultrasonic transducer. The generator includes: a
equipment, and relates more particularly to a regulated power supply; a bridge inverter circuit powered by the
ultrasonic generator operable for supplying a driving power supply for generating a power signal having two
signal to an ultrasonic transducer.
alternating components of opposite potential, where the
2. Description of the Relevant Art
10 bridge inverter circuit includes four power transistors
The process of ultrasonic cleaning includes the steps configured in two pairs thereof, and where each pair of
of immersing a part to be cleaned in a suitable liquid power transistors generates one component of the
medium, and agitating that medium with high-fre power signal; a timing circuit for generating a timing
quency sound energy for a short period of time. The 15 signal equal in frequency to the desired frequency of the
high-frequency sound energy produces alternating rar power signal; a bridge driver circuit responsive to the
efactions and compressions of the liquid. Small vapor timing signal for periodically generating base drive
cavities or bubbles form through cavitation during rar signals that when supplied to the bases of the power
efactions and collapse during compressions. The forma transistors cause the power transistors to switch on; a
tion and collapse of the vapor cavities create shock 20 bridge modulating circuit coupled between the bridge
waves that impinge on the surface of the part and, driving circuit and the bridge inverter circuit for selec
through a scrubbing action, displace or loosen particu tively connecting the base drive signals to and discon
late matter. necting the base drive signals from the bases of the
The high-frequency sound energy is typically pro power transistors to define the amount of time during
duced by some form of a displacement transducer, such 25 each cycle of the power signal that the power transis
as ferromagnetic or piezoelectric, that converts an elec tors are on so as to regulate the power content of the
trical driving signal into mechanical motion. The elec power signal; and means for supplying the power signal
trical driving signal is generated and supplied to the to the ultrasonic transducer.
ultrasonic transducer by an ultrasonic generator. One Preferably, the bridge inverter circuit supplies the
factor that affects the degree of scrubbing action of an 30 power signal to a transformer that reshapes the power
ultrasonic cleaner is the frequency of the sound energy, signal to a sine wave and converts it to a voltage that is
which commonly ranges between 20 KHz and 120 appropriate for the ultrasonic transducer. The timing
KHz. The size and number of the cavitation cavities and base driving circuits define the frequency of the
varies with the frequency of the sound energy, with power signal independently from the operation of the
higher frequencies producing more numerous cavities 35 power signal generation portion of the generator, so
of smaller size than lower frequencies. The selection of that the frequency of operation is not affected by
an optimum frequency is difficult because it varies with changes to the transducer or fluid. The bridge modulat
each cleaning application. ing circuit monitors the current of the power signal and
Another factor that affects ultrasonic cleaning is the tion modulates the power signal using a pulse width modula
amplitude of the sound energy, which is proportional to 40 technique in order to regulate its power. A soft
the electrical energy supplied to the ultrasonic trans initial start circuit also modulates the power signal during the
turn-on of the generator. Using an optional duty
ducer. In order for cavitation to occur in a liquid me cycle controller,
dium, the amplitude of the sound energy must exceed a signal prior to thetheend generator can shut off the driving
of each power supply cycle to
certain threshold value. The application of sound en
ergy over and above this threshold value causes an 45 allow for degassing.
increase in the overall quantity of the cavitation cavi The regulated ultrasonic generator of the present
ties, which may or may not be desirable for a particular invention includes several advantageous features. One
cleaning application. feature is that both the frequency and the amplitude of
Still another factor that affects ultrasonic cleaning is the power signal are independently adjustable and inde
the degree of entrapment of air in the liquid medium, 50 pendently regulated. Another feature is that the po
which resists the collapse of the cavitation cavities and wer/degassing duty cycle can be varied. Still another
reduces the effectiveness of cleaning. The amount of feature is that open circuit and short circuit protection is
entrapped air can be reduced by periodically switching provided. A major advantage of the regulated ultra
sonic generator of the present invention over prior
off the ultrasonic transducer to permit adjacent air bub generators
bles to coalesce, float to the surface, and escape, in a 55 is that the frequency and amplitude of the
process known as degassing modulation. power signal is not effected by variations of the power
Prior ultrasonic generators exhibit certain shortcom supply, transducer, or fluid.
ings that limit their effectiveness. One such shortcoming The features and advantages described in the specifi
is that prior ultrasonic generators do not regulate the cation are not all inclusive, and particularly, many addi
frequency and amplitude of the driving signal very 60 tional features and advantages will be apparent to one of
closely, so that changes in the operational environment, ordinary skill in the art in view of the drawings, specifi
such as the temperature or fluid level of the liquid me cation and claims hereof. Moreover, it should be noted
dium, can produce an undesired shift in frequency or that the language used in the specification has been
amplitude that, in turn, degrades cleaning performance. principally selected for readability and instructional
Another shortcoming is that many prior art ultrasonic 65 purposes, and may not have been selected to delineate
generators do not offer protection against short circuit or circumscribe the inventive subject matter, resort to
or open circuit operation. Under those conditions, such the claims being necessary to determine such inventive
generators will blow fuses or even transistors. subject matter.
 4,864,547 4.
3
BRIEF DESCRIPTION OF THE DRAWINGS
inverter 16 (FIG. 3). If the full/half wave switch 14 is
closed, the signal on the output terminal 42 is rectified
FIG. 1 is a block diagram of a regulated ultrasonic and has a frequency of twice the frequency of the AC
generator according to the present invention. input power signal. In such case, the frequency of the
FIG. 2 is a schematic diagram of a power supply signal at terminal 42 will equal 120 Hz, assuming that
circuit of the regulated ultrasonic generator. the AC input power has a frequency of 60 Hz. If the
FIG. 3 is a schematic diagram of one half of a bridge full/half wave switch 14 is open, the signal on the out
inverter circuit and portions of a base driver circuit and put terminal 42 resembles the positive half of the AC
a bridge modulating circuit of the regulated ultrasonic input power signal. The switch 40 determines which
generator. O half of the AC input power signal is supplied to the
FIG. 4 is a schematic diagram of the other half of the output terminal 42 when the full/half wave switch 14 is
bridge inverter circuit and additional portions of the open. In parallel with the diode bridge 36 is another
base driver and bridge modulating circuits of the regu diode rectifier 44 that supplies rectified power at node
lated ultrasonic generator. 46 for connection to the duty cycle controller 32 (FIG.
FIG. 5 is a schematic diagram of an output trans 15 9). From the midpoint of the diode rectifier 44, a diode
former stage of the regulated ultrasonic generator. 48 supplies rectified power to the bridge driver 22
FIG. 6 is a schematic diagram of another portion of (FIG. 6) via a node 50 and to a DC power supply 52
the bridge driver circuit of the regulated ultrasonic (FIG. 7) via a series-connected resistor 54 and a node
generator. S6.
FIG. 7 is a schematic diagram of another portion of 20 The bridge inverter 16, as illustrated in FIGS. 3 and
the bridge modulating circuit of the regulated ultrasonic 4, includes four power transistors 58, 60, 62, and 64
generator. connected in a bridge configuration between the output
FIG. 8 is a schematic diagram of the remainder of the terminal 42 of the power supply 12 and node 66. Node
bridge modulating circuit of the regulated ultrasonic 66, as shown in FIG. 7, is slightly above common poten
generator. 25 tial due to the 0.1 ohm series-connected resistor 67,
FIG. 9 is a schematic diagram of a duty cycle control which is used for current sensing by the power control
ler of the regulated ultrasonic generator. ler 28. All of the power transistors 58, 60, 62, and 64 are
FIG. 10 is a diagram of various signals present preferably bipolar transistors of the same polarity, pref.
throughout the regulated ultrasonic generator. erably NPN, as shown. The collectors of transistors 58
30 and 62 are connected to terminal 42, while the emitter
DETAILED DESCRIPTION OF THE of transistor 58 is connected to a node 68 and the emitter
PREFERRED EMBODMENT of transistor 62 is connected to a node 70. The emitters
FIGS. 1 through 10 of the drawings depict various of transistors 60 and 64 are connected to node 66, while
preferred embodiments of the present invention for the collector of transistor 60 is connected to node 68
purposes of illustration only. One skilled in the art will 35 and the collector of transistor 64 is connected to node
readily recognize from the following discussion that 70. Four diodes 72 are connected across the power
alternative embodiments of the structures and methods transistors to protect against induced reverse voltages.
illustrated herein may be employed without departing A filter capacitor 74 is connected between terminal 42
from the principles of the invention described herein. and node 66 for attenuating the high-frequency switch
The preferred embodiment of the present invention is ing noise generated by the bridge inverter 16.
a regulated ultrasonic generator operable for supplying The bridge inverter 16 converts the 120 Hz full-wave
a driving signal to an ultrasonic transducer. A power power signal supplied by the power supply 12 into a
portion of the regulated ultrasonic generator 10, as high-frequency power signal for supplying to the ultra
shown in FIG. 1, includes a power supply 12, a full/half sonic transducer 20. Node 68 is connected directly to
wave switch 14, a bridge inverter 16, and a transformer 45 one terminal of the primary winding of transformer 18,
18 all connected in series and operable for supplying an as shown in FIG. 5, while node 70 is coupled through
ultrasonic driving signal to an ultrasonic transducer 20. parallel capacitors 76 to the other terminal of the pri
A control portion of the generator 10 includes a bridge mary winding of transformer 18. The secondary wind
driver 22, an oscillator 24, a modulator 26, a power ing of the transformer 18 is coupled to the ultrasonic
controller 28, a soft start circuit 30, and an optional duty 50 transducer 20, with a series-connected capacitor 78
cycle controller 32, all of which are coupled either inserted in one connecting line between the transducer
directly or indirectly to the bridge inverter 16. The and the transformer.
individual schematic diagrams of the component ele By means described below, the power transistors 58,
ments of the generator 10, as seen in FIGS. 2 through9, 60, 62, and 64 are alternately switched on and off by the
will be described below, starting with the power por 55 bridge driver 22 and the modulator 26 at a high-fre
tion of the generator and then shifting to the control quency rate, which in the illustrated preferred embodi
portion. ment is about 40 KHz. The power transistors are config
The power supply 12, as shown in FIG. 2 receives ured in two pairs, with transistors 58 and 64 forming
input power from a single-phase alternating-current one pair and transistors 60 and 62 forming the other
power source via input terminals 34. Preferably, the pair. The pairs of power transistors are switched alter
input power is fused and filtered prior to entering the nately; in other words, the transistor pair 58-64 is
power supply 12. From the input terminals 34, the input switched on and transistor pair 60-62 is switched off
power is rectified by a full wave diode bridge rectifier during one half of the high-frequency cycle, and during
36. The negative side 38 of the output half of the diode the other half of the high-frequency cycle the transistor
bridge 36 is connected to common, while the positive 65 pair 58-64 is switched off and the transistor pair 60–62
side is connected through a switch 40 to the full/half is switched on. The above statement should be qualified
wave switch 14. From the switch 14, the rectified signal in that the bridge driver 22 permits each transistor pair
is supplied through output terminal 42 to the bridge to be switched on during its corresponding half of the
 4,864,547 6
5
high-frequency cycle, but the modulator 26 may limit former 92. The diode 110 is a zener diode that protects
the duration that the transistor pair is switched on to the gate of transistor 114 from an over-voltage condi
something less than a full half cycle, or may inhibit tion. The other terminal of the secondary winding 124 is
entirely the switching on of the transistor pair. connected to terminal 104 of the primary winding 90.
When transistor pair 58-64 is switched on, current The common connection between the diodes 118 and
flows from terminal 42, through transistor 58, through 120 is connected to one side of a capacitor 126, which is
node 68 and through the transformer 18, and then flows connected at the other side thereof to terminal 104 of
through node 70 and transistor 64 to node 66, which, as the primary winding 90. A high resistance resistor 128 is
stated above, is slightly above common potential. Con connected between node 50 and the common connec
versely, when transistor pair 60-62 is switched on, cur O tion between resistor 116 and diode 118. The drain
rent flows from terminal 42, through transistor 62, terminal of transistor 114 is coupled to common
through node 70 to the transformer 18, and then flows through a capacitor 130 to suppress transients. Clamp
through node 68 and transistor 60 to node 66. Thus, the ing diodes 132 and 134 restrict the voltage swings of
bridge inverter supplies an alternating current at the terminal 104 of the primary winding 90, with diode 132
high-frequency to the transformer 18, with each pair of 15 being connected between terminal 104 and common,
power transistors generating one component thereof. and with diode 134 being connected between terminal
The transformer 18 provides the necessary step-up in 104 and the positive side of capacitor 108. Capacitors
signal voltage to drive the transducer 20, and also pro 136 and 138 keep the voltage applied to terminal 140 of
vides isolation between the generator 10 and the trans the primary winding 90 at a mid-point between the
ducer. In addition, the transformer 18 preferably is 20 voltages that are alternately applied to terminal 104,
designed to have a leakage inductance between the with capacitor 136 being coupled between terminal 140
primary and secondary windings, which limits the cur and the positive side of capacitor 108, and with capaci
rent into the capacitive transducer 20, thereby trans tor 138 being coupled between terminal 140 and com
forming the power signal supplied by the bridge in O.
verter 16 into a driving signal that approximates a sine 25 In operation, the timing signal applied at node 88
WaVe. causes transistor 98 to alternately switch on and off at
The base driver circuit 22, shown in FIGS. 3, 4, and the high-frequency rate. When transistor 98 is switched
6, generates base drive signals to be supplied through on, any charge on terminal 104 of the primary 90 will
modulating transistors 80, 82, 84, and 86 of the modula flow through diode 108 and inductor 106 and through
tor 26 to the bases of the power transistors 58, 60, 62, 30 transistor 98 to common. The inductor 106 limits the
and 64 for switching the power transistors at the high voltage spikes that would otherwise be present due to
frequency rate. In reference now to FIG. 6, a high-fre the inductance of the transformer 92. During this time,
quency timing signal is generated by the oscillator 24 current induced in the secondary winding 124 is stored
and supplied to node 88 of the bridge driver 22. The in capacitor 126. When the timing signal goes low and
portion of the bridge driver circuit that is illustrated in 35 the transistor 98 is switched off, current flows from
FIG. 6 drives the primary winding 90 of a bridge driv capacitor 126 and through diode 118 and resistor 116 to
ing transformer 92 at the high-frequency rate with an pull up the voltage applied to the gate of transistor 114,
alternating current to induce base drive signals in four thus switching on transistor 114. When transistor 114 is
secondary windings 94. Node 88 is coupled through on, current flows from the positive side of the capacitor
resistor 96 to the gate terminal of a first bridge driving 108, through fuse 112 and transistor 114 to terminal 104.
transistor 98, and from there is coupled to common Since the capacitors 136 and 138 keep the voltage at
through resistor 100. The resistor 96 and a parallel con terminal 140 of the primary winding 90 at an intermedi
nected diode 102 comprise a wave-shaping network for ate voltage, such switching of the transistors 98 and 114
modifying the wave shape of the square-wave timing creates an alternating current through the primary
signal applied to node 88. The source terminal of the 45 winding 90, which in turn induces alternating currents
transistor 98 is connected to common, while the drain in the secondaries 94 that generate the base drive sig
terminal of the transistor is coupled to one terminal 104 nals.
of the primary winding 90 through an inductor 106 and Turning attention back to FIGS. 3 and 4, the remain
a diode 108. A diode 110 is connected in parallel with der of the bridge driver circuitry 22 can now be de
diode 108, while another diode 112 is connected in 50 scribed. As described above, alternating voltages are
parallel across the inductor 106. When transistor 98 is induced in the secondary windings 94 of the trans
switched on, it effectively connects to common the former 92. In reference first to the base drive circuitry
terminal 104 of the primary winding 90. associated with power transistor 64, one terminal 142 of
The primary winding 90 of the transformer 92 is the secondary winding 94 is coupled through a resistor
supplied an alternating current based on an electrical 55 144 and a modulating transistor 86 to the base of power
charge stored in a capacitor 108. One side of the capaci transistor 64, while the other terminal 146 of the sec
tor 108 is connected to common, while the positive side ondary winding is connected to node 66, which is near
is coupled to node 50 of the power supply 12 through a common potential. The source of the modulating tran
low-resistance resistor 110, which continuously charges sistor 86 is connected to the base of the power transistor
the capacitor. The positive side of the capacitor 108 is 60 64 and is also connected to the emitter of a PNP transis
also coupled through a fuse 112 to the drain terminal of tor 148. The base of the transistor 148 is connected to
a second bridge driving transistor 114. Preferably, both the gate of the modulating transistor 86 and to a node
bridge driving transistors 98 and 114 are field-effect 150 that receives a first modulating signal that controls
transistors. The source terminal of the transistor 114 is the switching of the transistors 86 and 148. The collec
connected to terminal 104 of the primary winding 90. 65 tor of the transistor 148 is coupled through node 152
The gate terminal of the transistor 114 is coupled and a capacitor 153 to common (see FIG. 8), is con
through a resistor 116 and two diodes 118 and 120 to a nected to the FIG. 3 portion of the bridge driver cir
terminal 122 of a secondary winding 124 of the trans cuitry through node 154, and is coupled to terminal 142
 4,864,547 8
7
of the secondary 94 through a diode 156 and to node 66 switches off the transistor 180. With the modulating
through a capacitor 158. The primary winding 160 of a transistor 80 switched on, the current generated in the
transformer 162 is connected in parallel across resistor secondary winding 94 flows through resistor 174 and
144. In odder to suppress transients, a resistor 164 and a the now-conductive modulating transistor 80 to the
capacitor 166 are connected in series between the termi base of the power transistor 58, switching it on. Thus,
nal 142 and node 66. the first modulating signal applied to node 150 causes
The first modulating signal, which controls the oper both power transistors 58 and 64 to switch on. Note that
ation of the modulating transistor 86 and the PNP tran during this half-cycle, the power transistor pair 60-62 is
sistor 148, is applied to the gate of transistor 86 and the switched off due to the opposite polarity of the base
base of transistor 148 through node 150. At the begin 10 drive signals generated by their associated secondaries
ning of a half-cycle, when a positive voltage exists at 94.
terminal 142 of the secondary and the modulating tran When the modulating transistor 86 is switched off by
sistor 86 is switched on and transistor 148 is switched a logic low voltage applied at node 150, current stops
off by a logic high voltage applied through node 150, flowing through the transformer 160, causing the PNP
current flows through the resistor 144 and the modulat 15 transistor 180 to switch on and the modulating transis
ing transistor to turn on the power transistor 64. When tor 80 to switch off, thereby switching off the power
the modulating transistor is switched off by a logic low transistor 58. The power transistors 58 and 64 then
voltage applied at node 150, transistor 148 switches on remain switched off through the remainder of the half
to rapidly switch off the power transistor 64. The cycle and through the succeeding half-cycle that turns
power transistor 64 then remains switched off through 20 on transistor pair 60-62. The modulating transistor 80
the remainder of the half-cycle and through the suc thus serves as a switch connected in series between the
ceeding half-cycle that turns on power transistor pair bridge driver transformer 92 and the power transistor
60-62. The modulating transistor 86 thus serves as a 58 and operable for selectively coupling the base drive
switch connected in series between the bridge driver signal generated by the secondary winding 94 to the
transformer 92 and the power transistor 64 and is opera 25 base of the power transistor.
ble for selectively coupling the base drive signal gener The power transistors 60 and 62 are coupled together
ated by the secondary winding 94 to the base of the as a pair in the same manner as described above in con
power transistor. nection with power transistors 58 and 64. The modulat
The power transistors 58 and 64 are coupled together ing transistor 82 is controlled directly by a second mod
as a pair, with transistor 64 being controlled directly by 30 ulating signal applied through node 204 to the gate of
the first modulating signal applied to node 150, and with transistor 82, while the other modulating transistor 84 is
transistor 58 being configured to follow the operation of controlled indirectly through transformer 206 and fol
transistor 64. In reference now to the circuitry associ lows the operation of transistor 82. The secondaries 94.
ated with power transistor 58, one terminal 172 of the of the bridge driver transformer 92 are configured such
secondary winding 94 is coupled through a limiting 35 that the base drive signals generated for the power
resistor 174 and a modulating transistor 80 to the base of transistor pair 58-64 are opposite in polarity to the base
power transistor 58, while the other terminal 176 of the drive signals generated for the other power transistor
secondary winding is connected to node 68. The source pair 60-62 so that the two transistor pairs can be
of the modulating transistor 8 is connected to the base of switched on only during alternate half-cycles.
the power transistor 58 and is also coupled through a 40 The circuitry of the oscillator 24, illustrated in FIG.
diode 178 back to the gate of the transistor 80, to the 7, includes a timer 210 and a D-type flip-flop. 212. The
emitter of a PNP transistor 180, and through a resistor timer 210, which is preferably one half of a 556 dual
182 and diode 184 back to terminal 172 of the secondary timer, is powered by the positive DC voltage available
94. The anode of diode 184 is also connected to one at node 56, which is also applied to the reset terminal of
terminal 186 of the secondary winding 187 of trans 45 the timer. The timer 210 is configured as an astable
former 162 and to the collector of transistor 180, and is oscillator, with the discharge, threshold, and trigger
coupled through a capacitor 188 to node 68. The other terminals coupled through a timing capacitor 214 to
terminal 190 of the secondary winding 187 is coupled common and through a fixed resistor 216 and an adjust
through a resistor 192 to the base of the transistor 180 able resistor 218 to the positive voltage at node 56. The
and through a diode 194 to the gate of the modulating 50 RC value of resistors 216 and 218 and capacitor 214
transistor 80. A zener diode 196 is coupled between the determine the frequency of the output signal of the
terminal 186 and the gate of the modulating transistor timer 210. The control terminal of the timer 210 is cou
80 to provide over-voltage protection to the gate. A pled to common through capacitor 220, while the out
resistor 198 is connected in parallel to the diode 196 and put terminal 221 of the timer 210 is connected to the
provides, in combination with resistors 182 and 192, 55 clock input terminal of the flip-flop. 212. One output
diodes 178 and 184, and capacitor 188, a biasing net terminal of the flip-flop 212 supplies a timing signal to
work for the transistors 58, 80, and 180. In order to node 222, while the inverse output terminal supplies an
suppress transients, a resistor 200 and a capacitor 202 inverse timing signal to node 22 and to the D input
are connected in series between the drain of the modu terminal of the flip-flop. The frequency of the output
lating transistor 80 and node 68. signal of the timer 210 is adjusted by changing the resis
When the first modulating signal, which is applied to tance of the adjustable resistor 218 until the timer fre
node 150, switches on the modulating transistor 86, quency is twice the desired frequency of the power
current flows through the resistor 144 and the modulat signal. The timing and inverse timing signals are square
ing transistor to turn on the power transistor 64. The waves equal in frequency to the desired frequency. The
base current of the power transistor 64 flows through 65 waveforms for the timer output signal and the timing
the transformer 162 and induces a current in the second signals are shown in FIG. 10. In the illustrated preferred
ary winding 187 thereof that flows through diode 194 embodiment, the timer output signal is an 80 KHz sig
and switches on the modulating transistor 80 and nal, while the timing signal output of the flip-flop. 212 is
 4,864,547 10
9
a 40 KHz square-wave. As shown in FIG. 8, the timing age that is applied to the negative terminal of the volt
signal at node 222 is coupled through an inverter 226 to age comparator 260 is shifted downward toward the
node 88, which is the entry point for the timing signal in negative DC voltage at node 250 by the action of the
the bridge driver 22, shown in FIG. 6. resistor ladder. For a given current through the resistor
The DC power supply 52, illustrated in FIG. 7, gen 67, the exact voltage applied to the negative input ter
erates positive and negative DC power for the control minai of the comparator 260 is determined by the set
circuitry of the generator 10. The input power supplied tings of the adjustable resistors 266 and 272. Preferably,
to the generator 10 is rectified through diode rectifier 44 resistor 272 is factory adjusted to calibrate the power
(FIG. 2) and diode 48, and flows through resistor 54 to controller 26, while resistor 266 is operator adjusted to
node 56. As seen in FIG. 7, node 56 is coupled to com 10 select the power output of the generator 10. When the
mon through a parallel-connected capacitor 228 and current flowing through the resistor 67 is at its desired
zener diode 230, the breakdown voltage of which deter level, the voltage applied to the negative input terminal
mines the voltage at node 56. The positive voltage at of the comparator 260 by the resistance ladder is equal
node 56 is supplied to various parts of the circuitry, as to common potential.
shown, and starts the timer 210 oscillating, which 15 The voltage comparator 260 generates a current
through the flip-flop 212 supplies the timing signal to error signal that indicates whether the current of the
node 88. The timing signal causes the two bridge driv power signal is less than or greater than desired. The
ing transistors 98 and 114 of the bridge driver circuit 22 output terminal of the voltage comparator 260 is cou
to switch on and off, which in turn applies an alternat pled through a resistor 280 to the control input terminal
ing current to the primary winding 90 of the trans 20 of a timer 282, which is preferably the other half of the
former 92 (FIG. 6). Current is induced in a secondary 556 dual timer that contains timer 210. Between the
winding 232, which supplies an alternating potential comparator 260 and the resistor 280, the output terminal
through node 234 to the common junction between of the comparator is coupled to common via a filter
diodes 236 and 238 (FIG. 7). This alternating potential capacitor 283, and is coupled back to the input terminal
is rectified by diode 236 into positive voltage and by 25 of the comparator through a series connected resistor
diode 238 into negative voltage. Capacitors 240 and 242 284 and capacitor 286, all of which provides a stabiliz
serve as filter capacitors, while resistors 244 and 246 ing filter that converts the digital output signal of the
serve as current limiting resistors. The zener diode 248 comparator into an analog signal that indicates the cur
regulates the negative voltage at node 250 to a fixed rent error. Additional signal conditioning of this analog
amount relative to common. During the initial start-up, 30 signal is performed by a resistor ladder consisting of
additional current is supplied to node 56 from the pri resistor 288 connected between the positive DC voltage
mary 90 of transformer 92 through node 252 and resis at node 56 and the control terminal of the timer 282, and
tor 254. resistor 290 and capacitor 292 connected in parallel
The modulator 26 and the power controller 28, between the control terminal of the timer and common.
shown in FIGS. 7 and 8, determine how long each 35 The timer 282 responds to the current error signal
power transistor pair is switched on during each half generated by the voltage comparator 260 and its associ
cycle. The power controller 28 senses the current of the ated circuitry to generate a modulator signal, which is
power signal supplied to the transformer 18 to drive the supplied through the output terminal 294 of the timer to
ultrasonic transducer 20, and compares that sensed cur node 296. The threshold terminal of the timer 282 is
rent to a reference that indicates the desired current of 40 connected to the common connection between resistor
the power signal. More specifically, the power control 216 and capacitor 214, so that the same sawtooth volt
ler 28 senses the voltage drop across the low-resistance age is applied to both timers 210 and 282. The trigger
resistor 67, which is connected in series between node terminal 298 of the timer 282 is coupled to the output
66 and common. The voltage upstream of the current terminal 221 of timer 210 through a network consisting
sensing resistor 67 is coupled to the negative terminal of 45 of a capacitor 300 and a resistor 302 connected in series
a voltage comparator 260 through fixed resistors 262 between terminal 221 and terminal 298, with terminal
and 264 and adjustable resistor 266. Resistor 262 and a 298 also coupled to the positive DC voltage at node 56
capacitor 268 that is connected between common and through a resistor 304 and a parallel clamp diode 306
resistor 262 filter the pulsating current through the and coupled to common through a resistor 308 and a
current-sensing resistor 67 to create a DC signal. The 50 parallel clamp diode 310. The timer 282 is triggered at
negative terminal of the voltage comparator 260 is also the same rate as the timer 210 output signal, that is,
coupled to the negative DC voltage at node 250 twice the frequency of the timing signal.
through a fixed resistor 270 and an adjustable resistor The voltage of the current error signal generated by
272, so that, the voltage upstream of the resistor 67 is the comparator 260 and applied to the control terminal
coupled through a voltage divider or resistor ladder to 55 of the timer 282 determines the length of the pulses in
the voltage comparator. Also, the negative terminal of the modulator signal generated by the timer 282. When
the voltage comparator 260 is coupled to the positive the current error signal is at a relatively high voltage,
DC voltage at node 56 through a clamping network which corresponds to the case where the current of the
consisting of two zener diodes 274 and resistors 276 and power signal is significantly less than desired, the modu
244. The positive terminal of the voltage comparator lator signal remains at the logic high voltage because
260 is coupled to common through a resistor 278 to the charge on the capacitor 214 never reaches the high
provide a reference voltage to the comparator down control voltage needed to reset the output signal of the
stream of the current-sensing resistor 67. timer 282. When the current error signal is at a rela
As current flows through the current-sensing resistor tively low voltage, which corresponds to the case
67, the voltage drop across the resistor is equal to the 65 where the current of the power signal is more than
current times the resistance of the resistor, thus, relative desired, the modulator signal rises to the logic high
to common, the voltage upstream of the resistor 67 is a voltage at the beginning of each pulse of the timer 210,
measure of the current flowing therethrough. The volt but resets to the logic low voltage soon afterwards. In
 4,864,547 12
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effect, the timer 282 provides pulse width modulation of logically combined with the timing and modulator sig
the modulator signal under the control of the current nals to form the channel A and B control signals. As
error signal, with relatively narrow pulses signifying a shown in FIG. 7, the soft start circuit 30 includes two
power signal current in excess of that desired and rela NPN transistors 340 and 342, a capacitor 344, a diode
tively wide pulses signifying a power signal current that 346, a bias network 348 for the transistors, and an output
is less than desired. As explained below, the relatively node 350 where the soft start control signal is formed.
narrow pulses of the modulator signal cause the power The transistor 340 has its base coupled to common
transistors of the bridge inverter to switch on for a through a resistor 352 and coupled to the positive DC
relatively shorter period of time within each cycle to voltage at node 56 through a zener diode 354 and resis
decrease the current of the power signal, while the 10 tor 356. The emitters of both transistors 340 and 342 are
relatively wide pulses of the modulator signal cause the connected to common. The collector of transistor 340 is
power transistors to switch on for a relatively longer connected to the base of transistor 342 and is coupled to
period of time within each cycle to increase the current node 56through resistor 358. The collector of transistor
of the power signal. 342 is coupled through a resistor 360 to node 56, is
The modulator signal and the timing signal are logi 15 coupled through diode 346 to the control terminal of
cally combined by a two channel logic circuit 311, and the timer 282, is coupled through capacitor 344 to com
the resultant control signals are amplified and supplied mon, and is connected to the node 350. The soft start
to the modulating transistors to control the on time of control signal is supplied through node 350 to input
the power transistors of the bridge inverter 16. As terminals of the two AND gates 312, where it is logi
shown in FIG. 8, the timing signal at node 222 and the 20 cally combined with the timing and modulator signals.
inverse timing signal at node 224 are applied to two When the generator is first powered up, the voltage
input terminals of two separate quad-input AND gates at node 56 is at common potential. As the voltage at
312. The modulator signal at node 296 is coupled node 56 starts rising, transistor 340 is switched off due
through a shaping network 314 to input terminals of the to its connection to common through resistor 352, and
two AND gates 312. The shaping network consists of 25 transistor 342 is switched on due to its connection to
series resistors 315 and 316 in parallel with a diode 318. node 56through resistor 358. With transistor 342 on, the
The common connection between the resistors 315 and capacitor 344 remains discharged and the soft start
316 is coupled to common through a capacitor 320. The control signal at node 350 is at common potential,
output terminals of the two AND gates 312 are coupled which causes the channel A and B control signals to be
through separate inverters 322 and two stages 324 and 30 at the logic low voltage, which in turn causes the power
326 of amplification to nodes 150 and 204. Networks transistors of the bridge inverter to remain switched off.
328,330, and 332 provide biasing for the transistors of At some intermediate voltage, the breakdown volt
the amplification stages 324 and 326. age of the zener diode 354 is exceeded and transistor 340
The resultant signals at nodes 150 and 204 are sup switches on, causing transistor 342 to switch off. The
plied to the modulating transistors 86 and 82 through 35 capacitor 344 can now begin charging through the resis
nodes 150 and 204, respectively. As shown in FIG. 10, tor 360. During this time, the voltage applied to the
the signal at node 150 is denoted the channel A control control terminal of the timer 282 is pulled down
signal, while the signal at node 204 is denoted the chan through diode 346 to a voltage near the voltage on the
nel B control signal. The channel A control signal is the capacitor 344. Recall that the voltage applied to the
logical AND of the modulator signal and the timing control terminal of the timer 282 controls the pulse
signal, while the channel B control signal is the logical width of the modulating signal. As the capacitor 344
AND of the modulator signal and the inverse timing charges, the pulse width of the modulating signal gradu
signal. Thus, the timing signals determine the alternate ally increases, thus providing a gradual application of
phase relationship of the control signals, while the mod power to the transformer 18 and ultrasonic transducer
ulator signal determines the width of the pulses. The 45 20. Waveforms of the soft start control signal, the mod
waveform of the power signal is defined by the control ulator signal, and the resultant power signal during this
signals. The power transistor pair 58-64 switches on for powerup phase are shown in FIG. 10.
each positive pulse of the channel A control signal to Another factor that influences the on-time of the
drive the transformer 18 in one direction. At the falling power transistors of the bridge inverter is the action of
edge of the channel A control signal pulse, the transis 50 the duty cycle controller 32, which provides a degas
tor pair 58-64 switches off and the voltage of the power sing modulation. The duty cycle controller 32 generates
signal decays to a floating neutral. At the next rising a duty cycle control signal at node 370, which signal is
edge of the channel B control signal, the other power supplied to input terminals of the AND gates 312 for
transistor pair 60-62 switches on to drive the trans logically combining with the timing, modulation, and
former 18 in the opposite direction. At the falling edge 55 soft start control signals. The duty cycle control signal
of the channel B control signal pulse, the transistor pair defines how long during each cycle of the power supply
60-62 switches off and the voltage of the power signal (120 Hz in the illustrated preferred embodiment) the
decays back to the floating neutral. The amount of time power signal is generated. As shown in FIG. 9, the duty
that the transistor pairs are on is determined by the cycle controller 32 includes a 555 type timer 372 having
width of the control signal pulses, which are in turn its power input terminal connected to node 56, its
determined by the width of the modulator signal pulses. ground terminal connected to common, its trigger and
In addition to the timing and modulator signals, the reset terminals coupled to common through parallel
channel A and B control signals reflect two additional connected resistor 374 and capacitor 376 and coupled to
factors that influence the on time of the power transis node 46 through series connected zener diode 378 and
tors of the bridge inverter. One such factor is the desire 65 resistor 380, its control terminal coupled to common
to ramp upgradually the application of power when the through capacitor 382, and its threshold and discharge
generator is first powered up. For this purpose, the soft terminals coupled to common through a timing capaci
start circuit 30 generates a soft start signal that is also tor 384 and coupled to node 56 through series con
 4,864,547 14
13
nected resistors 386 and 388. In addition, an NPN tran pair of power transistors generates one component
sistor 390 has its base connected to common, its emitter of said power signal;
coupled to the negative voltage portion of the DC timing means for generating a timing signal equal in
power supply 52 through resistor 392 and node 394 and frequency to the desired frequency of said power
to node 46 through resistor 396, and its collector con 5 signal;
nected to node 46. The transistor 390 provides a bypass bridge driving means responsive to said timing signal
circuit for the voltage applied to node 46. A clamping for periodically generating base drive signals that
diode 398 is inserted between node 56 and the common when supplied to the bases of said power transis
connection between Zener diode 378 and resistor 380 tors cause said power transistors to switch on,
and a decoupling capacitor 400 is coupled between O wherein said bridge driving means alternately gen
node 56 and common. erates said base drive signals at the desired fre
The timing sequence begins when the rectified power quency for switching on alternate pairs of said
at node 46 sets up a voltage on the zener diode 378 that power transistors;
exceeds its threshold, which sends a high voltage to the bridge modulating means coupled between said
trigger and reset terminals of the timer 372. The timer 15 bridge driving means and said bridge inverter
then begins to charge the timing capacitor 384 with means for selectively connecting said base drive
current drawn through resistors 386 and 388. The signals to and disconnecting said base drive signals
charging rate of the capacitor 384 is adjusted by chang form the bases of said power transistors, said bridge
ing the resistance of the adjustable resistor 388. During 20 modulating means including four modulating tran
this time, the output signal of the timer, which is the sistors each coupled between said bridge driving
duty cycle control signal, is at its logic high voltage. means and a base terminal of one of said power
When the timer times out, the output signal of the timer transistors and operable for supplying a base drive
signal to its coupled power transistor, said bridge
372 goes to its logic low voltage and remains low until modulating means including means responsive to
the next power supply cycle. As shown in FIG. 10, 25 the power of said power signal for regulating the
while the duty cycle control signal is high, the control amount of time during each cycle of said power
signals are generated, which in turn cause the power signal that said power transistors are on by switch
transistors to generate the power signal. When the duty ing on and off said modulating transistors; and
cycle control signal fall to low, however, the control means for supplying said power signal to the ultra
signals also drop to low and stay there during the re 30 sonic transducer.
mainder of the power supply cycle. The utility of such 2. An apparatus as recited in claim 1 wherein said
a dwell time is that degassing can occur during each timing means includes a first timer running at a fre
power supply cycle, with the duration of the dwell time quency equal to twice the desired frequency, and in
adjustable by the operator. cludes a D-type flip-flop that receives the output signal
By separating the control functions from the power 35 of said first timer as a clock input signal thereto, and
generation functions, the generator 10 of the present wherein said flip-flop generates said timing signal at the
invention provides a regulated and stable power signal desired frequency and also generates an inverse timing
for driving the ultrasonic transducer 20. Short circuit signal equal to the logical inverse of said timing signal.
protection is provided by the power controller 28 and 3. An apparatus as recited in claim 2 wherein said first
modulator 26 by modulating the power signal when the timer includes means for adjusting the frequency of
current exceeds a desired amount. Open circuit protec operation of said first timer so as to adjust the frequency
tion is provided by separation of the bridge driver cir of said timing signal.
cuitry from that of the power control circuitry. 4. An apparatus as recited in claim 1 wherein said
From the above description, it will be apparent that bridge driving means includes a capacitor, a bridge
the invention disclosed herein provides a novel and 45 driving transformer, and first and second bridge driving
advantageous regulated ultrasonic generator operable transistors, wherein said capacitor is continuously
for supplying a driving signal to an ultrasonic trans charged by said power supply, wherein said first and
ducer. The foregoing discussion discloses and describes second bridge driving transistors and circuitry associ
merely exemplary methods and embodiments of the ated therewith in response to said timing signal alter
present invention. As will be understood by those famil 50 nately connect a first terminal of the primary windings
iar with the art, the invention may be embodied in other of said bridge driving transformer to opposite terminals
specific forms without departing from the spirit or es of said capacitor, wherein said bridge driving means
sential characteristics thereof. For example, the genera further includes means for coupling a second terminal
tor can be used for driving ultrasonic devices other than of said primary windings of said bridge driving trans
transducers used in ultrasonic cleaning. Accordingly, 55 former to a potential intermediate to the potentials alter
the disclosure of the present invention is intended to be nately applied to said first terminal of said primary
illustrative, but not limiting, of the scope of the inven windings through said bridge driving transistors, and
tion, which is set forth in the following claims. wherein said base drive signals are generated by second
We claim: ary windings of said bridge driving transformer.
1. An apparatus for generating a driving signal for 60 5. An apparatus as recited in claim 4 wherein said
powering an ultrasonic transducer, said apparatus com bridge driving transformer includes four secondary
prising: windings, each generating a base drive signal for con
a power supply; nection to an individual power transistor of said bridge
bridge inverter means powered by said power supply inverter means.
for generating a power signal having two alternat 65 6. An apparatus as recited in claim 5 wherein all of
ing components of opposite potential, wherein said said power transistors are bipolar transistors of like
bridge inverter means includes four power transis polarity, wherein the two base drive signals generated
tors configured in two pairs thereof, wherein each to drive one pair of power transistors are the opposite
 4,864,547 16
15
polarity as the other two base drive signals generated to 15. An apparatus as recited in claim 14 wherein one of
drive the other pair of power transistors, and wherein said channels of logic circuitry includes a first AND
the polarities of said base drive signals alternate accord gate that logically combines said timing signal and said
ing to the frequency of said timing signal. modulator signal to generate a first modulating transis
7. An apparatus as recited in claim 4 wherein said tor control signal, and wherein the other one of said
bridge driving transistors are coupled in a complemen channels of logic circuitry includes a second AND gate
tary manner such that each bridge driving transistor is that logically combines said modulator signal with the
switched off when the other bridge driving transistor is inverse of said timing signal to generate a second modu
switched on. lating transistor control signal.
8. An apparatus as recited in claim 7 wherein said 10 16. An apparatus as recited in claim 13 wherein said
timing signal is coupled to the base of one of said bridge bridge modulating means further includes current sens
driving transistors for switching said bridge driving ing means for sensing the current of said power signal,
transistors o and off. includes current reference means for indicating a de
9. An apparatus as recited in claim 1 wherein said sired current of said power signal, includes comparison
means for generating a current error signal indicative of
bridge modulating means includes four modulating 15 the relative difference between the sensed current of
transistors each connected in series between the base of
a corresponding one of said power transistors and said includessaid power signal and the desired current thereof, and
bridge driving means, wherein each of said modulating said current pulse width modulation means responsive to
transistors is operable for selectively connecting a cor 20 signal. error signal for generating said modulator
responding base drive signal to and disconnecting the 17. An apparatus as recited in claim 16 wherein said
base drive signal from the base of said corresponding current sensing means includes a current sensing resis
power transistor, and wherein said bridge modulating tor through
means also includes modulating transistor switching voltage dropwhich said power signal flows, wherein the
across said current sensing resistor indi
means for switching said modulating transistors on and 25 cates the current of said power signal.
off. 18. An apparatus as recited in claim 17 wherein said
10. An apparatus as recited in claim 9 wherein said current reference means includes a voltage divider cou
four modulating transistors are grouped into two pairs pled between one side of said current sensing resistor
thereof, with each pair of modulating transistors being and a reference voltage, wherein said comparison
coupled to a corresponding one of said pairs of power 30 means includes a voltage comparator coupled at a first
transistors. input terminal thereof to an intermediate voltage tap on
11. An apparatus as recited in claim 10 wherein said said voltage divider and coupled at a second input ter
bridge modulating means further includes coupling minal thereof to the other side of said current sensing
means for coupling together the control terminals of resistor, and wherein said voltage comparator generates
each pair of modulating transistors, and wherein a con 35 said current error signal according to the voltage differ
trolled transistor of each pair of modulating transistors ence between the signals applied to the input terminals
is directly switched by said modulating transistor of said voltage comparator.
switching means and a follower transistor of said pair of 19. An apparatus as recited in claim 18 wherein the
modulating transistors is indirectly switched through voltage difference between the signals applied to the
said coupling means. 40 input terminals of said voltage comparator is zero when
12. An apparatus as recited in claim 11 wherein said the desired current is flowing across said current sens
coupling means includes two coupling transformers ing resistor.
with each of said coupling transformers coupling to 20. An apparatus as recited in claim 16 wherein said
gether the control terminals of a pair of modulating pulse width modulation means includes a second timer
transistors so that a control signal applied to the control 45 triggered at a rate determined by said timing signal,
terminal of a controlled transistor is coupled through wherein a modulation input terminal of said second
said coupling transformer and also applied to the con timer receives said current error signal and an output
trol terminal of the associated follower transistor to terminal of said second timer generates said modulator
switch on or off both transistors of said pair of modulat signal, wherein the pulse width of said modulator signal
ing transistors. 50 is determined by the magnitude of said current error
13. An apparatus as recited in claim 10 wherein said signal.
modulating transistor switching means includes logic 21. An apparatus as recited in claim 16 further com
means for combining said timing signal with a modula prising soft-start means for gradually increasing the
tor signal to generate modulating transistor control pulse width of said modulator signal during an initial
signals that control the switching of said modulating 55 power-up of said apparatus.
transistors, wherein said modulator signal defines the 22. An apparatus as recited in claim 21 wherein said
amount of time during each cycle of said power signal soft-start means includes a soft-start capacitor that is
that said power transistors are to be switched on in initially discharged and which gradually charges during
order to obtain a desired output power from said power the initial power-up of said apparatus, and wherein the
signal. voltage of said current error signal supplied to said
14. An apparatus as recited in claim 13 wherein each pulse width modulation means is limited by the charge
of said modulating transistor control signals controls on said soft-start capacitor during the initial power-up
the switching of one of said pairs of modulating transis of said apparatus.
tors, and wherein said logic means includes two chan 23. An apparatus as recited in claim 21 wherein said
nels of logic circuitry each channel operable for logi 65 logic means is responsive to a cut-off signal for generat
cally combining said timing signal with said modulator ing said modulating transistor control signals for
signal to generate one of said modulating transistor Switching off said modulating transistors, and wherein
control signals. said soft-start means includes means for generating said
 4,864,547 18
17
cut-off signal at the beginning of the initial power-up of wherein said bridge driving means alternately gen
said apparatus. erates said base drive signals at the desired fre
24. An apparatus as recited in claim 13 wherein said quency for switching on alternate pairs of said
logic means is responsive to a cut-off signal for generat power transistors, wherein said bridge driving
ing said modulating transistor control signals for 5 means includes a bridge driving transformer and
switching off said modulating transistors, and wherein means for supplying an alternating current to said
said apparatus further comprises a duty cycle controller bridge driving transformer, wherein said alternat
for periodically generating said cut-off signal to control ing current is equal in frequency to said timing
the duty cycle of said apparatus. signal, and wherein said base drive signals are gen
25. An apparatus as recited in claim 24 wherein said 10 erated by secondary windings of said bridge driv
power supply supplies cyclic power to said bridge in ing transformer;
verter means at a frequency less than the desired fre bridge modulating means coupled between said
quency of said power signal, and wherein said duty bridge driving means and said bridge inverter
cycle controller includes a duty cycle timer that begins means for selectively connecting said base drive
timing at the start of each power supply cycle and gen 15 signals to and disconnecting said base drive signals
erates said cut-off signal after a selectable time after the from the bases of said power transistors, wherein
start of the power supply cycle but before the end of the said bridge modulating means includes four modu
power supply cycle. lating transistors and means for switching said
26. An apparatus as recited in claim 1 wherein said modulating transistors on and off, wherein each of
means for supplying said power signal to the ultrasonic 20 said modulating transistors is connected in series
transducer includes an output power transformer cou between the base of a corresponding one of said
pled to said bridge inverter means for converting said power transistors and one of said secondary wind
power signal into the driving signal for transmission to ings of said bridge driving transformer, wherein
the ultrasonic transducer. said means for switching said modulating transis
27. An apparatus as recited in claim 26 wherein said 25
tors includes logic means for combining said timing
output power transformer has some inductance that acts signal with a modulator signal to control the
to round off the sharp corners of said power signal so switching of said modulating transistors, wherein
that the waveshape of the driving signal is similar to a said modulator signal defines the amount of time
sine wave. during each cycle of said power signal that said
28. An apparatus for generating a driving signal for 30 power transistors are to be switched on in order to
powering an ultrasonic transducer, said apparatus com obtain a desired current of said power signal,
prising: wherein said bridge modulating means further in
a power supply; cludes means for generating said modulator signal
bridge inverter means powered by said power supply including current sensing means for sensing the
for generating a power signal having two alternat 35 current of said power signal, comparison means for
ing components of opposite potential, wherein said generating a current error signal indicative of the
bridge inverter means includes four power transis relative difference between the sensed current of
tors configured in two pairs thereof, wherein each said power signal and the desired current thereof,
pair of power transistors generates one component
of said power signal; and pulse width modulation means responsive to
timing means for generating a timing signal equal in said current error signal for generating said modu
frequency to the desired frequency of said power lator signal; and
signal; an output power transformer coupled to said bridge
bridge driving means responsive to said timing signal inverter means for converting said power signal
for periodically generating base drive signals that 45 into the driving signal for transmission to the ultra
when supplied to the bases of said power transis sonic transducer.
: s ck ck ck
tors cause said power transistors to switch on,

50

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