Research on High Power Density SiC Mosfet Driver

Circuit

Shaokun Zhang1, 2, Guolin He1, 2, Dan Zheng 1, 2, *Tao Fan1, 3, Xuhui Wen1, 2
1
Institute of Electrical Engineering of Chinese Academy of Sciences, Beijing, P.R. China
2
Key Laboratory of Power Electronics and Electric Drive, Institute of Electrical Engineering, Chinese Academy of Sciences
3
Collaborative Innovation Center of Electric Vehicles in Beijing
E-mail: fantao@mail.iee.ac.cn

Abstract—Compared with silicon (Si) power devices, silicon fault feedback, active Miller Clamp, overcurrent protection
carbide (SiC) power devices have higher doping and other functions. However, its driving ability is small,
concentrations, wider band gaps, and lower on-state only 2A, so the power amplifier chip IXDN609 is connected
impedance at high voltages, so they can be used to increase to the rear stage.
switching frequency in high-power applications. Reduce the
volumetric weight of the converter and increase the power SiC MOSFETs have higher requirements on the driving
density. According to the switching characteristics of SiC voltage and driving speed. The turn-on voltage is only 2.7V,
MOSFET, a driving circuit of SiC MOSFET is designed. The and it decreases with the increase of temperature, but it can
paper focuses on how the commercial driver chip can better be fully turned on only when the driving voltage reaches
use the supersaturation detection circuit on SiC MOSFET and 18~20V. In this paper, the turn-on voltage is 20V and the
perform double pulse experiment on 1200V/300A SiC module. turn-off voltage is -5V. Considering the height and volume
The switching time, switching loss and crosstalk of the upper of the isolated driver power supply design, this paper uses
and lower tubes were measured experimentally. The effects of the AUIRS2003S chip and its peripheral circuits to convert
different resistance driving resistors on the switching behavior the DC voltage into an AC voltage input to the pulse
of SiC MOSFET modules were analyzed. In addition, a high- transformer. The topology of the power circuit is shown in
power test was conducted on a controller with a peak power of Figure 1.
81 kW, and the reliability and anti-interference of the drive
circuit were fully tested and verified.

Keywords—SiC mosfet, driver protection circuit,

1ED020I12_F2

I. INTRODUCTION
In view of the driving requirements of the integrated SiC
mosfet module, a small volume SiC mosfet drive protection
circuit is designed by 1ED020I12_F2 with the aim of high
power density. The drive circuit integrates anti-through Fig.1. Power circuit
protection circuit, voltage sampling circuit and driver circuit. In order to prevent the bridge arm from passing straight
In addition to meeting the basic driving requirements of SiC through, the bridge arm interlock function is specially added
MOSFETs, a desaturation detection circuit that is more at the input end of the driving chip, that is, when the input
suitable for overcurrent protection of SiC MOSFETs is and output levels of the upper and lower tubes are both high,
considered. the output of the driving chip is low until the upper and
lower tubes are not all high. The driver chip output is
II. TECHNICAL WORK PREPARATION normal. The power supply and bridge arm interlock circuit
A. Driving Circuit are shown in Fig.2.
Due to the high operating frequency and input
impedance of the MOSFET, it is easy to be disturbed.
Therefore, the driver circuit should have good electrical
isolation performance to achieve isolation between the main
circuit and the control circuit. When selecting a driver
circuit, this article only considers the isolation driver circuit.
Isolation drives can be divided into electromagnetic
isolation and optical isolation. The use of pulse transformer
to achieve electromagnetic isolation of the circuit is a circuit
that is simple and reliable, and has electrical isolation. Fig.2 Bridge arm interlock circuit
In addition, some unique features have been carefully
This article uses a commercial driver chip 1ED020I12- considered in the design of the desaturation detection
F2 with no core transformer technology, which integrates circuit, such as faster fault response time, stronger noise
many functions, such as detecting undervoltage lockout, immunity, and avoiding false triggering. The schematic
differential input, rail-to-rail output, isolated open collector diagram of the driver circuit designed according to the

978-1-7281-3398-0/19/$31.00 ©2019 IEEE

above analysis principle is shown in Fig. 3. In order to avoid
the influence of the Miller current on the gate when the
MOSFET is switched at a high speed, a gate active clamp
circuit with a negative voltage turn-off is added here. In
addition, the short-circuit clamp is added. When a short
circuit occurs, the dVDS/dt caused by the short-circuit will
pull up the gate voltage of the MOSFET through the reverse
transfer capacitor, and the diode D5 can effectively clamp
the MOSFET gate to VCC2_R to limit the short circuit
current.
Fig.4. Desaturation detection circuit

Due to the nature of SiC MOSFETs, during the blanking

time, the fault current can proliferate to very high values, so
the resulting thermal effects can degrade device
performance or damage the device.
Here, the appropriate blanking time is selected by the
switching characteristics of the device measured by the
double pulse experiment. The blanking time is determined
by the time constant of the high-precision current source
inside the driver chip, the threshold voltage Vdesat_th, and
Fig.3. Driver circuit
the R-C circuit τ:
B. Desaturation detection technique
VCC 2 _ R + I ⋅ ( R1 + R2 )
The desaturation protection circuit implemented in this tblk = τ ln ,
design is shown in Fig.4. The drive chip DESAT pin is an VCC 2 _ R + I ⋅ ( R1 + R2 ) − Vdesat _ th
anti-supersaturation input pin. The internal circuit consists of
τ = ( R1 + R2 ) ⋅ C10
a 500uA constant current source and a comparator with a
threshold of 9V. The external circuit consists of D2, D3, R1, Where I is 50uA and Vdesat_th is 9V.
R2, C0, and D6. The drain-source voltage of the MOSFET is
monitored by Zener diode D3, diode D2, and R-C network Due to the nature of the SiC MOSFET, the resulting
(R1, R2, and C10). When selecting the values of R1 and R2, thermal effects may degrade device performance or damage
the Miller effect capacitor on the Zener diode D3 and the the device. Therefore, the fast response time of overcurrent
diode D2 should be minimized and a large amount of current protection is the first consideration. However, during the fast
is not drawn from the power supply VCC2_R. The power switching of SiC MOSFET, the noise resistance is a big
supply VCC2_R and the resistor R2 are equivalent to problem through the late high-power experiment. If it is not
increasing the current based on the 500uA constant current properly optimized, it is turned on. During the turn-off
source, which helps to improve the anti-interference ability switching transient, high dVDS /dt may falsely trigger the
of the entire circuit. When the MOSFET is "on" and desaturation protection circuit, and frequent mis-protection
saturated, D2 will pull the voltage on C10 low, eventually may cause the experiment to fail. This is because the diode
the voltage of Zener diode D3, which will not reach the D2 and the Zener diode D3 have parasitic junction
threshold voltage of the internal comparator of the chip by capacitance. During the fast switching of the MOSFET, the
9V. Under overcurrent conditions, the MOSFET will exit large dVDS /dt will generate a displacement current on the
saturation, driving the constant current source inside the chip junction capacitance, which will also flow through the
and the VCC2_R supply will charge C10 and flip the blanking capacitor C10 and the loop. The parasitic
comparator inside the driver chip. inductance on the above will form a resonant loop, which
will oscillate at a certain frequency to affect the value of the
Adjusting the withstand voltage of the resistor R1 and the inverting input voltage of the internal comparator Vdesat, as
diode D2 in the desaturation detection circuit and the voltage shown in Fig. 4.
regulation value of the Zener diode D3 can adjust the
protection threshold, and adjust the protection speed by After analysis, false triggering can be suppressed by: (1)
adjusting the capacitance. If the overcurrent protection point SiC diode D2 with small series junction capacitance and
is represented by VDS_sat, there is: Zener diode D3 to minimize displacement current; (2) series
decoupling small resistor R1 (R1<<R2) increases Damping
VDS _ sat = Vdesat _ th − I ⋅ R1 − VD 2 − VD 3 of the oscillating circuit limits the switching noise coupled
between the diode and the Zener diode during DESAT
In equation, Vdesat_th is the comparison threshold detection; (3) In the PCB layout, R1, R2 and C10 should be
voltage of the internal comparator of the chip, the value is placed as close as possible to the DESAT pin of the driver
9V, I is the constant current source inside the chip, the value chip, and the parasitics should be minimized during wiring.
is 50uA, the resistance of R1 is 510Ω, and VD2 is the Capacitance to avoid interference between the high-side and
voltage across the diode, the value is 0.48V. VD3 is the low-side loops due to the presence of parasitic capacitance
voltage across the voltage regulator D3 and is adjusted coupling dv/dt.
according to the protection value. C. Current sampling circuit
In the current sampling circuit, the signal is first divided
by a resistor, which is suitable for the range of sample
values, and followed by the second-order filter circuit. Pay special attention to the bridge crosstalk problem to
Adjusting the resistance and capacitance values of the prevent damage to the power device. A drive-circuit design
second-order filter circuit can achieve different signal cutoff uses a gate-active clamp circuit with a negative-voltage shut
frequencies. The current samping circuit is show in Fig.5. down to prevent crosstalk.
The driver board was tested for crosstalk on a
1200V/300A full SiC module with a drive resistance of 10Ω,
a bus voltage of 600V, an on-time of 22us+10us+3us, and a
switching current of 300A. The crosstalk of the first
MOSFET of the full SiC module to the upper MOSFET is
measured instantaneously. During the test, the Rogowski coil
is clamped to the source of the lower MOSFET, and the
Fig.5. Schematic diagram of the current sampling circuit
differential probe is sandwiched between the DS, GS of the
lower MOSFET and the GS of the upper tube. Test wiring
III. EXPERIMENT AND ANALYSIS and test point locations such as Fig.8.
A Desaturation circuit test The crosstalk test waveform is shown in Fig.9. The
The 1ED020I12-F2 chip has a desaturation detection maximum gate voltage of the full SiC MOSFET module is -
function. If the drive output OUT is high, VDS is higher than 10V/+25V, and the forward turn-on threshold voltage
the defined value and the blanking time has expired, the VGS(th) is 2.4V. According to the test waveform, when the
desaturation protection is activated and the MOSFET is bus voltage is 600V and the switching current is 300A, the
turned off. When the DESD pin voltage of the driver chip forward voltage of the lower tube is 5.05V, which is
rises and reaches 9 V, the output is driven low. On the dual equivalent to a 5.05V superimposed on the off-voltage of the
pulse test bench, separate the drive board from the module upper tube. The upper gate voltage spike reaches 0.05V, and
and measure the blanking time of the saturation circuit. The the forward threshold voltage of the MOSFET module is not
experimental bench is shown in Figure 6. The experimental reached at 2.4V. The upper and lower tubes do not
waveforms are shown in Figure 7. It can be seen from the instantaneously pass through. The negative voltage spike of
test waveform that the blanking time is about 2 us, which is the lower tube switch to the off upper tube is 2V, which is
basically consistent with the theoretical value considering the equivalent to a -2V superimposed on the off-voltage of the
influence of parasitic parameters and capacitance bias upper tube -5V, and the upper gate voltage spike reaches -
characteristics. 7V, and the maximum of the module The gate voltage is -
10V, which is unlikely to cause breakdown of the gate
source and damage to the switch.

Fig.6 Double pulse test bench

Fig.8 Crosstalk test connection diagram

Fig.7 Blanking time test

B. Crosstalk test
Since the upper and lower tubes of the bridge arm circuit
are complementarily turned on and there is dead time, the
faster switching speed of the switch affects the
complementary driving waveform, and the SiC gate voltage
Fig.9. Crosstalk test waveform
safety threshold range is small and easy to be misdirected, so
C. Double pulse test CH1:VGS(20V/div)
The driver board performs a full double pulse test on a
self-packaged 1200V/300A three-phase full-bridge SiC
MOSFET module. The drive resistance is 10Ω, the bus
voltage is 600V, and the on-time is 22us+10us+. 3us,
CH3:ID(100A/div)
switching current 300A. The double-pulse test connection is
the same as the crosstalk test, except that the gate signal of
the disturbed tube is no longer detected.
The overall waveform of the double pulse test is shown
in Fig.10,where CH1 is the driving UGS voltage signal, CH2 CH2:VDS(200V/div)
is the MOSFET tube UDS voltage, and CH3 is the Rogowski
coil measuring the measured tube ID current. The turn-on
loss measurement waveform is shown in Fig.11. The turn-off
loss test waveform is shown in Fig.12.The current rise time
measurement waveform is shown in Fig.13. The current fall
time measurement waveform is shown in Fig.14. It can be Fig.12. 600V/300A turn-off loss measurement(8.75mJ)
seen from the experimental waveform that the driver board
can drive 1200V/300A SiC module well under the voltage
and current levels of 600V and 300A. The designed driving
circuit works well and meets the design requirements of the
driving circuit. The experimental data is shown in Table 1.
The turn-on loss is 8.43 mJ and the turn-off loss is 8.75 mJ.
The rise time is 84ns and the fall time is 107ns.
Tab.1 double pulse test data under 600V/300A operating
conditions
Udc/V Ic/A Eon/mJ Eoff/mJ tr/ns
600 300 8.43 8.75 84
Udc/V Ic/A td(on)/ns tf/ns td(off)/ns
600 300 118 107 436

Fig.13. Current rise time measurement(84ns)

Fig.10. 600V/300A double pulse test overall waveform

CH1:VGS(20V/div)

Fig.14. Current fall time measurement(107ns)

CH2:VDS(200V/div) In addition, the switching waveforms of the current and

voltage under the bus voltage of 300V, ID current 200A,
10Ω and 15Ω are compared in the double pulse experiment.
See Table 2 for experimental data. See Fig.15 for the
comparison of the losses of the different resistors. See Fig.16
CH3:ID(100A/div) for a comparison of switching times for different resistors.
As can be seen from Fig.17 to Fig.20, as the gate resistance
increases, the rise and fall times of the voltage and current of
the device become longer, thereby increasing the overlapping
area of the drain-source voltage and the drain current, and
Fig.11. 600V/300A turn-on loss measurement(8.43mJ) thus the loss becomes larger, but with The increase in RG,
the current overshoot at turn-on, and the voltage overshoot at
turn-off, the current slope di/dt is significantly reduced.
Tab.2 Double pulse test data under different drive resistances
of 300V/200A
Rg=15Ω Rg=10Ω
Udc/V ID/A Eon/mJ Eoff/mJ Eon/mJ Eoff/mJ

300 100 2.3 2.14 1.5 1.6

300 200 4.3 5.4 2.72 4

300 300 5.6 8 3.88 6

Rg=15Ω Rg=10Ω

Udc/V ID/A tr/ns tf/ns tr/ns tf/ns

300 100 70 124.5 50 96

300 200 99 126 72 100

Fig.18 Current turn-off waveform comparison
300 300 123 130 94 122

Rg=15Ω Rg=10Ω

Udc/V ID/A td(on)/ns td(off)/ns td(on)/ns td(off)/ns

300 100 152 665.4 114 392

300 200 166 630 121 451

300 300 180 592 128.6 391

Fig.19 Voltage turn-on waveform comparison

Fig.15 Comparison of different drive resistance switching losses

Fig.16 Comparison of different drive resistance switching time Fig.20 Voltage turn-off waveform comparison

D. High power experiment verification

Fig.21 shows the PCB and physical map of the drive
board.

Fig.21. Driver board PCB map and physical map

Fig.17 Current turn-on waveform comparison

 In order to verify the reliability and stability of the drive
circuit in high-power experiments, a high-power test was
conducted on a full SiC controller with a power density of
37.1 kW/L. The controller measures 158mm in length,
148mm in width, 98mm in height, 2.29L in volume and
4.5kg in weight. The controller has a rated voltage of
600VDC, a maximum current peak of 240A on the AC side,
and an output peak power of 81kW. The permanent magnet
synchronous motor is matched with the controller, the model
is EMRAX 268, the performance index is
125A/80kW/4500rpm, the internal resistance is 26mΩ, the d-
axis inductance is 0.35mH, the q-axis inductance is 0.37mH,
and the pole pair is 10 pairs pole. The high-power
experimental environment is shown in Fig.22. The phase Fig.24. Phase current and line voltage waveform of 45kW
current and line voltage waveforms of the 45kW power
experiment are shown in Fig.23. The phase current and line IV. CONCLUSIONS
voltage waveforms of the 81kW power experiment are In this paper, a special driving circuit for SiC MOSFET is
shown in Fig.24. designed, and its overcurrent protection circuit is studied. It
is shown that the circuit is very effective for the protection of
SiC MOSFET module. Finally, a double-pulse experiment
was carried out and a high-power test was carried out on a
full SiC controller with a peak power of 81 kW. The
reliability and anti-interference of the drive circuit were
fully tested and verified. The result proves that the drive
circuit very effective
ACKNOWLEDGMENT
This work supported by Chinese National Key
Technologies R&D Program under Project
2016YFB0100600.
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Fig.23. Phase current and line voltage waveform of 81kW