Chapter no 5
MCQS
Any electronic holding place where data can be stored and retrieved later whenever
required is ____________
a) memory
b) drive
c) disk
d) circuit
2. Cache memory is the onboard storage.
a) True
b) False
3. Which of the following is the fastest means of memory access for CPU?
a) Registers
b) Cache
c) Main memory
d) Virtual Memory
4. The memory implemented using the semiconductor chips is _________
a) Cache
b) Main
c) Secondary
d) Registers
5. Size of the ________ memory mainly depends on the size of the address bus.
a) Main
b) Virtual
c) Secondary
d) Cache
6. Which of the following is independent of the address bus?
a) Secondary memory
b) Main memory
c) Onboard memory
d) Cache memory
7. ____________ storage is a system where a robotic arm will connect or disconnect
off-line mass storage media according to the computer operating system demands.
a) Secondary
b) Virtual
c) Tertiary
d) Magnetic
8. What is the location of the internal registers of CPU?
a) Internal
b) On-chip
c) External
d) Motherboard
9. MAR stands for ___________
a) Memory address register
b) Main address register
c) Main accessible register
d) Memory accessible register
10. If M denotes the number of memory locations and N denotes the word size, then
an expression that denotes the storage capacity is ______________
a) M*N
b) M+N
c) 2M+N
d) 2M-N
11. Is it possible to build a computer which uses only static RAM___
a) True
b) False
12. Cache be located on CPU chip or module_____
a) True
b) False
13.cache sit Between processor and virtual memory management unit____
a) True
b) False
14.Physical cache stores data using main memory physical addresses____
a) True
b) False
15.Logical cache (virtual cache) stores data using virtual addresses______
a) True
b) False
16.Three techniques can be used Mapping function____
a) True
b) False
17.Permits each main memory block to be loaded into any line of the cache___
a) True
b) False
18.The cache control logic interprets a memory address simply as a Tag and a Word
field___
a) True
b) False
19.Least Significant w bits identify unique word___
a) True
b) False
20.Most Significant s bits specify one memory block___
a) True
b) False
21.The MSBs are split into a cache line field r and a tag of s-r ____
a) True
b) False
22.0, m, 2m, 3m…2s-m is in m-1 cache line___
a) True
b) False
23.1,m+1, 2m+1…2s-m+1 is in 0 caches line___
a) True
b) False
24.2 bit tag stored with each 32 bit block of data___t
a) True
b) False
25.Cache is divided into a number of sets___t
a) True
b) False
26.Fetches instructions from____
a) True
b) False
27.Decodes instructions into RISC like micro-ops before L1 cache___
a) True
b) False
28.Performance improved by separating decoding from scheduling & pipelining___
a) True
b) False
29.L1 cache controlled by 2 bits in register CD = cache disable___
a) True
b) False
30.NW = not write__
a) True
b) False
True & False
Qno1) Is it possible to build a computer which uses only static RAM___
Qno2) Cache be located on CPU chip or module_____
Qno3)cache sit Between processor and virtual memory management unit____
Qno4)Physical cache stores data using main memory physical addresses____
Qno5)Logical cache (virtual cache) stores data using virtual addresses______
Qno6)Three techniques can be used Mapping function____
Qno7)Permits each main memory block to be loaded into any line of the cache___
Qno8)The cache control logic interprets a memory address simply as a Tag and a
Word field___
Qno9)Least Significant w bits identify unique word___
Qno10)Most Significant s bits specify one memory block___
Qno11)The MSBs are split into a cache line field r and a tag of s-r ____
Qno12)0, m, 2m, 3m…2s-m is in m-1 cache line___f
Qno13)1,m+1, 2m+1…2s-m+1 is in 0 caches line___f
Qno14)2 bit tag stored with each 32 bit block of data___t
Qno15)Cache is divided into a number of sets___t
Qno16)Fetches instructions from____
Qno17)Decodes instructions into RISC like micro-ops before L1 cache___
Qno18)Performance improved by separating decoding from scheduling &
pipelining___
Qno19)L1 cache controlled by 2 bits in register
CD = cache disable___
Qno20)NW = not write__
Shorts Question
Qno1)How much memory Capacity?
Qno2)How fast is memory?
Qno3)How much expensive?
Qno4)Write down the Memory Hierarchy List?
Qno5)How can you cache cache?
Qno6)Write down the list Elements of Cache Design?
Qno7)Where does cache sit?
Qno8) in Direct Mapping Address length is equal to?
Qno9) in Direct Mapping Number of addressable cache is equal to?
Qno10) in Direct Mapping Block size line size is equal to?
Qno11) in Direct Mapping Number of blocks in main memory is equal to?
Qno12) in Direct Mapping Number of lines in cache is equal to?
Qno13) in Direct Mapping Size of cache is equal to?
Qno14) in Direct Mapping Size of tag is equal to?
Qno15)Write down the Direct Mapping Cache Line Table?
Qno16) how is Cache divided?
Qno17) The block number in main memory is modulo?
Qno18) write Set Associative Mapping Address Structure?
Qno19) For two-way set associative, this is easily implemented?
Qno20)Write down the Pentium 4 Block Diagram?
