Rizal Technological University

Boni Ave, City of Mandaluyong

College of Engineering and Industrial Technology

Electronics Engineering 2
ECE32

CEIT-05-601P
(TF 04:30pm-6:00pm)

Professor:
Engr. Ricardo Nasuli

Submitted by:
Obiedo, Peale Norman G.

FIELD EFFECT TRANSISTOR

Introduction

Although it has brought about a revolution in the design of electronic equipment, the
bipolar (PNP/NPN) transistor still has one very undesirable characteristic. The low input
impedance associated with its base-emitter junction causes problems in matching
impedances between inter-stage amplifiers.

For years, scientists searched for a solution that would combine the high input
impedance of the vacuum tube with the many other advantages of the transistor. The
result of this research is the FIELD-EFFECT TRANSISTOR (FET). In contrast to the
bipolar transistor, which uses bias current between base and emitter to control
conductivity, the FET uses voltage to control an electrostatic field within the transistor.
Because the FET is voltage-controlled, much like a vacuum tube, it is sometimes called
the "solid-state vacuum tube."

As the figure shows, the JFET is a three-element device comparable to the other two. The
"gate" element of the JFET corresponds very closely in operation to the base of the
transistor and the grid of the vacuum tube. The "source" and "drain" elements of the JFET
correspond to the emitter and collector of the transistor and to the cathode and plate of
the vacuum tube.

- Comparison of JFET, transistor, and vacuum tube symbols.

FET AS AN AMPLIFIER
The weak signal is applied between gate and source and the amplified output is obtained
in drain-source circuit. The input circuit is always reversed biased. A small change in the
reverse bias on the gate produces a large change in drain current. The large variation in
drain current produces large output across the load RL and so FET acts as an amplifier.

Output Characteristics of FET

The curve drawn between ID and VDS of a FET at constant VGS is known as output or
static characteristic of FET.

Let us first consider the characteristic for VGS = 0 (the gate being shorted with source). 
When VDS = 0, there is no attracting potential at the drain and, therefore, ID = 0,
although the channel between the gates is fully open as VGS = 0. With the increase n
VDS, ID increases linearly up to knee point i.e. the FET behaves as an ordinary resistor till
knee point, at point A, is reached.

With the increase in ID, gate junctions are reversing biased due to ohmic voltage drop in
the semiconductor material of channel and as a result the channel region begins to
constrict. With the further increase in VDS, ID increases at reverse square law rate up to
point B, called the pinch-off point. The voltage corresponding to this point B is called the
pinch-off voltage and is denoted by VP. At this voltage the channel is more or less
blocked. The worth noting point is that pinch-off does not mean ID cut-off. Moreover the
channel is not completely closed and so ID does not reduce to zero. With the further
increase in VDS (beyond pinch-off voltage), the channel resistance increases in such a
way that ID practically remains constant up to point C. the region BC is called saturation
region or amplifier region. In this region the FET operates as a constant current
device. With constant increase of VDS corresponding to point C, called the avalanche
breakdown voltage VA, eventually breakdown across the gate junction takes place and
current ID shoots up to a high value.

   Fig. 5.73
  (a) (b)

Fig. 5.73 (b) shows a family of ID versus VDS curves for different values of VGS. It is seen,
from fig. 5.73 (b), that the ID-VDS curves drawn for different values of VGS are similar to
that one for VGS = 0 except the following points.

(i) ohmic region of portion reduces,

(ii) Maximum saturation drain current is smaller and

(iii) Avalanche breakdown occurs at progressively lower values of VDS because reverse

bias gate voltage adds to the drain voltage thereby increases the voltage effective across
the gate junctions.

2 Classifications of FET:
1.) Junction Field Effect Transistors, or JFET’s,

2) Metal Oxide Semiconductor Field Effect Transistors or MOSFET’s.

1. Junction Field Effect Transistor (JFET)

In JFETs a conducting channel is formed of n or p-type semiconductor (GaAs, Ge or Si).

Connections are made to each end of the channel, the Drain and Source.

Characteristics of JPET:

Input voltage signal is applied to the gate-source junction in a reverse biased mode,
resulting in high input impedance. Input signal varies the source-to-drain internal
resistance. Applications include high input impedance amplifier circuitry.

. - JFET structure.

2.) Metal Oxide Field Effect Transistors (MOSFETs)

Both JFETs and MOSFETs are conductivity modulated devices, utilizing only one type of
charge carrier. Thus they are called unipolar devices, unlike bipolar transistors, for which
both electrons and holes are crucial.

Unlike a JFET, where a conducting channels is formed by doping and its geometry
modulated by the applied voltages, the MOSFET changes the carrier concentration in the
channel.

Characteristics of MOSFETs

Similar to the JFET above except the input voltage is capacitive coupled to the transistor.
The device is easily fabricated, inexpensive, and has a low power drain, but is easily
damaged by static discharge. Computer chips utilize CMOS.

. - MOSFET structure.
In sum, a FET can OPERATE in three regimes:

1) Cut-off regime in which no channel exists (V gs < Vt for NMOS) and Id = 0 for any vDS.)

2) Ohmic or Triode regime in which the channel is formed and not pinched o
(Vgs > Vt and Vds ≤ Vgs Vt for NMOS) and FET behaves as a “voltage-controlled” resistor.

3) Active or Saturation regime in which the channel is pinched o

(Vgs ≤ Vt and Vds > Vgs Vt for NMOS) and Id does not change with Vds.)

The key to FET operation is the effective cross-sectional area of the channel, which can
be controlled by variations in the voltage applied to the gate. This is demonstrated in the
figures which follow.

Figure 3-47 shows how the JFET operates in a zero gate bias condition. Five volts are
applied across the JFET so that current flows through the bar from source to drain, as
indicated by the arrow. The gate terminal is tied to ground. This is a zero gate bias
condition. In this condition, a typical bar represents a resistance of about 500 ohms. A
milliammeter, connected in series with the drain lead and dc power, indicates the
amount of current flow. With a drain supply (VDD) of 5 volts, the milliammeter gives a
drain current (ID) reading of 10 milliamperes. The voltage and current subscript letters
(VDD, ID) used for an FET correspond to the elements of the FET just as they do for the
elements of transistors.

Figure 3-47. - JFET operation with zero gate bias.

In figure 3-48, a small reverse-bias voltage is applied to the gate of the JFET. A gate-
source voltage (VGG) of negative 1 volt applied to the P-type gate material causes the
junction between the P- and N-type materials to become reverse biased. Just as it did in
the varactor diode, a reverse-bias condition causes a "depletion region" to form around
the PN junction of the JFET. Because this region has a reduced number of current
carriers, the effect of reverse biasing is to reduce the effective cross-sectional area of the
"channel." This reduction in area increases the source-to-drain resistance of the device
and decreases current flow.
Figure 3-48. - JFET with reverse bias.

The application of a large enough negative voltage to the gate will cause the depletion
region to become so large that conduction of current through the bar stops altogether.
The voltage required to reduce drain current (ID) to zero is called "pinch-off" voltage and
is comparable to "cut-off" voltage in a vacuum tube. In figure 3-48, the negative 1 volt
applied, although not large enough to completely stop conduction, has caused the drain
current to decrease markedly (from 10 milliamperes under zero gate bias conditions to 5
milliamperes). Calculation shows that the 1-volt gate bias has also increased the
resistance of the JFET (from 500 Ω to 1 k Ω). In other words, a 1-volt change in gate
voltage has doubled the resistance of the device and cut current flow in half.

These measurements, however, show only that a JFET operates in a manner similar to a
bipolar transistor, even though the two are constructed differently. As stated before, the
main advantage of an FET is that its input impedance is significantly higher than that of a
bipolar transistor. The higher input impedance of the JFET under reverse gate bias
conditions can be seen by connecting a microammeter in series with the gate-source
voltage (VGG), as shown in figure 3-49.

Figure 3-49. - JFET input impedance.

With a VGG of 1 volt, the microammeter reads .5 microamps. Applying Ohm's law
(1V ¸ .5mA) illustrates that this very small amount of current flow results in a very high
input impedance (about 2 megohms). By contrast, a bipolar transistor in similar
circumstances would require higher current flow (e.g., .1 to -1 mA), resulting in a much
lower input impedance (about 1000 ohms or less). The higher input impedance of the
JFET is possible because of the way reverse-bias gate voltage affects the cross-sectional
area of the channel.

FET PARAMETERS
Like vacuum tubes, a FET has certain parameters which determine the performance of a
circuit. The main parameters of a FET when connected in common-source configuration
are as follows:

1. DC Drain Resistance is the static or ohmic resistance of the channel and is given by
RDS = VDS/ID.

2. AC Drain Resistance is the ratio of change in drain source voltage (ΔV DS) and change in
drain current (ΔID) at constant gate-source voltage VGS. It is also called the dynamic
resistance and denoted as rd.

3. Transconductance is the ratio of change in drain current (ΔID) to the change in gate-
source voltage (ΔVGS) at constant VDS. It corresponds to transconductance gm in a
vacuum tube and is denoted by gfs.

4. Amplification Factor is defined as the ratio of change in VDS to the change in VGS at
constant drain current and is denoted by µ
i.e.  = µ = ΔVDS / ΔVGS = ΔID/ ΔVGS = rd x gm

List of Differences between BJT and FET

  IMPEDENCE IS HIGH COMPARED THEN BJT.

 JFET IS VOLTAGE DRIVEN DEVICE WHILE AS BJT CURRENT DRIVEN DEVICE.

 IN JFET THERE ARE NO JUNCTIONS AS IN ORDINARY TRANSISTOR,

CONDUCTION IS THROUGH AN n-TYPE OR p-TYPE SEMICONDUCTOR
MATERIAL. FOR THIS REASON NOISE LEVEL IS VERY SMALL.

 BJT is a bipolar device involving both types of charge carriers, where as FET is a
unipolar device involving only one type of charge carrier. The main difference is
that bjt is current controller device and FET is voltage controller device.

 FET has high input impedance compared to BJT.

FET has low noise compared to BJT. 
FET has low power dissipation compared to BJT.

 FET has better temperature stability as compared to BJT. 

BJT is more temp sensitive than FET.

 BJT has better driving capability (fan-out) than FET

and BJT also has high speed switching compared to FET.

Advantages of FET

1) They are devices controlled by voltage with a very high input impedance (107 to
1012ohms).
2) FETs generate a lower noise level than the Bipolar Junction Transistor (BJT).
3) FETs are more stable than BJT with temperature
4) FETs are easier to manufacture than the BJT, because they require fewer steps to be
built and they allow more integrated devices in the same IC.
5) FETs behave like resistors controlled by voltage for small drain-source voltage values.
6) The high input impedance of FET allows them to withhold loads long enough to allow
its usage as storage elements.
7) Power FETs can disipate higher power and can switch very large currents.

Disadvantages of FET

1) FETs have a poor frequency response due to its high input capacitance.
2) FETs have a very poor linearity, and generally they are less linear than BJT.
3) FETs can be damaged due to the static electricity.