FQB60N03L

October 2002

FQB60N03L
N-Channel Logic Level PWM Optimized Power MOSFET
General Description Features
This device employs a new advanced MOSFET technology • Fast switching
and features low gate charge while maintaining low on-
resistance. • rDS(ON) = 0.010Ω (Typ), VGS = 10V

Optimized for switching applications, this device improves • rDS(ON) = 0.017Ω (Typ), VGS = 5V
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies. • Qg (Typ) = 13nC, VGS = 5V

Applications • Qgd (Typ) = 4.5nC

• DC/DC converters • CISS (Typ) = 1650pF

DRAIN D
(FLANGE)

GATE G
SOURCE

S
TO-263AB
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol Parameter Ratings Units
VDSS Drain to Source Voltage 30 V
VGS Gate to Source Voltage ±16 V
Drain Current
Continuous (TC = 25oC, VGS = 10V) 51 A
ID Continuous (TC = 100oC, VGS = 4.5V) 27 A
Continuous (TC = 25oC, VGS = 10V, RθJA = 43oC/W) 7 A
Pulsed Figure 4 A
Power dissipation 62 W
PD
Derate above 25oC 0.5 W/oC
o
TJ, TSTG Operating and Storage Temperature -55 to 150 C

Thermal Characteristics
o
RθJC Thermal Resistance Junction to Case TO-263 2 C/W
o
RθJA Thermal Resistance Junction to Ambient TO-263 62 C/W
RθJA Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 43 o
C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity
FQB60N03L FQB60N03L TO-263AB 330mm 24mm 800 units

©2002 Fairchild Semiconductor Corporation FQB60N03L Rev. B

 FQB60N03L
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V
VDS = 25V - - 1
IDSS Zero Gate Voltage Drain Current µA
VGS = 0V TC= 150oC - - 250
IGSS Gate to Source Leakage Current VGS = ±16V - - ±100 nA

On Characteristics
VGS(TH) Gate to Source Threshold Voltage V GS = VDS, ID = 250µA 1 - 3 V
ID = 51A, VGS = 10V - 0.010 0.0135
rDS(ON) Drain to Source On Resistance Ω
ID = 27A, VGS = 4.5V - 0.017 0.020

Dynamic Characteristics
CISS Input Capacitance - 1650 - pF
VDS = 15V, VGS = 0V,
COSS Output Capacitance - 800 - pF
f = 1MHz
CRSS Reverse Transfer Capacitance - 200 - pF
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V 25 52 nC
Qg(5) Total Gate Charge at 5V VGS = 0V to 5V V = 15V - 13 30 nC
DD
Qg(TH) Threshold Gate Charge VGS = 0V to 1V ID = 27A - 1.5 2.3 nC
Qgs Gate to Source Gate Charge Ig = 1.0mA - 4.3 - nC
Qgd Gate to Drain “Miller” Charge - 4.5 - nC

Switching Characteristics (VGS = 4.5V)

tON Turn-On Time - - 115 ns
td(ON) Turn-On Delay Time - 15 - ns
tr Rise Time VDD = 15V, ID = 12A - 60 - ns
td(OFF) Turn-Off Delay Time VGS = 5V, RGS = 11Ω - 25 - ns
tf Fall Time - 30 - ns
tOFF Turn-Off Time - - 83 ns

Switching Characteristics (VGS = 10V)

tON Turn-On Time - - 57 ns
td(ON) Turn-On Delay Time - 8 - ns
tr Rise Time VDD = 15V, ID = 12A - 30 - ns
td(OFF) Turn-Off Delay Time VGS = 10V, RGS = 11Ω - 45 - ns
tf Fall Time - 30 - ns
tOFF Turn-Off Time - - 115 ns

Unclamped Inductive Switching

tAV Avalanche Time ID = 2.9A, L = 3.0mH 195 - - µs

Drain-Source Diode Characteristics

ISD = 27A - - 1.5 V
V SD Source to Drain Diode Voltage
ISD = 20A - - 1.0 V
trr Reverse Recovery Time ISD= 27A, dISD/dt = 100A/µs - - 71 ns
QRR Reverse Recovered Charge ISD= 27A, dISD/dt = 100A/µs - - 104 nC

©2002 Fairchild Semiconductor Corporation FQB60N03L Rev. B

 FQB60N03L
Typical Characteristic TC = 25°C unless otherwise noted

1.2 60
VGS = 10V
POWER DISSIPATION MULTIPLIER

1.0 50

ID, DRAIN CURRENT (A)

0.8 40

0.6 30 VGS = 5V

0.4 20

0.2 10

0
0
0 25 50 75 100 125 150 25 50 75 100 125 150
TA , AMBIENT TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs

Ambient Temperature Case Temperature

2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
0.05
THERMAL IMPEDANCE

0.02
ZθJC, NORMALIZED

0.01
PDM
0.1

t1
t2
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t , RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

700
TRANSCONDUCTANCE TC = 25oC
MAY LIMIT CURRENT FOR TEMPERATURES
IN THIS REGION ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
IDM , PEAK CURRENT (A)

I = I25 150 - TC
125
VGS = 10V

100
VGS = 5V

40
10-5 10-4 10-3 10-2 10-1 100 101
t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

©2002 Fairchild Semiconductor Corporation FQB60N03L Rev. B

 FQB60N03L
Typical Characteristic (Continued) TC = 25°C unless otherwise noted

120 120
PULSE DURATION = 80ms PULSE DURATION = 80µs VGS = 10V
DUTY CYCLE = 0.5% MAX TJ = 25oC DUTY CYCLE = 0.5% MAX
100 VDD = 15V 100
TC = 25 oC VGS = 5V
ID , DRAIN CURRENT (A)

ID, DRAIN CURRENT (A)

80 80

60 60
VGS = 4V

40 40
TJ = 150o C
20 20 VGS = 3V
TJ = -55oC

0 0
1 2 3 4 5 6 0 0.5 1.0 1.5 2.0
VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)

Figure 5. Transfer Characteristics Figure 6. Saturation Characteristics

30 2.0
PULSE DURATION = 80µs PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE DUTY CYCLE = 0.5% MAX
25 ID = 51A
ON RESISTANCE
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)

1.5
20

ID = 27A
15
1.0
ID = 7A

10

VGS = 10V, ID = 51A

5 0.5
2 4 6 8 10
-80 -40 0 40 80 120 160
VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC)

Figure 7. Drain to Source On Resistance vs Gate Figure 8. Normalized Drain to Source On

Voltage and Drain Current Resistance vs Junction Temperature

1.2 1.2
VGS = VDS, ID = 250µA ID = 250µA
NORMALIZED DRAIN TO SOURCE

1.0
BREAKDOWN VOLTAGE
THRESHOLD VOLTAGE
NORMALIZED GATE

1.1

0.8

1.0
0.6

0.4 0.9

-80 -40 0 40 80 120 160 -80 -40 0 40 80 120 160

TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC)

Figure 9. Normalized Gate Threshold Voltage vs Figure 10. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature

©2002 Fairchild Semiconductor Corporation FQB60N03L Rev. B

 FQB60N03L
Typical Characteristic (Continued) TC = 25°C unless otherwise noted

2000 10

VDD = 15V

VGS , GATE TO SOURCE VOLTAGE (V)

CISS = C GS + CGD
8
1000
C, CAPACITANCE (pF)

COSS ≅ CGS + CGD 6

4
CRSS = CGD WAVEFORMS IN
DESCENDING ORDER:
2
ID = 51A
VGS = 0V, f = 1MHz ID = 27A

100 0
0.1 1 10 30 0 10 20 30
VDS , DRAIN TO SOURCE VOLTAGE (V) Qg , GATE CHARGE (nC)

Figure 11. Capacitance vs Drain to Source Figure 12. Gate Charge Waveforms for Constant
Voltage Gate Currents

150 200
VGS = 4.5V, VDD = 15V, ID = 12A VGS = 10V, VDD = 15V, ID = 12A
td(OFF)

150
SWITCHING TIME (ns)
SWITCHING TIME (ns)

100
tr td(OFF)

100
tf

50
tf tr
td(ON) 50
td(ON)

0 0
0 10 20 30 40 50 0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE (Ω) RGS, GATE TO SOURCE RESISTANCE (Ω)

Figure 13. Switching Time vs Gate Resistance Figure 14. Switching Time vs Gate Resistance

Test Circuits and Waveforms

VDS BVDSS

tP
VDS
L
IAS
VARY tP TO OBTAIN VDD
+
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS 0
0.01Ω
tAV

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

©2002 Fairchild Semiconductor Corporation FQB60N03L Rev. B

 FQB60N03L
Test Circuits and Waveforms (Continued)

VDS
VDD Qg(TOT)
RL
VDS
VGS = 10V

VGS Qg(5)
+

VDD VGS VGS = 5V

-

DUT VGS = 1V

Ig(REF) 0
Qg(TH)
Qgs Qgd

Ig(REF)
0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

VDS tON tOFF

td(ON) td(OFF)

RL tr tf
VDS
90% 90%

+
VGS
VDD 10% 10%
- 0

DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2002 Fairchild Semiconductor Corporation FQB60N03L Rev. B

 FQB60N03L
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the 80
thermal resistance of the heat dissipating path determines RθJA = 26.51+ 19.84/(0.262+Area)
the maximum allowable device power dissipation, PDM , in an
application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
60
must be reviewed to ensure that TJM is never exceeded.

RθJA (o C/W)
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.

(T –T )
JM A (EQ. 1) 40
P D M = -----------------------------
Z θJ A

In using surface mount devices such as the TO-263

package, the environment in which it is applied will have a 20
significant influence on the part’s current and maximum 0.1 1 10
power dissipation ratings. Precise determination of P DM is AREA, TOP COPPER AREA (in2)
complex and influenced by many factors: Figure 21. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.

Displayed on the curve are RθJA values listed in the

Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM .

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using
Equation 2. R θJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.

19.84
Rθ JA = 26.51 + ------------------------------------- (EQ. 2)
( 0.262 + Area )

©2002 Fairchild Semiconductor Corporation FQB60N03L Rev. B

 FQB60N03L
PSPICE Electrical Model
.SUBCKT FQB60N03L 2 1 3 ; rev October 2002

CA 12 8 9e-10
CB 15 14 9e-10
CIN 6 8 1.3e-9
LDRAIN
DBODY 7 5 DBODYMOD DPLCAP 5 DRAIN
DBREAK 5 11 DBREAKMOD 2
10
DPLCAP 10 5 DPLCAPMOD RLDRAIN
RSLC1
51 DBREAK
EBREAK 11 7 17 18 31.2 +
RSLC2
EDS 14 8 5 8 1 5
EGS 13 8 6 8 1 ESLC 11
51
-
ESG 6 10 6 8 1 50 +
EVTHRES 6 21 19 8 1 -
RDRAIN 17 DBODY
EVTEMP 20 6 18 22 1 ESG
6 EBREAK 18
8
EVTHRES -
+ 16
IT 8 17 1 + 19 - 21
LGATE MWEAK
EVTEMP 8
LDRAIN 2 5 1e-9 GATE RGATE + 6
18 -
1 22 MMED
LGATE 1 9 6.24e-9 9 20
LSOURCE 3 7 3.15e-9 RLGATE MSTRO
LSOURCE
CIN SOURCE
MMED 16 6 8 8 MMEDMOD 8 7 3
MSTRO 16 6 8 8 MSTROMOD
RSOURCE
MWEAK 16 21 8 8 MWEAKMOD RLSOURCE
S1A S2A
RBREAK 17 18 RBREAKMOD 1 12 RBREAK
13 14 15
RDRAIN 50 16 RDRAINMOD 2.3e-3 17 18
8 13
RGATE 9 20 1.79 RVTEMP
S1B S2B
RLDRAIN 2 5 10
13 CB 19
RLGATE 1 9 62.4 CA
IT
+ + 14 -
RLSOURCE 3 7 31.5
6 5 VBAT
RSLC1 5 51 RSLCMOD 1e-6 EGS EDS
8 8 +
RSLC2 5 50 1e3 - -
RSOURCE 8 7 RSOURCEMOD 6e-3 8
22
RVTHRES 22 8 RVTHRESMOD 1 RVTHRES
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),2.5))}

.MODEL DBODYMOD D (IS = 1.8e-12 RS = 6.4e-3 TRS1 = 2e-5 TRS2 = 1.1e-6 XTI=2 CJO = 7e-10 TT = 6e-9 M = 0.55)
.MODEL DBREAKMOD D (RS = 1.28 TRS1 = 2.48e-3 TRS2 = -2e-5)
.MODEL DPLCAPMOD D (CJO = 3.8e-10 IS = 1e-30 N = 10 M = 0.42)
.MODEL MMEDMOD NMOS (VTO = 1.86 KP = 3 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.79)
.MODEL MSTROMOD NMOS (VTO = 2.43 KP = 50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.6 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 17.9 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.8e-4 TC2 = -2.3e-8)
.MODEL RDRAINMOD RES (TC1 = 1.6e-2 TC2 = 1e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-7)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.2e-3 TC2 = -1.03e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 5e-7)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.0 VOFF= -2.0)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= -5.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.6 VOFF= 0.2)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.6)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2002 Fairchild Semiconductor Corporation FQB60N03L Rev. B

 FQB60N03L
SABER Electrical Model
REV October 2002
template FQB60N03L n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1.8e-12, rs = 6.4e-3, trs1 = 2e-5, trs2 = 1.1e-6, xti=2, cjo = 7e-10, tt = 6e-9, m = 0.55)
dp..model dbreakmod = (rs = 1.28, trs1 = 2.48e-3, trs2 = -2e-5)
dp..model dplcapmod = (cjo = 3.8e-10, isl=10e-30, nl=10, m=0.42)
m..model mmedmod = (type=_n, vto = 1.86, kp=3, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.43, kp = 50, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.6, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.0, voff = -2.0)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.0, voff = -5.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.6, voff = 0.2) LDRAIN
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.6) DPLCAP 5 DRAIN
2
10
c.ca n12 n8 = 9e-10 RLDRAIN
RSLC1
c.cb n15 n14 = 9e-10
51
c.cin n6 n8 = 1.3e-9 RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod 50 DBREAK
-
dp.dplcap n10 n5 = model=dplcapmod RDRAIN
6
ESG 11
8 DBODY
i.it n8 n17 = 1 + EVTHRES 16
+ 19 - 21
LGATE EVTEMP MWEAK
l.ldrain n2 n5 = 1e-9 8
GATE RGATE + 18 - 6
l.lgate n1 n9 = 6.24e-9 1 MMED EBREAK
9 22 +
l.lsource n3 n7 = 3.15e-9 20
RLGATE MSTRO 17
18
LSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u CIN - SOURCE
8 7
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u 3
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u RSOURCE
RLSOURCE
res.rbreak n17 n18 = 1, tc1 = 9.8e-4, tc2 = -2.3e-8 S1A S2A
12 RBREAK
res.rdrain n50 n16 = 2.3e-3, tc1 = 1.6e-2, tc2 = 1e-5 13 14 15
17 18
res.rgate n9 n20 = 1.79 8 13
res.rldrain n2 n5 = 10 S1B S2B RVTEMP
res.rlgate n1 n9 = 62.4 13 CB 19
CA
res.rlsource n3 n7 = 31.5 + + 14 IT -
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-7 6 5 VBAT
res.rslc2 n5 n50 = 1e3 EGS EDS +
8 8
res.rsource n8 n7 = 6e-3, tc1 = 1e-3, tc2 =1e-6 - - 8
res.rvtemp n18 n19 = 1, tc1 = -2.9e-3, tc2 = 5e-7 22
res.rvthres n22 n8 = 1, tc1 = -1.2e-3, tc2 = -1.03e-5 RVTHRES

spe.ebreak n11 n7 n17 n18 = 31.2

spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e-6/180))** 2.5))
}
}

©2002 Fairchild Semiconductor Corporation FQB60N03L Rev. B

 FQB60N03L
SPICE Thermal Model JUNCTION
th
REV 23 October 2002

FQB60N03L_Thermal

CTHERM1 th 6 1.0e-3
CTHERM2 6 5 3.5e-3
RTHERM1 CTHERM1
CTHERM3 5 4 4.8e-3
CTHERM4 4 3 5.2e-3
CTHERM5 3 2 8.0e-3
CTHERM6 2 tl 3.7e-2 6

RTHERM1 th 6 8.0e-3
RTHERM2 6 5 6.0e-2
RTHERM3 5 4 1.0e-1 RTHERM2 CTHERM2
RTHERM4 4 3 3.9e-1
RTHERM5 3 2 4.8e-1
RTHERM6 2 tl 5.1e-1
5

SABER Thermal Model

SABER thermal model FQB60N03L_Thermal RTHERM3 CTHERM3
template thermal_model th tl
thermal_c th, tl
{
4
ctherm.ctherm1 th 6 = 1.0e-3
ctherm.ctherm2 6 5 = 3.5e-3
ctherm.ctherm3 5 4 = 4.8e-3
ctherm.ctherm4 4 3 = 5.2e-3 RTHERM4 CTHERM4
ctherm.ctherm5 3 2 = 8.0e-3
ctherm.ctherm6 2 tl = 3.7e-2

rtherm.rtherm1 th 6 = 8.0e-3 3
rtherm.rtherm2 6 5 = 6.0e-2
rtherm.rtherm3 5 4 = 1.0e-1
rtherm.rtherm4 4 3 = 3.9e-1
RTHERM5 CTHERM5
rtherm.rtherm5 3 2 = 4.8e-1
rtherm.rtherm6 2 tl = 5.1e-1
}
2

RTHERM6 CTHERM6

tl CASE

©2002 Fairchild Semiconductor Corporation FQB60N03L Rev. B

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
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Across the board. Around the world.™ OCXPro™ RapidConnect™ UltraFET®
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.

As used herein:
1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

PRODUCT STATUS DEFINITIONS

Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In This datasheet contains the design specifications for
Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. I1