DATASHEET
Verdi
Automated debug Overview
system The Verdi® Automated Debug System is an advanced open platform for debug of digital
designs. It includes powerful technology that helps you comprehend complex and
unfamiliar design behavior, automate difficult and tedious debug processes and unify
diverse and complicated design environments.
Cut Debug Time in Half
The Verdi system lets you focus on tasks that add more value to your designs by
cutting your debug time, typically by over 50%. These time savings are made possible
by unique technology that:
• Automates behavior tracing using unique behavior analysis technology
• Extracts, isolates, and displays pertinent logic in flexible and powerful design views
• Reveals the operation of and interaction between the design,
assertions, and testbench
Figure 1: The unique behavior analysis technology of the Verdi system
automates many time-consuming aspects of debug
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Complete Debug System
The Verdi automated debug system incorporates all of the technology and capabilities you would expect in a debug system. In
addition, the Verdi system combines advanced debug features with support for a broad range of languages and methodologies.
Core Features
The Verdi system provides the following fundamental debug features:
• Full-featured waveform viewer enables you to display and analyze activity over time
• Powerful waveform comparison engine allows you to isolate differences between fast signal database (FSDB) files
• Source code browser enables you to easily traverse between source code and hierarchy
• Flexible schematics and block diagrams give you the ability to display logic and connectivity using familiar symbols
• Intuitive bubble diagrams help you to reveal the operation of finite state machines
Advanced Features
The Verdi system also includes the following advanced debug features:
• Automatic tracing of signal activity enables you to quickly trace activity across many clock cycles with powerful behavior
analysis technology
• Temporal flow views provide a combined display of time and structure to help you rapidly understand cause-and-
effect relationships
• Transaction-based debug with flexible transaction and message support for debug and analyzing designs at higher levels
of abstraction
• Assertion-based debug with built-in support for assertions facilitates quick traversal from assertion failure to related
design activity
• SystemVerilog Testbench debug with:
––Full source code support for SystemVerilog Testbench (SVTB) and libraries, including Universal Verification Methodology
(UVM), to ensure reusability and interoperability of testbench code
––Specialized views that help you understand testbench code, including declaration-based hierarchy browsing and navigation,
class inheritance and relationship comprehension, and tracing
––Built-in message logging and automated UVM transaction recording capabilities, coupled with advanced visualization
techniques, give you a complete picture of testbench activity in the post-simulation verification environment
––Full-featured interactive simulation control allows you to step through complex testbench code for more detailed analysis
––UVM-aware debug views allow users to explore verification results from specific UVM aspects like resources, factory,
phase and sequence
––Transaction-level debug views are based on extended FSDB and support new transaction and relation data recording
Resources Factory Phase Sequence
Figure 2: UVM-aware debug with built-in UVM intelligent viewers
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Languages and Methodologies
The Verdi system supports the following languages and methodologies:
• Design components described in Verilog, VHDL, and SystemVerilog
• Automated testbench environments using SVTB, as well as UVM, OVM and VMM
• Assertions using SystemVerilog Assertions (SVA)
Optimized Open Architecture and Unified Methodology
The Verdi automated debug system is designed so that you can take full advantage of your verification and debug methodology. The
Verdi system is built on the open Design Knowledge Architecture, which consists of compilers that extract relevant information into
databases that are optimized for efficient debug. The Verdi system also unifies your debug process by providing a single solution that
operates seamlessly and consistently across multiple domains: verification tools, design/verification languages, and abstractions.
This consistency reduces your learning curve and saves time as you move to new projects using different tools and languages, and
allows you to further leverage your investment in the Verdi system even as your other tools and methodology evolve.
The Design Knowledge Architecture is comprised of the following:
• Knowledge engine compilers extract design knowledge contained in HDL code, testbenches, and assertions
• Knowledge database (KDB) stores crucial design knowledge to facilitate debug and understanding of your design
• Fast signal database (FSDB) captures and stores results from simulators, emulators, and formal tools that produce time/
value sequences
• Application programming interfaces (APIs) provide open access to both databases and command-and-control mechanisms,
enabling you to easily integrate the Verdi system with other verification tools and design environments
Third-Generation Debug Platform
The Verdi platform builds on these core values with unprecedented personalization, customization and interoperability to maximize
your debug productivity. You can speed debug of your large, complex designs, tailor the debug environment for the way you work, and
directly integrate custom and third-party programs into your flows. Faster, smaller and more efficient infrastructure:
• Multi-threaded database boosts performance by more than 45%
• Compact format reduces file size by more than 30%
• Parallel simulation dumping for 30% productivity gain
Unification Automation
Flexible environment Efficient architecture
Comprehension
Integrated tools and flows
Figure 3: Verdi provides total debug solution
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Flexible graphical user interface for personalization:
• Fast access to source files, videos and user-defined documents
• Personalize window layout to fit your debug needs
• Different working modes for different debug purposes
• Centralized spotlight to search commands, preferences and documents
Seamless VC Apps integration for customized flows:
• Rich array of VC Apps programs to tailor Verdi deployment for user flows
• Customizable menu/toolbars enable VC Apps functions in Verdi user interface
• Direct launch of VC Apps-enabled third-party tools/scripts from debug environment
Design comprehension
HDL
Verdi Interoperable Apps
Design rule validation
SDC KDB C-API
TCL
FSDB investigation
FSDB
UPF/CPF Interoperability with
other tools
.lib Design Manipulation
Verdi
Figure 4: VC Apps: a platform for customizing Verdi
Interoperability and Customization
The open architecture and interoperability of the Verdi platform also enables you to leverage your investment with integration of other
commercial and proprietary verification tools. Its continuously expanding ecosystem provides out-of-the-box support for a wide range
of commonly used tools, including:
• Simulators
• Emulators and accelerators
• Model checkers and other formal analysis engines
You can further maximize the effectiveness of your Verdi deployment with custom automation programs that leverage the power of
its underlying design knowledge infrastructure for data mining and manipulation applications. Seamless integration with the VC Apps
platform provides everything you need to quickly create and integrate Open Source scripts/utilities with the Verdi software that are
designed to work reliably in your flow.
Personalized Graphical User Interface
The Verdi platform provides Qt-based GUI and flexible usage models with:
• Welcome page for access to information and debug modes including:
––Release notes, application notes and command reference documents
––Predefined modes for different debug tasks, such as hardware debug, testbench debug, power-aware and property debug
––Saved sessions with screenshots and text notes to restore/continue work
––Training videos that demonstrate how to use key features
––Customizable user links for sharing documents and web page
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• Window management system to personalize layout of debug environment:
––All components can be docked or undocked from major window
––Major modules like nWave, nSchema and TFV can be configured as standalone window
––One-click access to multiple source files within single window
––Customizable toolbar, menu and hot keys for natural fit with debug tasks
• Spotlight search for fast, efficient navigation of commands, manuals and preference settings
Debug and Analysis Across Multiple Abstraction Levels
The Verdi platform allows you to seamlessly debug throughout your system-level to gate-level methodology flow. It provides
additional support for verification and analysis at the implementation level with the nAnalyzer Design Implementation Analysis
Module, a single environment for analyzing troublesome design errors related to clocks, clock trees, and timing.
RTL nAnalyzer
Synthesis
Timing
Gate Power
Place and Clock
route
Silicon
Figure 5: Analyze and debug design implementation issues in a single, comprehensive environment
nAnalyzer Design Implementation Analysis Module
The nAnalyzer™ Design Implementation Analysis Module provides a single system for understanding and debugging critical design
implementation issues that typically arise during synthesis and related activities that transform an RTL description into a gate-
level netlist that is ready for tapeout. Throughout the flow, these transformations impact timing closure, power consumption, and
clocking schemes. To detect and resolve detrimental effects in these areas, you must analyze your designs using specialized tools
and techniques outside of the traditional simulation flow. The nAnalyzer solution both augments and enables these analysis steps
through the following capabilities:
• Explore, analyze, and identify problems with clock-related logic using powerful clock tree and clock domain extraction and
analysis engines
• Identify and isolate potential timing, power, or hot-spot problems early in the process through analysis of the netlist, Standard
Delay File (SDF) information, and simulation results
• View, understand, and explore the results of third-party clock, timing, and power analysis tools integrated with the
nAnalyzer solution
• Debug and isolate problems identified with the built-in or third-party capabilities using the powerful tracing and exploration
features provided in the Verdi Automated Debug System
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Clock Tree and Clock Domain Analysis
Today’s complex designs require special and often sophisticated clock schemes. Multiple clock domains introduce the need to
synchronize data passed between the different domains. Low-power stipulations require special clock gating techniques.
The integration of third-party IP presents unexpected clock-related challenges at the IP interface. All of these factors increase
the complexity of the clock circuitry and introduce more opportunities for implementation errors and thus incorrect operation.
The nAnalyzer solution provides powerful built-in analysis engines that enable comprehensive exploration and debug of common
clock-related issues.
User inputs
(SDC, CTS constraints draft)
RTL
nAnalyzer
Clock tree analysis
Clock tree and clock domain extraction
Easy-to-use clock tree browser
Cross-domain synchronization checking Synthesis
Clock
Clock tree synthesis (CTS) support DB Gate
CTS constraint development and checking
Clock tree synthesis result qualification Placement
Level and delay (skew and insertion) CTS
annotation and anlysis constraints
CTS
Timing analysis results display and exploration
Routing
Netlist
Timing
report STA
Figure 6: Using nAnalyzer in clock tree synthesis flow for CTS results comprehension and improvement
Clock Analysis Features
• Extract clock trees, clock domains, and clock domain crossings from RTL or gate-level descriptions
• Browse analysis results in text form or display and explore them in intuitive Verdi schematics
• Import SDC information to identify clock sources and further constrain the analysis
• Pre-qualify clock tree synthesis (CTS) scripts to check for incorrect or incomplete constraints
• Develop and export SDC and CTS scripts to drive the CTS process
• Identify common problems such as flops outside of extracted clock trees and clocks connected to non-clock pins
• Verify proper cross-domain synchronization using user-defined synchronization methods
• Import SDF information and/or static timing analysis results to extract and display timing details—level delay, skew, slack time
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Timing and Power Analysis
Although dedicated tools exist that provide comprehensive analysis and verification in the timing and power analysis domains,
it is often useful to interactively explore timing and power issues outside of these tools. In some cases, the data required for a
comprehensive analysis may not be available. In other cases, the dedicated tool may take a long time to complete its analysis,
but only a quick approximation is needed. The nAnalyzer solution provides built-in analysis capability in both the timing and power
domains to meet these needs.
Timing Analysis Features
• Import reports from common static timing analysis (STA) tools
• Browse critical path details in text form or display and explore them in intuitive Verdi schematics
• Import SDF information and annotate the delay information on schematic views
• Calculate and display longest/shortest paths based on imported delay information
Power Analysis Features
• Analyze simulation results and identify areas of heaviest switching activity
• Sort and explore switching activity by signal, module, time, or time window
• Explore related logic using Verdi’s powerful tracing and visualization capabilities
Interoperability with Third-Party Tools
Complete analysis and resolution of timing, power and clock scheme related issues often require the application of best-in-class tools
dedicated to one of these domains. The nAnalyzer solution enhances your usability of these dedicated tools by importing, displaying,
and enabling the exploration of the analysis results in the familiar Verdi environment.
Embedded Software Debug
Verdi HW SW Debug works with the Verdi Debug Automation System to provide a comprehensive multi-window hardware and
software debug view of an SoC design. Hardware and software engineers can both simultaneously view their design at the hardware
and software level, including C/C++ and assembly code as well as memory, register and breakpoint windows. Please refer to the Verdi
HW SW Debug datasheet for more details.
Low Power Simulation Debug
Verdi Power-Aware Debug works with the Verdi Debug Automation System to enable the analysis of the impact of power intent on a
design, and accelerates the debug of unexpected design behavior by automating the process of visualizing and tracing the source of
power-related errors. Please refer to the Verdi Power-Aware Debug datasheet for more details.
Mixed-Signal Simulation Debug
Verdi Advanced AMS Debug works with the Verdi Debug Automation System to enable seamless debug for co-simulation of analog,
digital and mixed-signal subsystems within a unified debug environment. It accelerates debug of the interfaces between analog and
digital designs and simplifies the manual and painful process of co-simulation setup. Please refer to the Verdi Advanced AMS Debug
datasheet for more details.
For more information about Synopsys products, support services or training, visit us on the web at: synopsys.com,
contact your local sales representative or call 650.584.5000.
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