VNHD7008AY

H-bridge motor driver for automotive DC motor driving

Datasheet - production data

 MultiSense diagnostic functions

– Output short to ground detection
– Thermal shutdown indication
PowerSSO-36 GAPGCFT00004 – OFF-state open-load detection
– Output short to VCC detection
Features  Standby mode
 Half bridge operation
Type RDS(on) Iout VCCmax  Charge pump output for reverse battery
protection
8 mtyp
VNHD7008AY 51 A 38 V  Package: ECOPACK
per channel)

 AEC-Q100 qualified Description

 Output current: 51 A The device is a DC motor driver for automotive
 Dual fully protected HSD with MultiSense applications. It integrates a full protected dual
feedback high-side driver and the drivers and protections
for the two external power MOSFETs in low-side
 Two integrated drivers for the external LSDs configuration.
 3 V CMOS compatible inputs
The device is designed using STMicroelectronics
 Protections: well known and proven proprietary VIPower® M0
– Undervoltage shutdown technology that allows to efficiently integrate on
– Overvoltage clamp the same die a true PowerMOSFET with an
– Thermal shutdown intelligent signal/ protection circuitry. The device
is housed in a PowerSSO-36 exposed pad
– Load current limitation
package to optimize the dissipation
– Self-limiting of fast thermal transients performances.
(Power Limitation)
– Cross current protection The input signals INA and INB can directly
interface the microcontroller to select the motor
– Shoot through protection
direction and the brake conditions. Two selection
– Loss of ground and loss of VCC pins (SEL0 and SEL1) are available to address to
– Electrostatic discharge protection the microcontroller the information available on
– Drain and source voltage monitoring of the the MultiSense. The MultiSense pin allows to
external power MOSFETs, configurable via monitor the motor current, provides a voltage
an external resistance (short-to-battery proportional to the battery value and the
protection) information on the temperature of the chip. The
 PWM operation up to 20 kHz for external LSDs integrated protections are: load current limitation,
overload active power limitation (with latch-off),
 MultiSense monitoring functions overtemperature shutdown (with latch-off) and
– Analog motor current feedback cross current protection.
– Chip temperature monitoring
– Battery voltage monitoring

April 2020 DS11459 Rev 6 1/44

This is information on a product in full production. www.st.com
Contents VNHD7008AY

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 Power limitation (high-side driver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3 High-side current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 External PowerMOS low side VDS monitoring . . . . . . . . . . . . . . . . . . . . . 27

4 Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5 MultiSense operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 MultiSense analog monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 Multisense diagnostics flag in fault conditions . . . . . . . . . . . . . . . . . . . . . 29

6 VREG and Driver_LS Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9 Immunity against transient electrical disturbances . . . . . . . . . . . . . . . 31

10 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.1 PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

11 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

11.1 PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11.2 PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2/44 DS11459 Rev 6

VNHD7008AY Contents

11.3 PowerSSO-36 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

DS11459 Rev 6 3/44

3
List of tables VNHD7008AY

List of tables

Table 1. Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Suggested connection for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Logic inputs (INA, INB) (Vcc = 7 V up to 28 V; -40 °C < Tj < 150 °C) . . . . . . . . . . . . . . . . . 12
Table 8. HSD switching (VCC = 13 V; RLOAD = 1.1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. Gate driver for external MOS parameters (VCC = 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 10. Protections and diagnostics (7 V < VCC < 18 V; -40 °C < Tj < 150 °C). . . . . . . . . . . . . . . . 13
Table 11. MultiSense (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. Operative condition - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. On-state fault conditions- truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. Off-state — truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. IISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . 31
Table 16. PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 17. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. PowerSSO-36 (exposed pad) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4/44 DS11459 Rev 6

VNHD7008AY List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. Low-side turn-on delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Input reset time for HSD-fault unlatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Input reset time for LSD-fault unlatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL) . . . . . . . . . . . . . . . . 21
Figure 11. Normal operative conditions (resistive load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Out shorted to ground and short clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. OUT shorted to Vcc and short clearing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Gate driver low side rise time normalized vs Cg = 4.7nF . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Gate driver low side fall time normalized vs Cg = 4.7nF . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. MultiSense block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 18. PowerSSO-36 PCB board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20. Thermal fitting model of a double-channel HSD in PowerSSO-36 . . . . . . . . . . . . . . . . . . . 34
Figure 21. Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 23. PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 24. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 25. PowerSSO-36 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DS11459 Rev 6 5/44

5
Block diagram and pin description VNHD7008AY

1 Block diagram and pin description

Figure 1. Block diagram

VREG VBATT CP VCC

Reverse LSA_OVERTEMPERATURE LSB_OVERTEMPERATURE Power

VREG Driver Limitation
HSA_OVERTEMPERATURE UV HSB_OVERTEMPERATURE

CLAMP HS A CP CP CLAMP HS B

DRIVER DRIVER
HS A HS A LOGIC HS B
HS B

CURRENT Open-load Open-load CURRENT

LIMITATION A OFF-state A OFF-state B LIMITATION B

OUT A 1/K FAULT 1/K OUT B

DETECTION
CLAMP LS A
CLAMP LS B

DRIVER DRIVER
GATE_LSA LS A LS B GATE_LSB
MUX
VREF_OVL_LSB VREF_OVL_LSB
VDS_MONITORING VDS_MONITORING

KSOURCE_LSA IN A IN B PWM KSOURCE_LSB

SEL1
SEL0
MultiSense
MultiSense_EN

GAPG2808151154_2CFT

Table 1. Block description

Name Description

Allows the turn-on and the turn-off of the high-side and the
Logic control
low-side switches according to the truth table.
Undervoltage (US) Shuts down the device for battery voltage below (4 V).
Protect the high-side and the low-side switches from the high
High-side and low-side clamp voltage
voltage on the battery line.
Drive the gate of the concerned switch to allow a proper Ron
High-side and low-side driver
for the leg of the bridge.
Current limitation Limits the motor current in case of short circuit.
In case of short-circuit with the increase of the junction
High-side overtemperature protection temperature, it shuts down the concerned driver to prevent
degradation and to protect the die.
VDS_MONITORING Protection of LSD powers against short to battery failure
Internal voltage regulator that provides the supply for the
VREG
gates of the external low-side switches
Signalizes an abnormal condition of the power stage (output
Fault detection shorted to ground or output shorted to battery) by a feedback
on the MultiSense

6/44 DS11459 Rev 6

VNHD7008AY Block diagram and pin description

Table 1. Block description (continued)

Name Description

Limits the power dissipation of the high-side driver inside

Power limitation
safe range in case of short to ground condition.
Signalize, in combination with an external resistor, an open-
Open-load in OFF-state load when the switches are off by a feedback on the
MultiSense
Provides a signal linked to the Chip temperature by a
Tchip monitoring
feedback on the MultiSense
Provides a signal linked to the Chip temperature by a
VCC monitoring
feedback on the MultiSense
Drives an external PowerMOSFET to provide the reverse
Reverse driver
battery protection
Charge pump to drive the external N-MOSFET used on the
CP battery track for the reverse battery protection. 
The N-MOSFET source must be connected to the Vbatt pin.

Figure 2. Configuration diagram (top view)

OUTA 1 36 OUTB
OUTA OUTB
OUTA OUTB
OUTA OUTB
OUTA OUTB
OUTA OUTB
OUTA OUTB
OUTA OUTB
OUTA OUTB
OUTA TAB = V CC OUTB
SEL0 SEL1
MultiSense_EN VREG
GATE_LSA GATE_LSB
KSOURCE_LSA KSOURCE_LSB
VREF_OVL_LSA VREF_OVL_LSB
INA IN B
CP PWM
Vbatt 18 19 MultiSense

GAPG2808151437CFT

DS11459 Rev 6 7/44

43
Block diagram and pin description VNHD7008AY

Table 2. Pin definitions and functions

Pin N° Symbol Function

20 PWM PWM input.

25 VREG Internal supply output

16 INA Clockwise input.

Battery supply, connection to the source of the external

18 Vbatt
PowerMOS used for the reverse battery protection

19 MultiSense Output of current sense and diagnostic feedback

12 MultiSense_EN Enables the MultiSense diagnostic pin

11 SEL0 Address the MultiSense multiplexer (refer to Table 12)

26 SEL1 Address the MultiSense multiplexer (refer to Table 12)

21 INB Counter clockwise input.

1, 2, 3, 4, 5, 6, 7,
OUTA Source of high-side switch A
8, 9, 10
27, 28, 29, 30, 31,
OUTB Source of high-side switch B
32, 33, 34, 35, 36
Drives the gate of external P-MOSFET for the reverse
17 CP
battery protection

15 VREF_OVL_LSA Sets the threshold for VDS_MONITORING feature for LSA

22 VREF_OVL_LSB Sets the threshold for VDS_MONITORING feature for LSB

13 GATE_LSA Gate driver of the external PowerMOS LSA

24 GATE_LSB Gate driver of the external PowerMOS LSB

14 KSOURCE_LSA Source of external LSA. Ground connection

23 KSOURCE_LSB Source of external LSB. Ground connection

Supply voltage. Drain of the high-side switches and

TAB VCC connection to the drain of the external PowerMOS used for
the reverse battery protection

Table 3. Suggested connection for unused and not connected pins

GATE_LSA,
Inx, PWM, SELx, VREF_OVL_LSA,
Connection / pin OUTA, OUTB Multisense GATE_LSB, CP,
Multisense_EN VREF_OVL_LSB
VREG

Floating X X X X X
To ground Not allowed Through 10 kΩ resistor Not allowed X

8/44 DS11459 Rev 6

VNHD7008AY Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

IB IS

IDS_LSA ICP
V REF_OVL_LSA Vbatt TAB = V CC CP
IDS_LSB IOUTA
OUTA
V REF_OVL_LSB
IINA IOUTB
OUTB
INA
ISENSE
IINB MultiSense
INB ISEN
ISEL0 MultiSense_EN
SEL0

KSOURCE_LSA

KSOURCE_LSB
ISEL1
SEL1
GATE_LSA

GATE_LSB
IREG
VREG
PWM
VSEN V VOUTB VOUTA VCP VCC
SENSE
IPWM IGLSB IGLSA
VDS_LSA

VDS_LSB

IGND
VSEL0

VSEL1

VREG

VPWM VGLSA
VINA

VINB

VGLSB

GAPG3109150935CFT

2.1 Absolute maximum ratings

Stressing the device above the rating listed in Table 4 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

VCC H-Bridge supply voltage 38 V

VBAT Maximum battery voltage(1) -16 to 38 V
Internally
Imax DC output current A
limited
IR Reverse output current (continuous)(2) 30 A
IIN Input current (INA and INB pins) -1 to 10 mA
ISEL SEL0,1 DC input current -1 to 10 mA
IPWM PWM Input current -1 to 10 mA
IMultiSense_EN SenseEnable DC input current -1 to 1.5 mA
MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V) 10 mA
IMultiSense
MultiSense pin DC output current in reverse (VCC < 0 V) -20 mA
VREG VREG DC voltage 12 V

DS11459 Rev 6 9/44

43
Electrical specifications VNHD7008AY

Table 4. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

VBATT -6 to
VCP VCP DC voltage V
VBATT +14
VGATE_LSx GATE_LAS, GATE_LSB DC voltage 12 V
VREF_OVL_LSx VREF_OVL_LSA, VREF_OVL_LSB input current -1 to 10 V

Electrostatic discharge (Human body model: R = 1.5 kΩ; C = 100 pF)

– MultiSenseVREG, VREF_OVL_LSx
VESD 2 kV
– INA, INB, OUTA, OUTB, PWM, SEL0, SEL1, SENSE_EN
4
– GATE_LSx
4
Tc Junction operating temperature -40 to 150 °C
TSTG Storage temperature -55 to 150 °C
IK_SOURCE_LSx DC reverse ground pin current (per leg) 100 mA
1. This applies with the n-channel MOSFET used for the reverse battery protection. Otherwise VBAT has to be shorted to VCC.
2. Based on the internal wires capability.
All logic pins cannot be left floating but they must be connected to GND if unused.

2.2 Thermal data

Table 5. Thermal data
Symbol Parameter Max. value Unit

Thermal resistance junction-case (per leg channel) 

Rthj-case 2.4 °C/W
(JEDEC JESD 51-8)
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5)(1) 50.6 °C/W
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-7) 16.6 °C/W
1. Device mounted on two-layers 2s0p PCB with 2 cm2.heatsink copper trace.

10/44 DS11459 Rev 6

VNHD7008AY Electrical specifications

2.3 Electrical characteristics

VCC = 7 V up to 28 V; -40 °C < Tj < 150 °C, unless otherwise specified.

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

Operating supply
VCC 4 28 V
voltage
Off-state standby
INA = INB = PWM = Multisense_EN= 0;  1 µA
SEL0,1 = 0; Tj = 25 °C; VCC = 13 V
Off-state standby; 
INA = INB = PWM = Multisense_EN= 0;  1 µA
SEL0,1 = 0; VCC = 13 V; Tj = 85 °C
Off-state standby;
INA = INB = PWM = Multisense_EN= 0;  10 µA
SEL0,1 = 0; VCC = 13 V; Tj = 125 °C

IS Supply current Off-state (no standby) 

INA = INB = PWM = Multisense_EN= 0; 4 8 mA
SEL0,1 = 5 V
On-state: INA or INB = 5V; 
PWM = 0 V or PWM = 5 V;
6 12 mA
SEL0 = 0 or SEL0 = 5 V;
SEL1 = 0 or SEL1 = 5 V
On-state: INA = INB = 5V; 
PWM = 0 V or PWM = 5 V;
9 18 mA
SEL0 = 0 or SEL0 = 5 V;
SEL1 = 0 or SEL1 = 5 V
VCC = 13 V; INA = INB = SEL1 =
Standby mode
tD_STBY MultiSense_EN = PWM = 0 V;  60 300 550 µs
blanking time
VSEL0 from 5 V to 0 V.
IOUT = 12 A; Tj = 25 °C, 
8 mΩ
VCC = 13 V
Static high-side
RONHS IOUT = 12 A;
resistance 16 mΩ
Tj = - 40 °C to 150 °C
VCC = 4 V, IOUT = 12 A, Tj=25 °C 8
High-side free-
Vf wheeling diode forward IOUT = -12 A; Tj = 150 °C 0.6 0.7 V
voltage
INA = INB = PWM = 0; VOUT = 0 V;
0 0.5 µA
Off-State Output VCC = 13 V; Tj = 25 °C
IL(off)
current of one output INA = INB = PWM = 0; VOUT = 0 V;
0 5 µA
VCC = 13 V; Tj = 125°C
Off-state output current
IL(off_h) of one output with INA = PWM = 0; INB = 5 V; VCC = 13 V 20 60 µA
other HSD on

DS11459 Rev 6 11/44

43
Electrical specifications VNHD7008AY

Table 7. Logic inputs (INA, INB) (Vcc = 7 V up to 28 V; -40 °C < Tj < 150 °C)
Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Input low level voltage 0.9 V

VIH Input high level voltage 2.1 V
VIHYST Input hysteresis voltage 0.2 V
IIN = 1 mA 5.3 7.2 V
VICL Input clamp voltage
IIN = -1 mA -0.7 V
IINL Input current VIN = 0.9 V 1 µA
IINH Input current VIN = 2.1 V 10 µA

SEL0, SEL1 (VCC = 7 V up to 18 V; -40 °C < Tj < 150 °C)

VSELL Input low level voltage 0.9 V

ISELL Low level input current VSEL = 0.9 V 1 µA
VSELH Input high level voltage 2.1 V
ISELH High level input current VSEL = 2.1 V 10 µA
VSEL(hyst) Input hysteresis voltage 0.2 V
ISEL = 1 mA 5.3 7.2 V
VSELCL Input clamp voltage
ISEL = -1 mA -0.7 V

PWM (VCC = 7 V up to 28 V; -40 °C < Tj < 150 °C)

VPWM Input low level voltage 0.9 V

IPWM Low level input current VPWM = 0.9 V 1 µA
VPWM Input high level voltage 2.1 V
IPWMH High level input current VPWM = 2.1 V 10 µA
VPWM(hyst) Input hysteresis voltage 0.2 V
IPWM = 1 mA 5.3 7.2 V
VPMWCL Input clamp voltage
IPWM = -1 mA -0.7 V

MultiSense_EN (VCC = 7 V up to 18 V; -40 °C < Tj < 150 °C)

VSEnL Input low level voltage 0.9 V

ISEnL Low level input current VSEn = 0.9 V 1 µA
VSEnH Input high level voltage 2.1 V
ISEnH High level input current VSEn = 2.1 V 10 µA
VSEn(hyst) Input hysteresis voltage 0.2 V
ISEn = 1 mA 5.3 7.5 V
VSEnCL Input clump voltage
ISEn = -1 mA -0.7 V

12/44 DS11459 Rev 6

VNHD7008AY Electrical specifications

Table 8. HSD switching (VCC = 13 V; RLOAD = 1.1 )

Symbol Parameter Test conditions Min. Typ. Max. Unit

Input rise time < 1 µs;

MultiSense_EN = 5 V (no
td(on) Turn-on delay time 53 µs
standby); SEL0,1 = 0; PWM = 0
(see Figure 6)
Input rise time < 1 µs;
MultiSense_EN = 5 V (no
td(off) Turn-off delay time 20 µs
standby); SEL0,1 = 0; PWM = 0
(see Figure 6)

Table 9. Gate driver for external MOS parameters (VCC = 13 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

f(1) PWM frequency 0 20 kHz

PWM = 5 V; INx = 0 V 10 V
Vgs_lsd Gate_LSD voltage VCC = 4 V, PWM = 5 V,
4 V
INx = 0 V, Tj=25 °C
Input rise time < 1 µs
tcross Low-side turn-on delay time 40 160 300 µs
(see Figure 7)
VCC = 13.5 V; Rg = 0 Ω;
tgr_ls Rise time Cg = 4.7 nF 0.25 0.5 µs
(see Figure 5)
VCC = 13.5 V; Rg = 0 Ω;
tgf_ls Fall time Cg = 4.7 nF 0.35 0.5 µs
(see Figure 5)
1. Parameter guaranteed by design.

Table 10. Protections and diagnostics (7 V < VCC < 18 V; -40 °C < Tj < 150 °C)
Symbol Parameter Test conditions Min. Typ. Max. Unit

VUSD Undervoltage shutdown VCC falling 4 V

VUSDreset Undervoltage shutdown reset VCC rising 5 V
Undervoltage shutdown
VUSDhyst 0.3 V
hysteresis
51 77 110 A
ILIM_HSD High-side current limitation
(1)
VCC = 4 V, Tj=25 °C 66 A
High-side driver clamp IOUT = 100 mA;
VCL_HSD voltage (VCC to OUTA = 0 or tclamp = 1 ms; 38 46 V
OUTB = 0) Iclamp = 100 mA
Low-side clamp voltage IOUT = 100 mA;
VCL_LSD(1) (OUTA = VCC or OUTB = VCC tclamp = 1 ms; 38 46 52 V
to GND) Iclamp = 100 mA
Low-side drain-current
tDEL_OVL_LSD 1 5 µs
overload blanking time

DS11459 Rev 6 13/44

43
Electrical specifications VNHD7008AY

Table 10. Protections and diagnostics (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit

Low-side drain-current
IREF_OVL_LSD 40 50 60 µA
overload reference current
Low-side drain-current
VREF_OVL_LSD_MIN overload threshold voltage 0.32 0.4 0.8 V
minimum
Low-side drain-current
VREF_OVL_LSD_MAX overload threshold voltage 1.6 2 2.4 V
maximum
High-side thermal shutdown
TTSD_HSD INx = 2.1 V 150 175 200 °C
temperature
High-side thermal reset
TTR_HSD 135 °C
temperature
High-side thermal hysteresis 
THYST_HSD 7 °C
(TSD_HSD - TR_HSD)
ΔTj_SD(1) Dynamic temperature 60 °C
OFF-state output sink current INA = INB = 0; PWM = 0;
IL(off3) 0 1.1 2.5 mA
with VOUT = VCC VOUT = VCC
IOUT = 100 mA;
Clamp signal 
VCL tclamp = 1 ms; 38 46 52 V
(VCC to GND)
Iclamp = 100 mA
INA = INB = 0; PWM = 0;
OFF-state open-load voltage VSEL0 = 5 V for CHA;
VOL 2 3 4 V
detection threshold VSEL0 = 0 V and within
tD_STBY for CHB
INA = INB = 0; VOUT = 2 V;
PWM = 2 V;
IL(off2) OFF-state output sink current VSEL0 = 5 V for CHA; -150 -5 µA
VSEL0 = 0 V and within
tD_STBY for CHB
OFF-state diagnostic delay INA = 5 V to 0 V; INB = 0;
tDSTKON time from falling edge of PWM = 0; VSEL0 = 5 V; 40 160 300 µs
INPUT (see Figure 4) IOUT = 0 A; VOUTA = 4 V
VCP - VBAT = VGS_CP 8 12 15 V
VGS_CP CP output voltage VBAT = -16 V; 
0.6 V
VCP - VBAT = VGS_CP
INA = INB = 0 V; PWM = 0;
OFF-state diagnostic delay VOUTx = 0 V to 4 V;
tD_VOL time from rising edge of VOUT VSEL1 = 0 V for CHA; 5 30 µs
(see Figure 10) VSEL0,1 = 0 V;
SENSE_EN = 5 V for CHB
Input reset time for high-side VINx = 5 V to 0 V; HSDx
tLATCH_RST_HS 3 10 20 µs
fault unlatch faulting (see Figure 8)

14/44 DS11459 Rev 6

VNHD7008AY Electrical specifications

Table 10. Protections and diagnostics (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit

Input reset time for low-side VINx = 0 V to 5 V; LSDx

tLATCH_RST_LS 3 10 20 µs
fault unlatch faulting (see Figure 9)
Low-side drain current
tstby_ovl_lsd overload delay time form stby 50% of VSENSEH 20 µs
exit
1. Parameter guaranteed by design and characterization; not subject to production test.

Table 11. MultiSense (7 V < VCC < 18 V; -40 °C < Tj < 150 °C)
Symbol Parameter Test conditions Min. Typ. Max. Unit

MultiSense clamp VSEn = 0 V; ISENSE = -1 mA 7 V

VSENSE_CL
voltage VSEn = 0 V; ISENSE = 1 mA -17 -12 V
IOUT = 0.25 A; VSENSE = 0.5 V
KOL IOUT/ISENSE 6300 10500 14700
Tj = -40 °C to 150 °C
IOUT = 2 A; VSENSE = 0.5 V;
K0 IOUT/ISENSE 8400 10900 13400
Tj = -40 °C to 150 °C
IOUT = 6 A; VSENSE = 0.5
K1 IOUT/ISENSE 8700 11000 13200
Tj = -40 °C to 150 °C
IOUT = 12 A; VSENSE = 4 V;
K2 IOUT/ISENSE 9000 11000 13000
Tj = -40 °C to 150 °C
IOUT = 24 A; VSENSE = 4 V
K3 IOUT/ISENSE 9200 11000 12200
Tj = -40 °C to 150 °C
Analog sense IOUT = 0.25 A; VSENSE = 0.5 V;
dKOL/KOL(1) -25 25 %
current drift Tj = -40 °C to 150 °C
IOUT = 2 A; VSENSE = 0.5 V;
Analog sense
dK0/K0(1) VSENSE_EN = 0 V;  -5 5 %
current drift
Tj = -40 °C to 150 °C
IOUT = 6 A; VSENSE = 0.5 V;
Analog sense
dK1/K1(1) VSENSE_EN = 0 V;  -5 5 %
current drift
Tj = -40 °C to 150 °C
Analog sense IOUT = 12 A; VSENSE = 4 V;
dK2/K2(1) -5 5 %
current drift Tj = -40 °C to 150°C
Analog sense IOUT = 24 A; VSENSE = 4 V;
dK3/K3(1) -5 5 %
current drift Tj = -40 °C to 150°C
VCC = 7 V; RSENSE = 10 kΩ;
Max analog sense
VSENSE_SAT IOUT = 24 A; VSEL0 = 5 V; 5 V
output voltage
Tj = 150 °C
MultiSense VCC = 7 V; VINA = 5 V; VINB = 0 V;
ISENSE_SAT(2) 4 mA
saturation current VSEL0 = 5 V; Tj = 150°C
VCC = 7 V; VSENSE = 4 V;
Output saturation
IOUT_SAT(2) VINA = 5 V; VINB = 0 V; VSEL0 = 5 V; 48 A
current
Tj = 150°C

DS11459 Rev 6 15/44

43
Electrical specifications VNHD7008AY

Table 11. MultiSense (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit

Output Voltage for VINA = 5 V; VINB = 0 V; VSEL0 = 5 V;

VOUT_MSD(2) MultiSense VSEL1 = 0 V; RSENSE = 2.7 kΩ 5 V
shutdown IOUT = 24 A
VMultiSense = VSENSE_EN = PWM = 0
V; INA = INB =0 V; SEL0 = SEL1 = 0; 0 0.5 µA
Tj = -40 °C to 150°C (standby)
SEn = 5 V; INA = INB = 5 V;
PWM = 0 V; SideX diagnostic
selected; IOUTx = 0 A
E.g.
0 12 µA
– SideA: SEL0 = 5 V; SEL1 = 0 V;
MultiSense leakage IOUTA = 0 A; IOUTB = 12 A
ISENSE0
current – SideB: SEL0 = 0 V; SEL1 = 0 V;
IOUTA = 12 A; IOUTB = 0 V
SEn = 5 V; PWM = 0 V; SideX
diagnostic selected; HSx OFF
E.g.
– SideA: SEL0 = 5 V; SEL1 = 0 V; 0 10 µA
INA = 0 V; INB = 5 V; IOUTB = 12 A
– SideB: SEL0 = 0 V; SEL1 = 0 V;
INA = 5 V; INB = 0 V; IOUTA = 12 A
MultiSense output VCC = 13 V; RSENSE = 1 kΩ;
VSENSEH voltage in fault – E.g: Ch0 in open-load; VIN = 0 V; 5 7 V
condition IOUT = 0 A; VOUT = 4 V
9 V < VCC < 18 V;
MultiSense current
ISENSEH VSENSE = 5 V; MultiSense in fault 10 20 30 mA
in fault condition
condition

Chip temperature analog feedback

VSENSE_EN = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN = 0 V; 2.325 2.41 2.495 V
RSENSE = 1 kΩ; Tj = -40 °C
MultiSense output VSENSE_EN = 5 V; VSEL0 = 0 V;
VSENSE_TC voltage proportional VSEL1 = 5 V; VIN = 0 V; 1.985 2.07 2.155 V
to chip temperature RSENSE = 1 kΩ; Tj = 25 °C
VSENSE_EN = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN = 5 V; 1.435 1.52 1.605 V
RSENSE = 1 kΩ; Tj = 125 °C
dVSENSE_TC/dT Temperature
(2) Tj = -40 °C to 150 °C -5.5 mV/K
coefficient
Transfer function VSENSE_TC(T) = VSENSE_TC(T0) + dVSENSE_TC/dT * (T - T0)

VCC supply voltage analog feedback

16/44 DS11459 Rev 6

VNHD7008AY Electrical specifications

Table 11. MultiSense (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit

MultiSense output
voltage proportional VCC = 13 V; VSENSE_EN = 5 V;
VSENSE_VCC 3.16 3.23 3.3 V
to VCC supply VSEL0 = VSEL1 = 5 V; RSENSE = 1 kΩ
voltage
Transfer function VSENSE_VCC = VCC/4

MultiSense timings (Multiplexer transition times)(2)

VINA = 5 V; VSENSE_EN = 5 V;
MultiSense
VSEL0 = 5 V to 0 V;
transition delay from
tD_CStoTC VSEL1 = 0 V to 5 V; IOUTA = 2.5 A; 60 µs
current sense to TC
RSENSE = 1 kΩ; VSENSE_TC = 90% of
sense
VSENSE_TC_FINAL
VINA = 5 V; VSENSE_EN = 5 V;
MultiSense
VSEL0 = 0 V to 5 V;
transition delay from
tD_TCtoCS VSEL1 = 5 V to 0 V; IOUTA = 2.5 A; 20 µs
TC sense to current
RSENSE = 1 kΩ; ISENSE = 90% of
sense
ISENSE_MAX
VINA = 5 V; VSENSE_EN = 5 V;
MultiSense
VSEL0 = 5 V; VSEL1 = 0 V to 5 V;
transition delay from
tD_CStoVCC I = 2.5 A; RSENSE = 1 kΩ; 60 µs
current sense to VCC OUTA
VSENSE_VCC = 90% of
sense
VSENSE_VCC_FINAL
MultiSense VINA = 5 V; VSENSE_EN = 5 V;
transition delay from VSEL0 = 5 V; VSEL1 = 5 V to 0 V;
tD_VCCtoCS 20 µs
VCC sense to current IOUTA = 2.5 A; RSENSE = 1 kΩ;
sense ISENSE = 90% of ISENSE_MAX
VCC = 13 V; Tj = 125 °C;
MultiSense VSENSE_EN = 5 V; 
transition delay from VSEL0 = 0 V to 5 V;
tD_TCtoVCC 20 µs
TC sense to VCC VSEL1 = 5 V; RSENSE = 1 kΩ;
sense VSENSE_VCC = 90% of
VSENSE_VCC_FINAL
VCC = 13 V; Tj = 125 °C;
MultiSense VSENSE_EN = 5 V; 
transition delay from VSEL0 = 5 V to 0 V;
tD_VCCtoTC 20 µs
VCC sense to TC VSEL1 = 5 V; RSENSE = 1 kΩ;
sense VSENSE_TC = 90% of
VSENSE_TC_FINAL

MultiSense timings (CurrentSense mode)

VINA = 5 V; VINB = 0 V;
Current sense
VSENSE_EN = 0 V to 5 V;
settling time from
tDSENSE1H RSENSE = 1 k; RL = 2.6 Ω 60 µs
rising edge of
VPWM = 5 V; VSEL0 = 5 V;
VSENSE_EN
VSEL1 = 0 V

DS11459 Rev 6 17/44

43
Electrical specifications VNHD7008AY

Table 11. MultiSense (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit

VINA = 5 V; VINB = 0 V;
Current sense
VSENSE_EN = 5 V to 0 V;
disable delay time
tDSENSE1L RSENSE = 1 k; RL = 2.6 Ω 20 µs
from falling edge of
VPWM = 5 V; VSEL0 = 5 V;
VSENSE_EN
VSEL1 = 0 V
VSENSE_TC settling VSENSE_EN = 0 V to 5 V;
tDSENSE2H time from rising VSEL0 = 0 V; VSEL1 = 5 V; 60 µs
edge of VSENSE_EN RSENSE = 1 kΩ
VSENSE_TC settling VSENSE_EN = 5 V to 0 V;
tDSENSE2L time from rising VSEL0 = 0 V; VSEL1 = 5 V; 20 µs
edge of VSENSE_EN RSENSE = 1 kΩ

MultiSense timings (VCC voltage sensor mode)

VSENSE_VCC settling VSENSE_EN = 0 V to 5 V;

tDSENSE3H time from rising VSEL0 = 5 V; VSEL1 = 5 V; 60 µs
edge of VSENSE_EN RSENSE = 1 kΩ
VSENSE_VCC settling VSENSE_EN = 5 V to 0 V;
tDSENSE3L time from rising VSEL0 = 5 V; VSEL1 = 5 V; 20 µs
edge of VSENSE_EN RSENSE = 1 kΩ
1. Analog sense current drift is deviation of factor K for a given device over (-40°C to 150°C and 9 V < VCC < 18 V) with
respect to its value measured at Tj = 25 °C, VCC = 13 V.
2. Parameter guaranteed by design and characterization; not subject to production test.

Figure 4. TDSTKON

VINPUT

VOUT

VOUT > VOL

MultiSense

TDSTKON GAPGCFT00601

18/44 DS11459 Rev 6

VNHD7008AY Electrical specifications

Figure 5. Definition of the low-side switching times

PWM

t
VGATE_LSA,LSB
80% 80%

tgf_Is
20% 20% tgr_Is t

Figure 6. Definition of the high-side switching times

VINA tD(off)
tD(on)

t
VOUTA

90%

10%

DS11459 Rev 6 19/44

43
Electrical specifications VNHD7008AY

Figure 7. Low-side turn-on delay time

INA

t
INB

PWM

Gate_LSA
tcross

Gate_LSB

t
GAPG3108151219CFT

Figure 8. Input reset time for HSD-fault unlatch

INA

OUTA Reset Pulse

Fault HSA
Fault removing

Multisense Fault cleaning

Vmulti_senseH
Tlatch_RST_HSD
Vsense_nom

GAPG2810151219CFT

Note: Multisense_EN=1

20/44 DS11459 Rev 6

VNHD7008AY Electrical specifications

Figure 9. Input reset time for LSD-fault unlatch

INA

OUTA Reset Pulse

tcross

Fault LSA OutA Short to VCC

Fault removing

Multisense Fault cleaning

Vmulti_senseH

T_Lacht_RST_LSD

GAPG2810151222CFT

Note: Multisense_EN=1

Figure 10. OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL)

INA

Fault : V out> V oL
OUTA

V multi_senseH

Multisense t D_VOL

GAPG2810151228CFT

Note: Multisense_EN=1

DS11459 Rev 6 21/44

43
Electrical specifications VNHD7008AY

Table 12. Operative condition - truth table

INA INB PWM SEL0 SEL1 MultiSense_EN MultiSense HSA LSA HSB LSB

1 0 0 1 High-Z OFF ON OFF ON

0 0
1 1 0 1 High-Z OFF ON OFF ON
0 0 0 1 Current Monitoring HSB OFF OFF ON OFF
0 1
1 0 0 1 Current Monitoring HSB OFF ON ON OFF
0 1 0 1 High-Z OFF OFF ON OFF
0 1
1 1 0 1 High-Z OFF ON ON OFF
0 0 0 1 High-Z ON OFF OFF OFF
1 0
1 0 0 1 High-Z ON OFF OFF ON
0 1 0 1 Current Monitoring HSA ON OFF OFF OFF
1 0
1 1 0 1 Current Monitoring HSA ON OFF OFF ON
0 0 1 Current Monitoring HSB ON OFF ON OFF
1 1 X(1)
1 0 1 Current Monitoring HSA ON OFF ON OFF
0 0 0 1 0 1 Off-state diagnostic OUTA OFF OFF OFF OFF
0 0 0 0 0 1 Off-state diagnostic OUTB OFF OFF OFF OFF
X X X 0 1 1 TCHIP Monitoring — — — —
X X X 1 1 1 VCC Monitoring — — — —
(2)
X X X X X 0 High-Z — — — —
1. X: the level of the pin can be 0 or 1.
2. When INA = INB = PWM = SEL0 = SEL1 = MultiSense_EN = 0 device enters standby after TDSTBY.

Table 13. On-state fault conditions- truth table

Digital input pins(1)
MultiSense Comment
INA INB PWM SEL0

0 0 1 0 VSENSE_H VDS LSB protection triggered; LSB latched off

0 0 1 1 VSENSE_H VDS LSA protection triggered; LSA latched off
0 1 X 0 VSENSE_H HSB protection triggered; HSB latched off
0 1 1 1 VSENSE_H VDS LSA protection triggered; LSA latched off
1 0 1 0 VSENSE_H VDS LSB protection triggered; LSB latched off
1 0 X 1 VSENSE_H HSA protection triggered; HSA latched off
1 1 X 0 VSENSE_H HSB protection triggered; HSB latched off
1 1 X 1 VSENSE_H HSA protection triggered; HSA latched off
1. MultiSense_EN = 1 and SEL1 = 0 are mandatory for fault detection. Other logic combinations on digital input pins not
reported on the above table do not allow to detect a latched-off channel.

22/44 DS11459 Rev 6

VNHD7008AY Electrical specifications

Table 14. Off-state — truth table

MultiSense_EN

MultiSense
OUTB
OUTA
SEL0

SEL1

PWM
INA

INB

Description

Off-state diagnostic

Case 1: OUTA shorted to VCC if no pull-up is applied.

VOUTA > VOL

Case 2: NO open-load in full bridge configuration with

an external pull-up on OUTB
X 1 VSENSEH
Case 3: open-load in half bridge configuration with an
external pull-up on OUTA (motor connected between
1 0 Out and Ground)

Case 1: open-load in full Bridge configuration with an

VOUTA < VOL

external pull-up on OUTB

X 1 Hi-Z Case 2: NO open-load in half Bridge configuration
with external pull-up on OUTA (motor connected
between Out and Ground)
0 0 0
Case 1: OUTB shorted to VCC if no pull-up is applied
VOUTB > VOL

Case 2: NO open-load in full bridge configuration with

external pull-up on OUTA
X 1 VSENSEH
Case 3: open-load in half bridge configuration with
external pull-up on OUTB (motor connected between
0 0 Out and Ground)
Case1: open-load in full Bridge configuration with an
VOUTB < VOL

external pull-up on OUTA

X 1 Hi-Z Case 2. NO open-load in half Bridge configuration
with external pull-up on OUTB (motor connected
between Out and Ground)

Note: To power on the device from standby, it is recommended to: toggle INA or INB or SEL0 or
SEL1 from 0 to 1 first to come out from STBY mode; toggle PWM from 0 to 1 with a delay of
20 microsecond this avoids any overstress on the device in case of existing short-to-battery.

DS11459 Rev 6 23/44

43
Electrical specifications VNHD7008AY

2.4 Waveforms
Figure 11. Normal operative conditions (resistive load)

VINA

VINB

VPWM

VSEL0

VOUTA

VOUTB

ILoad

Vsense

GAPG2909150752CFT

Note: MultiSense_EN=1

24/44 DS11459 Rev 6

VNHD7008AY Electrical specifications

Figure 12. Out shorted to ground and short clearing

Outx Shorted To Gnd + Fault Clearing

VINA
Reset Pulse
OutA Shorted to Gnd Fault Removing
VINB
Reset Pulse
OutB Shorted to Gnd Fault Removing VPWM

VSEL0

VOUTA

VOUTB

Vsense_nom VSenseH
VSENSE

ILoad_nom
ILOAD

GAPG2909150739CFT

Note: MultiSense_EN=1

DS11459 Rev 6 25/44

43
Electrical specifications VNHD7008AY

Figure 13. OUT shorted to Vcc and short clearing

Outx Shorted To Vcc + Fault Clearing

VINA
Reset Pulse

OutA Shorted to Vcc Fault Removing VINB

Reset Pulse

Fault Removing VPWM

OutB Shorted to Vcc

VSEL0

VOUTA

VOUTB

VSenseH VSENSE

ILoad_nom ILOAD

GAPG2909150743CFT

Note: MultiSense_EN=1

Figure 14. Gate driver low side rise time Figure 15. Gate driver low side fall time
normalized vs Cg = 4.7nF normalized vs Cg = 4.7nF
tr GADG271020171146IDL tf GADG271020171151LSG

1 1

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0 0
0 1 2 3 4 Qg(nF) 0 1 2 3 4 Cg (nF)

26/44 DS11459 Rev 6

VNHD7008AY Protections

3 Protections

3.1 Power limitation (high-side driver)

The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing Δ Tj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as soon
as Δ Tj exceeds the safety level of Δ Tj_SD. The protection prevents fast thermal transient
effects and, consequently, reduces thermo-mechanical fatigue. When Power Limitation is
reached, The device enters in latch mode and generates the Fault Flag on Multisense =
VsenseH when the faulty leg diagnostic is selected (please refer to Table 13).

3.2 Thermal shutdown

In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), the device enters in latch mode and generates the Fault Flag on
Multisense = VsenseH (please refer to Table 13). The concerned high side can be switched
ON again as soon as: Tj drops below TTR_HSD, INX is set low for a duration >
TLATCH_RST_HS and set high again.

3.3 High-side current limitation

The device is equipped with an output current limiter in order to protect the silicon as well as
the other components of the system (e.g. bonding wires, wiring harness, connectors, loads,
etc.) from excessive current flow. In case of short circuit, overload or during load power-up,
the output current is clamped to a safety level, ILIMH, by operating the output power
MOSFET in the active region

3.4 External PowerMOS low side VDS monitoring

The VDS_monitoring function has the ability to sense the OUTPUT Mosfet source voltage
and compare it to a predetermined threshold. This threshold is programmable, using an
internal reference current IREF_OVL_LSD = 50 µA (typ.) and an external resistor connected
at VREF_OVL_LS external pin.
This protection will be activated when the low side Power Mos is switched ON and its gate is
fully charged: to guarantee this condition the function will detect a short to battery event only
when PWM = H and after a blanking time tfil_OVL_LS= 2.2 µs (typ.) starting from PWM
rising edge. This feature is present for each LSD leg.
In case of fault conditions caused by Power Limitation or overtemperature or open
load/short to VCC in OFF state, the fault is indicated by the MultiSense pin being internally
switched to a "current limited" voltage source pulled to level VSENSEH.

DS11459 Rev 6 27/44

43
Typical application schematic VNHD7008AY

4 Typical application schematic

Figure 16. Typical application schematic

VBAT

4.7K
VBAT CP Vcc
1k PWM 100nF

470μF
1k INB
1k INA

μC
Open load in off
1k SEL0 stete detection
OUTA OUTB circuity
1k SEL1
1k MS_EN GATE_LSA
GATE_LSB

Source_LSA Source_LSB
10k MS
Vref_OVL_LSA Vref_OVL_LSB
1.5K

33nF
VREG
10K
10K

100nF

Note: To protect the device against Battery disconnection with energized inductive load when the
bridge driver goes into 3-state, suggested C(Vcc) is:

Emotor
c  V cc  = ---------------------------------------2-
0.5DVcc,max

where:
Emotor = 33.5 mJ;
DVcc,max = Vcc_AMR - Vcc_max;
Vcc_AMR = 38 V;
Vcc_max = 26 V (Vcc at jump start);

C(Vcc) = 470 µF

28/44 DS11459 Rev 6

VNHD7008AY MultiSense operation

5 MultiSense operation

5.1 MultiSense analog monitoring

Diagnostic information on device and load status are provided by an analog output pin
(MultiSense) delivering the following signals:
 Current monitor: current mirror of HSDx output current
 VCC monitor: voltage propotional to VCC
 TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in Table 12.

Figure 17. MultiSense block diagram

Vcc

INPUT

Sense MOS Main MOS

OUT
Current sense

Vbat Monitor

Temperature monitor Multisense Switch Block

Fault

MULTISENSE

To uC ADC

RPROT
RSENSE

GAPGCFT01040

5.2 Multisense diagnostics flag in fault conditions

Multisense pin delivers fixed voltage (VSENSEH) with a certain current capability in case of:
 fault condition on activated high-side triggered by Power Limitation
 fault condition on activated high-side triggered by overtemperature protection
 fault condition on VDS of Low side exceeded threshold

DS11459 Rev 6 29/44

43
VREG and Driver_LS Block VNHD7008AY

6 VREG and Driver_LS Block

VREG pin is the output of an internal low drop voltage regulator. VREG block is designed to
power the driver of external power Mosfet (Driver_LS) and it allows a proper MOS transition.
 VREG out voltage will be VREG=10V if Vbattery > 10V, while VREG = Vbattery if
Vbattery < 10V.
An external capacitor CREG = 100 nF connected to the pin VREG is needed to proper
polarize the circuit (see Figure 16).

7 Reverse battery protection

CP pin provides the necessary gate drive for an external n-channel PowerMOS used for
reverse polarity protection. The external N-channel Power MOSFET used for the reverse
battery protection should have the following characteristics:
 BVdss > 20 V (for a reverse battery of -16 V);
 RDS(on) < 1/3 of H-bridge total RDS(on)
 Standard Logic Gate Driving

8 Open-load detection in off-state

The Open Load (OL) detection in off-state operates when output is deactivated (means INA
= INB = PWM=0, or INB together with PWM=0). Open load detection is performed by
reading the MultiSense output. External (switched) pull-up resistor has to be used and
dimensioned to pull output voltage above the maximum open load detection voltage (VOL
MAX) when load is not connected and as well stays below the minimum level (VOL MIN)
when load is connected.
When the open load is detected, VsenseH is indicated on Multisense pin, possible
conditions are specified in Table 14.
If pull up resistor is applied over switched circuitry, it allows to detect short to VCC from
open-load (see Figure 16).
The RPU value has to be:

V BATTmin – V OLmax
R pull_up  -----------------------------------------------------------
2  I L(off2)min [@VOLmax]

30/44 DS11459 Rev 6

VNHD7008AY Immunity against transient electrical disturbances

9 Immunity against transient electrical disturbances

The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 15.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device
only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: "The function does not perform as designed during the test but returns automatically
to normal operation after the test".

Table 15. IISO 7637-2 - electrical transient conduction along supply line
Test pulse severity level Pulse duration
Test pulse Minimum Burst cycle/pulse
with status II functional and pulse
2011(E) number of repetition time
performance status generator
pulses or
internal
test time
Level US(1) min. max. impedance

1 III -112 V 500 pulses 0.5 s 2 ms, 10 Ω

2a III +55 500 pulses 0.2 s 5s 50 µs, 2 Ω
3a IV -220 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b IV +150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
(2)
4 IV -7 V 1 pulse 100 ms, 0.01 Ω

Load dump according to ISO 16750-2:2010

Test B(3) 40 V 5 pulse 1 min 400 ms, 2 Ω

1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E)
2. Test pulse from ISO 7637-2:2004(E)
3. With 40 V external suppressor referred to ground (-40 °C < TJ < 150 °C)

DS11459 Rev 6 31/44

43
Package and PCB thermal data VNHD7008AY

10 Package and PCB thermal data

10.1 PowerSSO-36 thermal data

Figure 18. PowerSSO-36 PCB board

32/44 DS11459 Rev 6

VNHD7008AY Package and PCB thermal data

Table 16. PCB properties

Dimension Value

Board finish thickness 1.6 mm +/- 10%

Board dimension 129 mm x 86 mm
Board material FR4
Cu thickness (outer layers) 0.070 mm
Cu thickness (inner layers) 0.035 mm
Thermal via separation 1.2 mm
Thermal via diameter 0.3 mm +/- 0.08 mm
Cu thickness on vias 0.025 mm
Footprint dimension 4.1 mm x 6.5 mm

Figure 19. Rthj-amb vs PCB copper area in open box free air condition

Equation 1: pulse calculation formula

ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T

DS11459 Rev 6 33/44

43
Package and PCB thermal data VNHD7008AY

Figure 20. Thermal fitting model of a double-channel HSD in PowerSSO-36

GAPGCFT00325

Note: The fitting model is a simplified thermal tool and is valid for transient evolutions where the
embedded protections (power limitation or thermal cycling during thermal shutdown) are not
triggered.

Figure 21. Thermal impedance junction ambient single pulse

Table 17. Thermal parameters

Area / island FP 2 8 4L

R1 (°C/W) 0.75
R2 (°C/W) 1
R3 (°C/W) 2 2 2 1
R4 (°C/W) 7 6 6 4
R5 (°C/W) 20 14 10 2

34/44 DS11459 Rev 6

VNHD7008AY Package and PCB thermal data

Table 17. Thermal parameters (continued)

Area / island FP 2 8 4L

R6 (°C/W) 30 26 15 7
R7 (°C/W) 0.75
R8 (°C/W) 1
C1 (W•s/°C) 0.0027
C2 (W•s/°C) 0.006
C3 (W•s/°C) 0.05 0.05 0.05 0.05
C4 (W•s/°C) 0.15 0.2 0.2 0.2
C5 (W•s/°C) 1 2 3 10
C6 (W•s/°C) 3 5 9 18
C7 (W•s/°C) 0.0027
C8 (W•s/°C) 0.006

DS11459 Rev 6 35/44

43
Package and packing information VNHD7008AY

11 Package and packing information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

11.1 PowerSSO-36 package information

Figure 22. PowerSSO-36 package dimensions
BOTTOM VIEW TOP VIEW

SECTION A-A SECTION B-B

GAPG2508150825CFT

Table 18. PowerSSO-36 (exposed pad) package mechanical data

Millimeters
Ref
Min. Typ. Max.

Ө 0° - 8°
Ө1 5° - 10°
Ө2 0° - -

36/44 DS11459 Rev 6

VNHD7008AY Package and packing information

Table 18. PowerSSO-36 (exposed pad) package mechanical data (continued)

Millimeters
Ref
Min. Typ. Max.

A 2.15 - 2.45
A1 0.0 - 0.1
A2 2.15 - 2.35
b 0.18 - 0.32
b1 0.13 0.25 0.3
c 0.23 - 0.32
c1 0.2 0.2 0.3
(1)
D 10.30 BSC
D1 6.9 - 7.5
D2 - 3.65 -
D3 - 4.3 -
e 0.50 BSC
E 10.30 BSC
(1)
E1 7.50 BSC
E2 4.3 - 5.2
E3 - 2.3 -
E4 - 2.9 -
G1 - 1.2 -
G2 - 1 -
G3 - 0.8 -
h 0.3 - 0.4
L 0.55 0.7 0.85
L1 1.40 REF
L2 0.25 BSC
N 36
R 0.3 - -
R1 0.2 - -
S 0.25 - -
Tolerance of form and position
aaa 0.2
bbb 0.2
ccc 0.1
ddd 0.2

DS11459 Rev 6 37/44

43
Package and packing information VNHD7008AY

Table 18. PowerSSO-36 (exposed pad) package mechanical data (continued)

Millimeters
Ref
Min. Typ. Max.

eee 0.1
ffff 0.2
ggg 0.15
1. Dimensions D and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is ‘0.25
mm’ per side D and ‘0.15 mm’ per side E1. D and E1 are Maximum plastic body size dimensions including
mold mismatch.

11.2 PowerSSO-36 packing information

Figure 23. PowerSSO-36 tube shipment (no suffix)

Base Qty 49
Bulk Qty 1225
Tube length (±0.5) 532
C
B A 3.5
B 13.8
C (±0.1) 0.6

All dimensions are in mm.

38/44 DS11459 Rev 6

VNHD7008AY Package and packing information

Figure 24. PowerSSO-36 tape and reel shipment (suffix “TR”)

Reel dimensions

Base Qty 1000

Bulk Qty 1000
A (max) 330
B (min) 1.5
C (±0.2) 13
F 20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4

Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 24
Tape Hole Spacing P0 (±0.1) 4
Component Spacing P 12
Hole Diameter D (±0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (±0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (±0.1) 2 End

All dimensions are in mm.

Start
Top No components Components No components
cover
tape 500mm min 500mm min
Empty components pockets
sealed with cover tape.

User direction of feed

DS11459 Rev 6 39/44

43
Package and packing information VNHD7008AY

11.3 PowerSSO-36 marking information

Figure 25. PowerSSO-36 marking information

Marking area
1 2 3 4 5 6 7 8 9

Special function digit

&: Engineering sample
<blank>: Commercial sample

PowerSSO-36 TOP VIEW

(not in scale)
GAPG1604151446CFT

Note: Engineering Samples: these samples can be clearly identified by a dedicated special
symbol in the marking of each unit. These samples are intended to be used for electrical
compatibility evaluation only; usage for any other purpose may be agreed only upon written
authorization by ST. ST is not liable for any customer usage in production and/or in reliability
qualification trials.
Note: Commercial Samples: fully qualified parts from ST standard production with no usage
restrictions.

40/44 DS11459 Rev 6

VNHD7008AY Order codes

12 Order codes

Table 19. Device summary

Order codes
Package
Tube Tape and reel
PowerSSO-36 VNHD7008AY VNHD7008AYTR

DS11459 Rev 6 41/44

43
Revision history VNHD7008AY

13 Revision history

Table 20. Document revision history

Date Revision Description of changes

11-Feb-2016 1 Initial release.

Updated table in Section: Features.
Updated values in Table 3: Absolute maximum ratings and added
note.
Updated Max. value in Table 4: Thermal data.
Updated Table 5: Power section.
Updated Table 8: Low-side driver parameters (VCC = 13 V).
Updated Table 9: Protections and diagnostics (7 V < VCC < 18 V; -
40 °C < Tj < 150 °C).
14-Jul-2017 2
Updated Table 10: MultiSense (7 V < VCC < 18 V; -
40 °C < Tj < 150 °C).
Added Figure 6: Input reset time for HSD-fault unlatch.
Added Section 3: Protections Section 4: Typical application schematic
Section 5: MultiSense operation, Section 6: Reverse battery
protection, Section 7: Open-load detection in off-state, Section 8:
Immunity against transient electrical disturbances, Section 9: Package
and PCB thermal data.
Updated Figure 1, Table 2: Pin definitions and functions.
Added Table 3: Suggested connection for unused and not connected
pins.
Updated Table 4: Absolute maximum ratings, Table 6: Power section,
Table 9: Gate driver for external MOS parameters (VCC = 13 V),
Table 10: Protections and diagnostics (7 V < VCC < 18 V; -
40 °C < Tj < 150 °C), Table 11: MultiSense (7 V < VCC < 18 V; -
40 °C < Tj < 150 °C).
03-Nov-2017 3 Added Figure 5: Definition of the low-side switching times and
Figure 6: Definition of the high-side switching times.
Updated Table 13: On-state fault conditions- truth table.
Added Figure 14: Gate driver low side rise time normalized vs Cg =
4.7nF and Figure 15: Gate driver low side fall time normalized vs Cg =
4.7nF, Section 5.2: Multisense diagnostics flag in fault conditions and
Section 6: VREG and Driver_LS Block, Figure 21: Thermal impedance
junction ambient single pulse and Table 17: Thermal parameters.
Minor text changes.
Document status promoted from target to production data.
11-Dec-2017 4 Updated features in cover page.
Minor text changes.

42/44 DS11459 Rev 6

VNHD7008AY Revision history

Table 20. Document revision history (continued)

Date Revision Description of changes

29-Jan-2018 5 Typo error.

Updated Table 4: Absolute maximum ratings (add VBAT and VCP
values).
Updated Table 10: Protections and diagnostics (7 V < VCC < 18 V; -
40 °C < Tj < 150 °C) (changed Min. value in tDEL_OVL_LSD; added Min.
01-Apr-2020 6 and Max. value in VGS_CP ).
Updated Figure 19: Rthj-amb vs PCB copper area in open box free air
condition.
Updated Figure 21: Thermal impedance junction ambient single pulse.
Updated Table 17: Thermal parameters.

DS11459 Rev 6 43/44

43
 VNHD7008AY

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2020 STMicroelectronics – All rights reserved

44/44 DS11459 Rev 6