Low Power Wireless Sensor Networks

http://www-mtl.mit.edu/research/icsystems/uamps

Rex Min, Manish Bhardwaj, Seong-Hwan Cho, Eugene Shih,

Amit Sinha, Alice Wang, Anantha Chandrakasan

Massachusetts Institute of Technology

 Emerging Networked Applications

Integrated PDAs Home/Office Networking

(e.g., Bluetooth)

Sensor Networks
Equipment Monitoring

Medical Monitoring

Integrated system-on-a -chip to sense, process and

collaborate
 The MIT µAMPS Project

µ-OS (Power Aware Control)

Battery/DC-DC Conversion

Sensor RF
StrongARM Remote Basestation
& A/D Tx/Rx

n A universal substrate for power aware data gathering

from a massively distributed wireless network
 System Requirements

n Sensor Types: Low Rate

(e.g., acoustic and seismic)
n Bandwidth: bits/sec to kbits/sec
n Transmission Distance: 5-10m
(< 100m)
n Spatial Density
o 0.1 nodes/m2 to 20 nodes/m2
n Node Requirements
n Small Form Factor
n Required Lifetime: > year
n Operational Diversity:
...from network roles ...from the environment ...from user demands
o Sensor o Event arrival o Tolerable latency
o Relay rate/type o Result SNR
o Data aggregator o Ambient noise o Pr(Detection)
o Signal statistics
 Integrated Sensor-Node-on-a-Chip

MULTIPLE
MICRO MEMORY
OUTPUT
BATTERY
DC-DC

µ-PROC
MEMS A/D & RF
DSP

n Integration is the key enabler for massively distributed

wireless sensing

What is the best computation/communication fabric?

How coupled should protocol design be to the fabric?
 Power Awareness

Energy Esystem
di
−1
 ∑ Esystemi d i 
 Scenarios 
η PA = 
Eperfect  ∑ E perfecti d i 
 Scenarios 

Scenario

n Diversity in operating scenarios: number and type of events, signal

statistics, desired quality, latency, etc.
n Cannot achieve Esystem = Eperfect at all points
o Optimize at important scenarios (Esystemi di is high)
 Power Aware Node Architecture

Capacity
variations Battery
Protocols Desired result
quality variations
Efficiency DC-DC Algorithms
variations Conversion Available energy
µOS Voltage
Power scheduling

RAM ROM
Acoustic
Sensor

A/D SA-1100 Radio

Seismic
Sensor

Standby current Leakage current Bias current

Low duty cycle Workload variation Start-up time

n Graceful energy scalability across a diversity of

operating conditions and energy-quality trade-offs
 OS Directed Power Management

Sensor Node 1200

1000
s0 Deeper sleep
µ-OS Lower power
800 More overhead
Sensor

Radio
A/D StrongARM

Power (mW)
600
Memory s1
400
s2
200
Battery and DC/DC converter s3
0 s4
-200
-10 0 10 20 30 40 50 60
ARM Memory Sensor Radio Transition Latency (ms)

s0 active active on tx, rx

s1 idle sleep on rx
• OS must decide suitable transition
s2 sleep sleep on rx
policy based on observed history
s3 sleep sleep on off

s4 sleep sleep off off

 Idle Mode Leakage Power

( −VT / S )
I leakage ∝ 10
n Leakage dominates switching energy for low duty cycles
n A major concern for event-driven operation (PDAs,
sensors, etc.)
 Leakage and Switching Power

90 90 56%
Leakage 0.13 µ, 15mm die, 1V Leakage 0.1µ, 15mm die, 0.7V
80 80 49%
Active Active
70
Power (Watts)

70

Power (Watts)
41%
60 60 33%
26% 26%
20% 19%
50 8% 11% 15% 50 14%
1% 2% 3% 5% 6% 9%
40 40
30 30
20 20
10 10
30

50

80
40

60
70

90

40

70

90
0

30

50

60

80

0
0
10
11

11
10
Temp (C) Temp (C)

Courtesy of Vivek De (Intel)

Need to Develop Techniques for Leakage Control

 Low Duty Cycle Radio
10000
20mW Electronics Power
1mW Transmit power @ 1Mbps

Energy Per Bit (nJ)

1000

100

10
10 100 1000 10000 100000
Packet size (bits)

n Start-up time dominates the energy for small packet sizes

n Innovative radio design required…

Startup Costs are Fundamental –

Latency not just a function of user requirement
 DVS on SA-1100

MIT DVS PCB

SA-1100 requests a voltage
appropriate for its clock frequency

1.6V Voltage request, 0.9 - 1.6 V

limiter StrongARM
5V 5
5 Evalualtion
Board

Vout SA-1100
Controller
Power

Control

µOS

µOS selects appropriate clock

Digitally adjustable DC-DC frequency based on workload
converter powers SA-1100 core and latency constraints
 Software Voltage Scheduling

Data from StrongARM-1100

CPU Core Power, 0.9-1.6 Volts
StrongArm
SA-1100

DC-DC Regulator
Controller
MOSFET control

Buck Regulator

n Operating system predicts and schedules the voltage

n Adapt power supply to deliver “just enough performance”
 DVS Demonstration

o User adjusts number of filter taps

o Frequency/Voltage adjusted appropriately (via eCOS based µOS)

Frequency /
Voltage

Workload
(filter taps)
 Computation vs. Communication
1E-03
1E-04
Energy for Electronics + Transmit
1E-05

Energy (J)
1E-06
1E-07
1E-08
R2 Propagation Loss
1E-09 Limit (no electronics)
Assuming 10pJ/bit/m2
1E-10
1E-11
1 10 100 1000 10000
Distance (m)

n Computation: 1nJ/op (µ-Processor) and Communication (@10m): 150nJ/bit

n @10 m: ~150 instructions/transmitted bit on a low-power processor
n @10m: > 1Million instructions/transmitted bit using dedicated hardware

Compute, Don’t Communicate

 Protocol Architectures

Source Destination Multi-hop Routing Example

(ignoring electronics)
• 1 hop over 100 m: 100nJ/bit
• 10 hops of 10 m:
Router 10 × 1 nJ/bit = 10nJ/bit

n Particular attention must be placed on multiple access

schemes
n Scheduled vs. Reactive routing (synchronous vs.
asynchronous)

Similar Trade-off to On-chip Interconnect

 Distributed DSP using DVS

A/D A/D FFT

A/D FFT
A/D Sensor 1 Sensor 1
Sensor 2 Sensor 2

Cluster Head
Cluster Head

FFT BF LOB A/D FFT BF LOB

A/D
Sensor 6 Sensor 7 Sensor 6 Sensor 7

n Approach 1 : All n Approach 2 :FFT is done at

computation is done at C-H node and transmitted to C-H
Parallelizing the FFT means we can reduce
Ecomp(Vdd=1.5V) = 7 * Efft +Ebf + ELOB the supply voltage and frequency
= 27.27 mJ Ecomp(variable Vdd) = 15.16 mJ
FFT is operated at .9 V
BF & LOB is operated at 1.3 V
 Energy Efficient Link Layer

Energy
2500

Energy per bit (nJ)

2000

1500
Encode
Decode
1000

500

0
(31,11,5)
(31,16,3)
(63,7,15)

(63,24,7)
(63,39,4)
(63,45,3)
(15,7,2)
(31,6,7)

§ Energy scalability through variation of error-correction (63,16,11)

scheme
§ Computation-communication tradeoff between coding and
Tx power for BER reduction
 Energy Scavenging

VDD
Load
Generator Regulator
Electronics

n Self-powered operation is a real option if the power

dissipation can be scaled to 10’s - 100’s of µW
o Mechanicalvibration (e.g., machine-mounted sensors)
o Electromagnetic fields (RF)

n A major opportunity exists in developing energy scavengers

(generator and associated electronics) for extracting useful
energy from ambient sources
 Energy Scavenging

MEMS Power PicoJoule

Generator Controller DSP

[Amirthrajah00]
n Scavenge energy from mechanical vibrations to power
micropower sensor systems
n Power delivered ~ 10µW
Hardwired Fabrics enable No Power Signal Processing
 Node Prototype

sensor/processor board radio baseband

n Version 1 prototype with COTS components

n Future nodes will feature custom chipsets
 Node and Network API

n Enable and encourage end -user to operate network in a

power-aware manner
o Sufficient abstraction to hide complexity of distributed wireless
network
o Get-optimize-set paradigm to maintain network state

n Functional interface, object abstractions, and behavioral

semantics
o Gather and set state of nodes, links, network
o Facilitate data exchange between node and basestation
o Realize a user’s desired operating point for the network
o Visualize network state
o Built-in and customizable energy models for energy, delay, etc.
 Summary

n Just-in-Time computing through supply optimization

minimizes energy dissipation
n Leakage is a first order issue – active leakage
management at the architecture, circuit, and device
levels are critical
n Focus must shift from computation to communication-
centric design
n Protocols must be fabric and domain aware
o Energy
per operation (mW/MIPS) will scale with technology
o Communication costs (nJ/bit) will not scale at the same rate

Low Energy Sensor Design Requires a System-level

Approach – Tight Coupling Between Fabrics,
Algorithms and Protocols