Analog Integrated Circuits and Signal Processing, 34, 7–16, 2003


C 2003 Kluwer Academic Publishers. Manufactured in The Netherlands.

Models and Implementation of a Dynamic Element Matching DAC

NIKLAS U. ANDERSSON,1 K. OLA ANDERSSON,2 MARK VESTERBACKA3

AND J. JACOB WIKNER4
1
Linköping Design Center, Ericsson Microelectronics AB, Box 1544, SE-581 15, Department of Electrical Engineering, Linköping University,
SE-581 83 Linköping, Sweden Tel.: +46 13 32 25 25, Fax: +46 13 139282
2
Department of Electrical Engineering, Linköping University, SE-581 83 Linköping, Sweden Tel.: +46 13 286698, Fax: +46 13 139282
3
Department of Electrical Engineering, Linköping University, SE-581 83 Linköping, Sweden Tel.: +46 13 281676, Fax: +46 13 139282
4
Swindon Design Centre, Ericsson Microelectronics, Westmead Dr., Swindon SN5 7UN, United Kingdom Tel.: +44 1793 494582
E-mail: niklasa@isy.liu.se; olaa@isy.liu.se; markv@isy.liu.se; Jacob.J.Wikner@mic.ericsson.se

Abstract. The dynamic element matching (DEM) techniques for digital-to-analog converters (DACs) has been
suggested as a promising method to improve matching between the DAC’s reference levels. However, no work
has so far taken the dynamic effects that limit the performance for higher frequencies into account. In this pa-
per we present a model describing the dynamic properties of a DEM DAC and compare the simulated results
with measurements of a 14-bit current-steering DEM DAC implemented in a 0.35-µm CMOS process. The mea-
sured data agrees well with the results predicted by the used model. It is also shown that the DEM technique
does not necessarily increase the performance of a DAC when dynamic errors are dominating the achievable
performance.

Key Words: DAC, DEM, CMOS, matching, current-steering

1. Introduction modifies the distortion terms, hence signal-dependent

errors, to become minimized or to become signal-
Design of high-resolution, wideband digital-to-analog independent noise.
converters (DACs) is hard, since highly linear compo- In this work we show how dynamic errors, deter-
nents, i.e., good device matching, as well as high-speed mined by, e.g., signal-dependent impedance limit the
building blocks are required. Mismatch between the performance at higher frequencies which leads to the
DAC’s reference levels introduces significant noise and conclusion that only a limited amount of DEM is re-
distortion to the output, setting the achievable spurious- quired in order to reach a certain performance. This
free dynamic range (SFDR) of the converter—at least allows us to reduce the design overhead and circuit
for low frequencies. The influence of device mismatch, complexity. With reduced digital circuitry we also re-
arising from process irregularities [1] and parasitic duce the switching noise.
components, can however be decreased using either Related to this work we have implemented a 14-bit
static or dynamic methods. current-steering DEM DAC in a 0.35-µm CMOS pro-
Static element matching techniques, e.g., special cess. The converter has dual unbuffered outputs and the
layout techniques, and distributed biasing [2], will not currents are terminated over a pair of 50 Ohm resistors.
compensate for matching errors occurring after pro- Since the DAC in this configuration does neither have a
cessing, e.g., aging and temperature variations. Dy- 0-ohm termination nor an infinite output resistance, the
namic methods on the other hand is used during oper- impedance and bandwidth of the current sources will
ation and are continuously compensating for matching dominate the limiting factor on linearity [8]. From the
errors by manipulating the input signal or the circuit simulation results we are able to identify the required
elements using digital signal processing. These tech- complexity of the DEM circuit. They also show us the
niques are commonly referred to as dynamic element typical limitations due to the output impedance prob-
matching (DEM) [3–7] techniques. DEM techniques lem. The measurement results are also compared with
8 Andersson et al.

simulated results from a dynamic model implemented neglect the offset A0 and the gain factor w 0 in the
in Matlab using a state-space description of the DAC. following)
We find a good correlation between simulated and mea-
sured results. 
M

In Section 2 we give a background to DACs Ãout (nT ) = bm (nT ) · w m · (1 + δw m )

and how mismatch in the DAC’s references affects the m=1

performance. In Section 3 we present a model describ- 

M

ing the dynamic properties of a current-steering DAC, = Aout (nT ) + bm (nT ) · w m · δw m

that is used in the simulations found in Section 4.2. In m=1

Section 4, we describe the most common randomiza- = Aout (nT ) + E out (nT ) (2)
tion DEM approaches. The test chip implementation
is discussed in Section 5 and in Section 6 we com- This output contains the wanted signal, Aout (nT ), but
pare measured results from the test chip with the sim- also a signal-dependent error, E out (nT ), which intro-
ulation results of the model. In Section 7 the work is duces distortion. The errors, δw m , must be small enough
concluded. to suppress the distortion terms below the specified
limits. As stated, expressions (1) and (2) only give the
static, memory-less behavior of the converter. There are
also dynamic errors originating from several sources.
2. Digital-to-Analog Converters
Typically, we have the influence of the limited out-
put impedance of the converter, glitches due to tim-
Considering the static, memory-less case, i.e., the sam-
ing mismatch between switching signals, and signal-
ple period is much larger than the time constant of the
dependent settling errors. The matching errors between
DAC, an M-bit digital-to-analog converter (DAC) will
the weights can be signal-dependent due to capacitive
in general perform the following operation
coupling, etc. These errors are much more difficult to
analyze and eliminate than the static matching errors.

M
One first-order dynamic DAC model is presented in the
Aout (nT ) = A0 + w 0 bm (nT ) · w m (1)
next section. This DAC model is used when simulat-
m=1
ing and comparing the performance of different DEM
where Aout (nT ) is the settled output amplitude (current structures.
or voltage) at the time instants nT , A0 is an offset am-
plitude, w 0 is a gain factor, bm (nT ) are the bits in the
input word, and w m are the DAC weights. bm is referred 3. Model of Dynamic Properties
to as the most significant bit (MSB) and b1 is the least in Current-Steering DACs
significant bit (LSB). For an input described by a bi-
nary offset code, we have M = N and w m = 2m−1 . For a DEM is useful for limiting the influence of transis-
thermometer-coded input, we would have M = 2 N − 1 tor mismatch, which causes a typical static error. For
and w m = 1. higher frequencies, dynamic errors tend to be the lim-
The current-steering DAC architecture [8–11] is a iting factor on the linearity. One source of dynamic
good candidate for high-speed and high-resolution ap- errors is the limited output impedance of the current
plications. In the current-steering DAC, the weights sources [8,11–13], where especially the capacitive part
will be constructed by using a number of weighted cur- degrades the high frequency performance. In this sec-
rent sources, as illustrated in Fig. 1(a), forming the w m . tion we present a Matlab model of this phenomenon
The switches, determining which current sources that which can be used for cosimulation with models of
are connected to the output, are controlled by the input matching errors in DEM DACs. This model was first
bits, bm . Implementation issues for this architecture is presented in [12].
further discussed in Section 5. A circuit-level description of the model is shown
Unfortunately, due to mismatch, the actual DAC in Fig. 1(b). The nonideal current sources include the
weights is given by w m · (1 + δw m ), where δw m is the finite output impedance. The switches are modeled as
relative error of the weight w m . Then equation (1) resistors, and a lumped RC-model is used for the output
will give the true, or actual, static output (we will wire and resistive load.
 Models and Implementation of a Dynamic Element Matching DAC 9

Fig. 1. Circuit schematic of (a) a binary-weighted, current-steering DAC, (b) the corresponding dynamic DAC model, and (c) model of one
output during an update period for a certain input.

In Fig. 1(c) we show the configuration for one output be written on a state space form
terminal during an update period for a certain value of
the input signal. In this case the output impedances V̇(t) = Ẋ(t) = A · X(t) + B · u(t) (3)
of the current sources are connected to ground instead
V(t) = X(t) + V(0− ) (4)
of the power supply rail. It is evident that the represen-
tations in Fig. 1(b) and (c) are equivalent if the nominal
where
current, I , is replaced with a current I˜ = I + VDD /Rout ,
where VDD is the supply voltage and Rout is the output
V(t) = [V1 (t), V2 (t), . . . , VK (t), V (t)]T (5)
resistance of the current source. The system of differ-
−
ential equations representing the circuit in Fig. 1(c) can X(t) = V(t) − V(0 ) (6)
10 Andersson et al.

  
1 1 1 1 1
 R1 + Rs1 C1
0 ··· 0
Rs1 C1 
 
   
 1 1 1 1 1 
 0 + ··· 0 
 
 R2 Rs2 C2 Rs2 C2 
 
 ··· ··· ··· ··· ··· 
 
A=  (7)
   
 1 1 1 1 1 
 0 0 ··· + 
 
 RK Rs K CK Rs K C K 
   
 
 1  1  1
K
 1 1 1 1 1 1 
··· − +
Rs1 C Rs2 C Rs K C R j=1 Rs j C

and This structure has the advantage that by using 1-bit

 T DACs a perfect linear performance can be achieved
I1 I2 IK
B = A · V(0− ) + , ,..., ,0 (8) [3]. However this approach is not suitable for high res-
C1 C2 CK olution DACs due to the large hardware complexity,
u(t) is a unit step and V(0− ) is the initial value of the so trade-offs usually have to be made. One straight-
vector V(t). forward approach is to apply the DEM technique in
A new state-space system is created for each update Fig. 2 to a number of the most significant bits (MSBs)
period, and the output voltage at the end of the period, only and keep the least significant bits (LSBs) binary
V (t), is used as the sampled output data from the DAC. weighted. Another approach proposed in [5] is the par-
The model allows simple integration with other mod- tial randomization DEM (PRDEM) technique which
els of mismatch for inclusion of dynamic errors in the is overviewed in the next section. Although not treated
DEM simulations. in this paper it is worth noticing that DEM spoils the
good glitch performance achieved by using thermome-
ter code [8,11], where even a DC input may result in
4. Dynamic Element Matching Techniques glitches. A DEM technique that retains the low glitch
property of the thermometer code with randomization
The DEM techniques [3–7] have shown significant re- is the restricted DEM (RSDEM) technique [6,7].
sults on improving linearity in DACs. A high-level
topology of DEM for D/A conversion is shown in Fig. 2.
The N -bit binary input word is transformed into an 4.1. Partial Randomization DEM (PRDEM)
M = 2 N − 1 bit thermometer word, and then the bits
are scrambled before entering the 1-bit DACs. The out- A generalized partial randomization DEM (PRDEM)
puts of the 1-bit DACs are summed forming the output. architecture [5] is shown in Fig. 3(a). It utilizes a binary

Fig. 2. Schematic of a general DEM structure.

 Models and Implementation of a Dynamic Element Matching DAC 11

Fig. 3. (a) A general PRDEM structure and schematics of a (b) binary switching block, and (c) (R-1)/1 bit DAC bank.

switching tree containing switching blocks, Sk,r , where when ck [n] = 1, the MSB, xk , of the input is copied
k denotes the layer and r the position of the switching k times and mapped to the top output, while the re-
block in the layer. The switching block in Fig. 3(b) has maining k bits of the input are mapped directly to the
one (k + 1)-bit input and two k-bit outputs, as well as a k bits of the bottom output. For ck [n] = 0 the situation
random control bit ck [n] equal for all blocks Sk,r in the is reversed.
kth layer. Every ck [n] is a random or pseudo random In PRDEM we introduce switching in a limited num-
bit-sequence (PRBS) uncorrelated with the control bits ber of layers, i.e., in layers b through R (Fig. 3(a)),
used in all other layers. Sk,r has the following function: where 2 ≤ R ≤ b. Since no randomness is introduced
12 Andersson et al.

in layers 1 through R − 1 we can simply substitute

these layers by N = 2b−R+1 nominally identical DAC
banks—each with an R-bit input (Fig. 3(c)). The LSB
of the input controls a unit DAC element, whereas the
remaining R − 1 bits control an (R − 1)-bit conven-
tional DAC.
A tree with switching in all layers, i.e., layer 1
through b, and hereby is terminated by a set of
1-bit DACs, is referred to as a full randomization DEM
(FRDEM) system. This system will in theory achieve
ideal SFDR performance, but it suffers from a large
hardware cost [4].

4.2. Simulation of Partial Randomization DEM

In the simulations, a Gaussian distributed error current

with a standard deviation of approximately 10% has
been added to each unit current source. This is a rather
large value, but it includes all static errors in the DAC,
e.g., mismatch between current sources, mismatch in
biasing, gain errors between the DAC banks, etc. The
input is a full-scale single-tone sinusoid with a sam-
pling frequency of f samp = 10 MHz and a single-ended
output is terminated over 50 . Values of the circuit pa-
rameters used in the simulations are given in Table 1.
In Fig. 4(a) we show the simulated output without
randomization. We find that the SFDR (∼60 dB) is limi-
ted by the third harmonic. When introducing switching
in the first layer (Fig. 4(b)) the SFDR is increased to
68 dB, a gain of ∼8 dB corresponding to about one

Table 1. DAC model parameters.

DAC Model Parameters Value

Unit current 1.22 µA

Output resistance (unit current source) 1 G
Output capacitance (unit current source) 10 fF
Switch resistance 200
Load resistance 50
Load capacitance 100 pF

Table 2. Chip parameters.

Chip Parameters Value

Process 0.35-µm CMOS

No. of input bits 14
Fig. 4. Simulated spectra, 10 MHz sampling frequency, (a) without
Area (core) 5 mm2
randomization, with (b) a single-layer switching, and (c) four-layer
No. of transistors ∼78 000
switching.
 Models and Implementation of a Dynamic Element Matching DAC 13

bit in performance, to the cost of a somewhat higher

noise floor. The SFDR is now limited by the second
harmonic. When introducing switching in all four lay-
ers (Fig. 4(c)) we can see some smaller differences
compared to Fig. 4(b), but the SFDR remains the same.
Hence, we do not gain any SFDR performance by hav-
ing more than one switching layer. This can be ex-
plained by observing the second harmonic in the spec-
tra shown in Fig. 4. The second harmonic is almost
unaffected by the randomization, i.e., it arises from
dynamic errors in the DAC and as soon as the third
harmonic, arising from mismatch, is suppressed below
the second harmonic we do not gain in SFDR perfor-
mance by using DEM [8]. We also notice that since
distortion is transformed into noise the overall SNDR
performance is unaffected by DEM, to gain in SNDR
performance oversampling has to be used.

5. Implementation of a PRDEM DAC

It has been shown [5] that the partial randomization

DEM (PRDEM), i.e., switching in a few layers only,
yields the same SFDR performance as the full random-
ization DEM (FRDEM), i.e., switching in all layers,
but at a significantly lower hardware cost. However
none of these investigations take the dynamic effects
in the DAC into account. Therefore it is of large in-
terest to see how well an implemented PRDEM struc-
ture corresponds to simulations of the dynamic DAC
model where also the PRDEM techniques have been
Fig. 5. (a) Floorplan and (b) chip photo of a 4 layer PRDEM chip.
included.
We have chosen to implement a PRDEM structure
using a 4-layer binary switching tree terminated by 16
10/1 DAC-banks (consisting of a 10-bit DAC and a in parallel. Each unit current source has been imple-
1-bit DAC). A block view of the test chip is shown in mented with a single PMOS transistor. The output of
Fig. 5(a). Each control bit ck [n] (equal for all blocks the DAC is differential and therefore two switches are
Sk,r within the kth layer) can be programmed to be ran- used for each weight (Fig. 1(a)). The current switches
dom or fixed. In an implementation the random signal are implemented with PMOS transistors and the dif-
could be generated on-chip using, e.g., a PRBS gen- ferential switching signals are slightly overlapping to
erator [14], but for simplicity and controllability the reduce the glitches. The peak differential output current
signal is generated off-chip. The ability to freely con- is 20 mA. The currents are doubly terminated over 50
trol ck [n] enables us to program the DAC to have zero loads.
to four switching layers. If all control bits are fixed
we get a 14-bit binary weighted DAC without switch-
ing. If the first control bit is set to random we get a 5.1. Chip Summary
PRDEM DAC with one switching layer and so on. To
improve local matching, unit current sources are used The process is a standard 0.35 µm 3-metal layer CMOS
to form the weights [1]. Hence for the kth LSB, we process. The chip data is further summarized in Table 2
use 2k−1 LSB current sources (unit current sources) and in Fig. 5(b) we show a chip photo of the converter.
14 Andersson et al.

6. Comparison of Simulated
and Measured Results

To verify the simulated results in Section 4.2 the im-

plemented DAC is measured with the same sampling
frequency, f samp = 10 MHz. The input is a full-scale
single-tone sinusoid and the single-ended output is
terminated over 50 .

6.1. Dependence on Order of Randomization

In Fig. 6(a) and (b) we compare the gain in perfor-

mance between using no randomization and using a

Fig. 6. Measured spectra, 10 MHz sampling frequency, (a) without Fig. 7. Simulated and measured SFDR performance for different
randomization, with (b) a single-layer switching and (c) four-layer sampling frequencies with (a) no randomization and (b) switching
switching. in all layers.
 Models and Implementation of a Dynamic Element Matching DAC 15

single layer switching. We find that the SFDR is in- References

creased from 61 dB to 68 dB, a gain 7 dB, which is be
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using DEM on a DAC. The model has been compared
with an implementation of a 3.3 V 14-bit current- 8. Wikner, J. J., Studies on CMOS Digital-to-Analog Convert-
ers, Dissertation, Linköping University, Thesis No. 667, ISBN
steering CMOS digital-to-analog converter (DAC) us- 91-7219-910-5, Linköping Sweden, March 2001.
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16 Andersson et al.

Mark Vesterbacka received the M.Sc. degree in

Niklas U. Andersson received the M.Sc. degree in applied physics and electrical engineering, the Lic.
applied physics and electrical engineering in 1999 from Eng. degree in applied electronics, and the Ph.D.
Linköping University, Sweden. He is currently working degree in electronics systems from Linköping
with R&D at Ericsson Microelectronics AB, Sweden. University, Sweden, in 1991, 1995, and 1997,
His major research interests are high-level modelling respectively. From 1997, he held faculty positions at
and error correction techniques for digital-to-analog Linköping University where he was appointed as
converters. professor of electronics systems in 2002. His current
research interests are concerned with design of mixed-
signal systems, targeting communication systems in
particular.

J. Jacob Wikner received the M.Sc. degree in com-

puter science and engineering in 1996 and the Ph.D. de-
gree in electronics systems in 2001, both from
Linköping University, Sweden. He studied high-speed
electronics and telecommunication theory at the Tech-
K. Ola Andersson received his M.Sc. degree in ap- nical University of Darmstadt, Germany, during 1995.
plied physics and electrical engineering in 2000 from Currently he is a senior design engineer at the Ericsson
Linköping University, Sweden, where he is currently Microelectronics’ Swindon Design Centre, UK, and
a Ph.D. student. His research interests include model- honorary research associate at the Circuits and Systems
ing and implementation of digital-to-analog convert- Group, Department of Electrical and Electronic Engi-
ers for telecom applications. Between December 1999 neering, Imperial College, London, UK. His research
and January 2002 he worked as a research engineer at interests include design and modeling of analog low-
Ericsson Microelectronics AB, Sweden, with similar power, low-voltage systems, mixed-signal systems and
issues. data converters.