Received October 21, 2019, accepted November 27, 2019, date of current version December 16, 2019.

Digital Object Identifier 10.1109/ACCESS.2019.2957180

A New Single Phase Single Switched-Capacitor

Based Nine-Level Boost Inverter Topology With
Reduced Switch Count and Voltage Stress
MARIF DAULA SIDDIQUE 1,2 , (Student Member, IEEE),
SAAD MEKHILEF 1,3 , (Senior Member, IEEE),
NORAISYAH MOHAMED SHAH 1 , (Member, IEEE),
JAGABAR SATHIK MOHAMED ALI 4 , (Senior Member, IEEE),
MOHAMMAD MERAJ 2 , (Student Member, IEEE),
ATIF IQBAL 2 , (Senior Member, IEEE), AND MOHAMMED A. AL-HITMI 2
1 Power Electronics and Renewable Energy Research Laboratory, Department of Electrical Engineering, University of Malaya, Kuala Lumpur 50603, Malaysia
2 Department of Electrical Engineering, Qatar University, Doha, Qatar
3 School of Software and Electrical Engineering, Faculty of Science, Engineering and Technology, Swinburne University of Technology, Victoria, VIC 3122,

Australia
4 Department of Electrical and Electronics Engineering, SRM University, Kattankulathur 603203, India

Corresponding author: Mohammad Meraj (mohammadmerajeee@gmail.com)

This work was supported in part by the QU High Impact under Grant QUHI-CENG-19/20-2 from Qatar University, and in part by the Qatar
National Library, Doha, Qatar.

ABSTRACT Based on the concept of switched-capacitor based multilevel inverter topology, a new structure
for a boost multilevel inverter topology has been recommended in this paper. The proposed topology uses
11 unidirectional switches with a single switched capacitor unit to synthesize nine-level output voltage
waveform. Apart from the twice voltage gain, self-voltage balancing of capacitor voltage without any
auxiliary method along with reduced voltage stress has been the main advantages of this topology. The merits
of proposed topology have been analyzed through various comparison parameters including component
counts, voltage stresses, cost and efficiency with a maximum value of 98.3%, together with the integration
of switched capacitors into the topology following recent development. Phase disposition pulse width
modulation (PD-PWM) technique and nearest level control PWM (NLC-PWM) have been used for the
control of switches. Different simulation and hardware results with different operating conditions are
included in the paper to demonstrate the performance of the proposed topology.

INDEX TERMS Multilevel inverter, boost inverter topology, switched-capacitor, single dc source, reduce
switch count, PWM.

I. INTRODUCTION reduced EMI, improved efficiency and many more. Neutral

With the rapid growth of the renewable energy resources point clamped (NPC), flying capacitor (FC) and cascade
and its application in high voltage applications link industrial H-bridge (CHB) are traditional topologies that have been
drive, high voltage dc transmission (HVDC), electric vehicle extensively researched and applied in different applications.
(EV), etc., power electronic converters play an important However, the major concerns with these topologies have
role in the power conversion suitable for each application. been the higher number of components, capacitor voltage
Multilevel inverters have its own importance in medium balancing and complex control for a higher number of levels
and high voltage applications due to reduced voltage rating [1]–[4]. Therefore, numerous topologies have been proposed
of power semiconductor devices for high voltage genera- with reduce switch count [5]–[14]. In [7], an optimal design
tion, reduced harmonic contents, the small size of the filter, of multilevel inverter topology has been discussed. The topol-
ogy of [7] uses several isolated dc voltage sources which
The associate editor coordinating the review of this manuscript and restricts its applications. Another topology based on isolated
approving it for publication was N. Prabaharan . voltage sources has been proposed in [9], in which 17 level

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see http://creativecommons.org/licenses/by/4.0/
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output voltage has been achieved using four voltage sources. captured in different loading conditions. Section V summa-
Similar topologies have been proposed in [10], [12]. In these rizes the paper.
topologies, higher number of levels can be generated to
improve the quality of the output voltage. However, most of II. PROPOSED NINE-LEVEL TOPOLOGY
these topologies lack the voltage boosting ability. A. DESCRIPTION OF THE PROPOSED TOPOLOGY
Voltage boosting is essential for the topologies to be used The circuit configuration of the proposed nine-level topology
in the integration with renewable energy resources especially has been depicted in Fig. 1. As shown in Fig. 1, the single dc
solar photovoltaic system due to its low voltage generation. source boost topology uses nine unidirectional switches and
Switched capacitor (SC) based multilevel inverter topologies one bidirectional switch along with two dc-link capacitors
with boosting feature gives a suitable approach for the low C1 and C2 and one switched capacitor C3 . The two dc-link
input voltage systems. In SCMLI, the switched capacitors capacitors C1 and C2 split the dc input voltage into equal half,
are charged and discharged in parallel and series configu- resulting in their voltage as Vdc /2. The switched capacitor C3
rations with dc input supply voltage, respectively. Further- is charged up to the dc input voltage Vdc through switches
more, SC-based topologies with self-voltage balancing of the S3 , S4 , S7 , and S8 . The switch S6 is used to give the boosting
capacitors without any auxiliary methods reduces the control feature of the proposed topology.
complexity of the system [15]–[21].
An SC-based MLI has been proposed in [22], which
generates five-level output voltage with unity voltage gain.
An improved topology of [22] has been proposed in [23]. The
topology of [23] produces seven level output voltage with a
voltage gain of 1.5. However, it uses two floating capacitors
with a voltage rating equal to a dc input voltage, which is
underutilized due to a lower voltage gain with higher voltage
ratings. Furthermore, two switches are needed to block twice
the input voltage. Another seven-level SC-based topology has
been suggested in [24], however, the unequal voltage step FIGURE 1. Proposed topology.
in [24] increases the harmonic content of the output voltage.
A topology with two dc-link capacitors and one floating The switching table for the proposed nine-level topology
capacitor has been proposed in [25]. It utilizes 10 switches is given in Table 1.
for seven-level generations, however, the voltage gain has
been limited to a value of 1.5. An improved topology of [26] TABLE 1. Switching states of the proposed topology.
has been proposed in [27] in which the voltage gain has
been extended to double the value of [26] to 1.5. Similar
to [26], a hybrid switched-capacitor based topology has been
proposed in [28] without boosting the input voltage. Another
topology with a voltage gain of 1.5 has been proposed in [29]
which has a higher switch count for the seven-level output
voltage.
In this paper, a new switches capacitor-based MLI topol-
ogy has been proposed with the aim of increasing the voltage
gain. The different merits of the proposed topologies are
• Uses a single dc voltage source with a single floating
capacitor for nine-level voltage generation
Reverse blocking voltage of a switch is an important aspect
• Twice voltage gain (Vo :Vin = 2)
in the design of the topology. Fig. 1 gives the maximum
• Maximum voltage stress of any switch is equal to input
blocking voltage of each switch used in the topology. Out
dc voltage source
of 11 switches, all the unidirectional switches need to block a
• Two switches are operated at the fundamental frequency
voltage equal to the input supply voltage, i.e., Vdc . The bidi-
• High voltage gain to switch ratio
rectional switch requires two unidirectional switches with a
• Self-capacitor voltage balancing independent of load
voltage rating of 0.5Vdc . Therefore the total standing voltage
parameters
(TSV), which is the sum of the maximum blocking voltage of
This paper has been organized as follows: Section II gives all switches, has a value of 10Vdc . Fig. 2 illustrates the voltage
the details of the proposed topology with capacitor value stress of all the switches considering all voltage levels at the
selection and modulation strategy. Section III gives a detailed output.
comparison with other SC-based MLI topologies. Section IV The operation of the proposed topology is explained with
elaborates the different simulation and experimental results the voltage states in the positive half cycle. The different

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FIGURE 2. Voltage stress of all switches for all voltage levels.

voltage level generation of the proposed topology are shown

in Fig. 3 (a)-(e).
• Zero Voltage State (Vo = 0): As shown in Fig. 3 (a),
the zero voltage state across the load by turning ON
switches S2 , S4 , S8 , and S10 . During zero voltage level,
the switched capacitor C3 is connected to the dc voltage
source and gets charged to Vdc .
• First Voltage State (Vo = 0.5Vdc ): As shown in Fig 3 (b),
the capacitor link voltage is utilized in these voltage
levels. The load is connected to the mid-point of the
dc-link capacitor through switches S2 , S5 , S7 , and S9 .
The capacitor voltage of C3 remains unchanged.
• Second Voltage State (Vo = Vdc ): In this voltage state,
the entire input voltage applies to the load. Simultane-
ously, the capacitor is also connected in parallel to the
dc voltage source to be charged. This voltage state is
illustrated in Fig. 3 (c).
• Third Voltage State ((Vo = 1.5Vdc ): In this voltage state,
as shown in Fig. 3 (d), the dc-link capacitor voltage
gets added to the switched capacitor voltage to give the
voltage level of 1.5Vdc .
• Fourth Voltage State (Vo = 2Vdc ): During this voltage
state, the input dc source voltage is added to the voltage
of the switched capacitor. This results in a voltage level
equal to twice the input voltage. The fourth voltage state
is illustrated in Fig. 3 (e).

B. MODULATION STRATEGY
For the proposed nine-level topology, phase-disposition pulse
width modulation (PD-PWM) technique has been used.
In this, four high-frequency carrier signals, each with a peak
to peak amplitude of one, and a frequency of fcr are compared
with a sinusoidal reference signal having a peak value of
Vsine to generate the pulses. Fig. 4 (a) shows the sinusoidal
reference signal along with four carrier waveforms to achieve FIGURE 3. Connection diagram with the conduction state of the switches
the nine-levels output voltage. To generate the gate pulses for for the proposed nine-level topology for voltage levels of (a) Vo = 0,
different switches, these pulses are configured according to (a) Vo = 0.5Vdc , (a) Vo = Vdc , (a) Vo = 1.5Vdc , and (a) Vo = 2Vdc .

Table 1 and the logic for the PWM generation is depicted

in Fig 4 (b). The modulation index (MI) for the nine-level
PD-PWM is given as Furthermore, the proposed nine-level topology has also been
Vsine tested with low switching frequency technique. Nearest
MI = (1) level control PWM (NLC-PWM) has been used as a low
4Vc
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FIGURE 5. Equivalent circuit of the proposed topology for (a) charging

loop (b) discharging loop for voltage level of ±1.5Vdc , and (b) discharging
loop for voltage level of ±2Vdc .

which is given by
Ipk
C3 = (2)
(1VC × fo )
where Ipk is the peak value of the load current, 1Vc is the
ripple voltage and fo is the frequency of the output voltage.

D. SELF-VOLTAGE BALANCING OF THE CAPACITOR

Self-voltage balancing of the capacitor voltage C3 has been
one of the important features of the proposed topology. The
capacitor C3 is charged up to Vdc during the voltage states
of zero and ±Vdc . During charging, the equivalent circuit for
the charging loop is shown in Fig. 5 (a). The capacitor C3
FIGURE 4. PWM control of the proposed topology with (a) PD-PWM, is directly connected to the input source voltage in parallel
(b) switching logic for the gate pulse generation for the proposed
topology and (c) NLCPWM.
through four switches. Therefore, in the charging loop, only
the ON-state resistance of switches rsw along with the equiva-
lent series resistance (ESR) of capacitor rESR is connected to
the capacitor C3 with the voltage source. Fig. 5 (b) and (c)
frequency technique for the gate pulse generation. In NLC- depicts the discharging loop during the voltage levels of
PWM, the sinusoidal reference signal Vsine is compared ±1.5Vdc , and ±2Vdc respectively. As the load is connected
with the staircase output voltage waveform Vstair as shown in the discharging loop, the time constant of the discharging
in Fig. 4 (c). The comparison generates the pulses and these circuit has a higher value compared to the charging circuit.
pulses are used for the gate pulse generation based on the The larges time constant in the discharging loop restricts the
switching logic of the proposed topology given in Table 1. rapid voltage drop of the capacitor voltage and it gets charged
to maintain the voltage drop during the next cycle of charging.
C. SELECTION OF CAPACITOR VALUE Therefore, over a complete fundamental period, the charging
During the positive half cycle, as depicted in Fig. 3 (a) and (c), and discharging of the capacitor is maintained to the voltage
the capacitor C3 is directly connected to the dc voltage source magnitude equal to the dc voltage source Vdc .
during voltage zero and Vdc . Similarly, during the negative Fig. 6 shows the variation of capacitor voltage VC3 for all
half cycle with voltage levels of zero and -Vdc , capacitor positive voltage levels with NLCPWM. Over a half cycle,
C3 gets charged by having a parallel connection with the the capacitor C3 is charged during zero voltage level i.e.,
input dc supply. For the charging loop, the time constant RC from (0 to t1 ) and from (t8 to t9 ). The capacitor voltage is
has a value which is lower than the charging duration. This maintained to Vdc during voltage levels of 0.5Vdc and Vdc .
results in the full charging of the capacitor C3 . During the As the capacitor discharged during the voltage level of 1.5Vdc
voltage levels of ±1.5Vdc , and ±2Vdc , the energy stored in and 2Vdc , the capacitor voltage drops to Vdc − 1VC3 where
the capacitor is transferred to the load. The decrease in the 1VC3 is the allowed voltage ripple of capacitor as given
stored energy level causes a drop in the capacitor voltage in (2). Again from (t6 to t7 ), the capacitor C3 is connected in
i.e., ripple voltage. The ripple voltage can be regulated by parallel to the input voltage source and get charged upto Vdc .
the proposed selection of capacitance value of the capacitor The same pattern is repeated during negative voltage levels.

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FIGURE 7. Efficiency comparison of different topologies.

FIGURE 6. Output voltage with the variation of capacitor voltage VC3 .

voltage gain has a value of 0.5 with a higher number of

TABLE 2. Comparison between proposed Topology and topologies with
single source configuration.
switches and capacitors compared to all other topologies
listed in Table 2.
A cost comparison has also been carried out with the
topologies listed in Table 2. For a fair comparison, the nor-
malized cost has been calculated by dividing the total cost
with the value of voltage gain.
Total Cost
Normalized Cost = (4)
G
For the cost comparison, the input voltage has been selected
as 600V and the different components of topology have been
selected accordingly. Form Table 3, the proposed topology
gives the lowest normalized cost with respect to all other
topologies used in the comparison. The lower cost is due to
the lower values of voltage stresses and higher voltage gain.
In addition to quantitative and cost comparison, efficiency
has also been taken into consideration. The equal peak of
output voltage is used to estimate its efficiency. Fig. 7 depicts
III. COMPARATIVE STUDY
the efficiency variation with respect to output power. The
In this section, a comparison between the proposed and other
proposed topology has similar efficiency to the topologies
similar topologies has been conducted. The comparison has
proposed in [23] and [25] and higher than [27]. Therefore,
been carried out in terms of number of switches, number of
from Table 2, Table 3 and Fig. 4, the newly proposed topology
the gate driver circuit, number of levels, number of capacitors
performed better compared to other topologies.
and terms related to voltage stress and gain which are calcu-
lated as
 IV. RESULTS AND DISCUSSION
TSV
TSVpu = 
 A. SIMULATION RESULTS
Vo,peak



 The results of the proposed topology are simulated using
MBV 
MBVpu = (3) PLECS software. For the simulation, the dc input voltage is
Vo,peak 
 selected as 200V. The carrier frequency for the PD-PWM has
Vo,peak 

Voltage gain = G = 
 been selected as 2.5 kHz with an output frequency of 50 Hz.
Vstep

The output voltage, output current and switched capacitor
Table 2 gives the quantitative comparison of various topolo- voltage VC3 for a purely resistive load of 50 is shown
gies with the proposed one. The topology in [20] along with in Fig. 8 (a). With the input voltage of 200V, the peak of
the proposed one achieves nine-level output voltage, however, the output voltage has a value of 400V, which verifies the
the topology of [20] has a unity voltage gain and does not twice voltage gain of the proposed topology. The nine-level
boost the input supply voltage, whereas the proposed topol- output voltage has a voltage step of 100V. For the boosting
ogy gives twice voltage gain. Furthermore, [27] and [29] uses of input voltage, the capacitor C3 is charged up to 200V and
less number of switches compared to the proposed topology, is maintained at 200V as depicted in Fig. 8 (a). Similarly,
however, the voltage gain of both topologies have a value the various waveforms for the proposed nine-level topology
lower than the proposed topology. In addition, both topolo- with a series-connected resistive-inductive load of 200mH
gies have higher TSVpu and MBVpu . The topology proposed and 10 have been illustrated in Fig. 8 (b). With differ-
in [28] has same TSVpu and lower MBVpu , however, the ent loading conditions, the capacitor voltage for both cases

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TABLE 3. Cost Comparison Between proposed 9LBI and Recently Introduced Topologies with Single Source Configuration.

remained at 200V, demonstrating the self-voltage balancing output voltage, current and capacitor voltage waveforms for
of the capacitor voltage VC3 . a transition of modulation technique, i.e., from PD-PWM to
Furthermore, the proposed topology has been tested with NLC-PWM. The parameter of the load during the change
the dynamic loading and change of modulation index. of modulation technique has been selected as Z = 100mH
Fig. 9 (a) shows the waveforms of the output voltage, output + 25. With all the simulation experiments, the proposed
current and switched capacitor voltage VC3 with changing topology gives satisfactory results in all operating conditions
load type and load parameters. First, the load is of purely with self-voltage balancing of the capacitor voltage. In addi-
resistive nature with Z1 = 25 and at time 0.15 sec, the value tion, Fig. 10 (b) and (c) depicts the harmonic spectrum of
of the load is doubled to Z2 = 50, reducing the load current the nine level output voltage with PD-PWM and NLCPWM
to half of its previous value of load current (i.e., the peak respectively. With PD-PWM, the value of THD is 14.1%
of load current reduced to 8A from 16A). At time 0.2 sec, whereas with NLCPWM, the amout of THD is 9.4%. How-
the load type is changed from resistive to series-connected ever, with PD-PWM, the lower order harmonics has has very
resistive- inductive load with Z3 = 100mH + 25. The load low value compare to lower order harmonics of NLCPW as
current now changes its nature from a staircase to almost a shown in Fig. 10 (b) and (c).
sinusoidal waveform with a peak value of 9.9A. Furthermore, The power loss distribution for the proposed topology has
at the time of 0.25 sec, the load parameters are changed to been carried out by modeling the semiconductor devices in
Z4 = 100mH + 25, which results in a reduction of the peak PLECS software. Table 4 gives the power loss of all switches
current value from 9.9A to 6.7A. With all these variations of and capacitors together with the efficiency of the proposed
load parameters, the capacitor voltage VC3 remains balanced topology with an output power of 500W and 2000W. The
with the change in the ripple voltage. switching power loss (Psw ) and conduction power loss (Pc ) of
In addition to variation in the load parameters, the change the switches have also been given in Table 4. The maximum
of modulation index has also been simulated for the proposed power loss is associated with the switch pair (S3 , S4 ) and
nine-level topology. Fig. 9 (b) illustrates the effect of change (S7 , S8 ). The higher power loss of these switch pairs are due
of MI on the output voltage, output current and capacitor to their operation during the charging and discharging of the
voltage with a load of Z = 50mH + 20. With MI = 1.0, switched capacitor C3 .
the rms value of output voltage has a magnitude of 281.5V. Furthermore, the variation of efficiency against the out-
Now at time 0.3 sec, the value of MI is changed to 0.8 which put power with both PD-PWM and NLCPWM are shown
reduces the rms value of output voltage to 228.6V. However, in Fig. 11. The maximum efficiency of the proposed con-
with MI = 0.8, the number of levels does not change from verter has a value of 98.6% at the output power of 100W
nine. Again, at the time of 0.35 sec, the MI is changed to 0.5, with NLCPWM. As the output power increases, the effi-
which results in the reduction of the number of levels from ciency decreases, however, the drop is low and the pro-
nine to five with a reduction in rms value to 146.3V. posed topology gives 92.2% efficiency at the output power
Additionally, the proposed nine-level topology has been of 5kW. As shown in Fig. 11, the efficiency of the proposed
tested with the NLCPWM technique. Fig. 10 illustrates the topology has a slighter lesser value with PD-PWM compare

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FIGURE 8. Simulation results of output voltage, current and capacitor

voltage VC3 with (a) purely resistive load Z = 50 and (b) series
connected resistive-inductive load Z = 200mH + 10.
FIGURE 9. Simulation results of output voltage, current and capacitor
voltage VC3 with (a) change of load and (b) change of modulation
index (MI).
to NLCPWM. This is due to the lower switching losses
due to lower number of transition of state in NLCPWM used with the PD-PWM technique with a carrier frequency
compare to PD-PWM. of 2.5kHz. NLC-PWM has also been used for the output
voltage generation with fundamental switching frequency.
B. EXPERIMENTAL VALIDATION The different parameters used for obtaining the experimental
To validate the simulation results of the proposed nine-level results are listed in Table 5.
topology, a prototype experimental setup has been developed As the proposed topology generates nine-level output volt-
in the laboratory as shown in Fig. 12. For the generation age with twice voltage gain, with the input dc voltage source
of gate pulses for different switched, dSPACE has been of 70V, the peak of the output voltage has a magnitude

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TABLE 4. Power loss distribution of the proposed topology.

FIGURE 11. Efficiency vs output power curve of the proposed topology.

FIGURE 10. Simulation results of (a) output voltage, current and capacitor
voltage VC3 with change of modulation technique, (b) harmonic spectrum FIGURE 12. Experimental setup of the proposed topology.
of output voltage with PD-PWM and (c) harmonic spectrum of output
voltage with NLCPWM.

a purely resistive load having a magnitude of 100 to an

of 140V with a step voltage of 35V. Fig. 13 (a) shows the RL load of 30+ 30mH. As the load changes, the change
output voltage and current waveform for a series-connected of load current from a peak value of 1.4A to 4.8A takes
resistive-inductive load with PD-PWM. Fig. 13 (b) illustrates place. However, with the change of load current and load
the waveforms of voltage, current and capacitor voltage VC3 type, the capacitor voltage remain balanced with an increase
with a dynamic load condition. The load is changed from in the ripple voltage. This shows the self-voltage balancing

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FIGURE 13. Experimental results with PD-PWM (a) output voltage and current waveform with Z = 15  + 30mH and (b) output voltage, current and
capacitor voltage waveform for change of load from purely resistive load to series connected resistive-inductive load.

TABLE 5. Experimental parameters.

FIGURE 15. Experimental efficiency curve of the proposed topology.

FIGURE 14. Experimental results with NLC-PWM (a) output voltage and
current waveform with Z = 15 + 30mH and (b) output voltage, current
and capacitor voltage waveform for change of load from a series technique. Fig. 14 (b) shows the voltage and current wave-
connected resistive-inductive load to purely resistive load.
forms along with the capacitor voltage with a change of load
parameters from series-connected RL load to a purely resis-
tive load. All these experimental results with different loading
of the capacitor voltage without any auxiliary circuit or any and modulation technique give the satisfactory performance
sensors. of the proposed topology with the self-voltage balancing of
Furthermore, the proposed nine-level topology has been the capacitor voltage.
tested with the NLC-PWM technique. Similar to Fig. 143 (a), Fig. 15 illustrates the efficiency curve of the proposed
the output voltage and current waveform with series- con- obtained from the experimental setup using PD-PWM with
nected RL load are shown in Fig. 14 (a). A change in loading 2.5kHz. With a load of 100 , the output power measured
conditions has also been considered with the NLC-PWM was 100W, at which the measured efficiency was 97.8%.

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Nov. 2008.
in 2014 and 2016, respectively. He is currently pur-
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suing the Ph.D. degree with the Power Electron-
M. A. Memon, ‘‘A new multilevel inverter topology with reduce switch
count,’’ IEEE Access, vol. 7, pp. 58584–58594, 2019. ics and Renewable Energy Research Laboratory
[12] C. Dhanamjayulu and S. Meikandasivam, ‘‘Implementation and compari- (PEARL), Department of Electrical Engineering,
son of symmetric and asymmetric multilevel inverters for dynamic loads,’’ University of Malaya, Kuala Lumpur, Malaysia.
IEEE Access, vol. 6, pp. 738–746, 2017. He is currently a Visiting Researcher with the
[13] M. Saeedian, J. Adabi, and S. M. Hosseini, ‘‘Cascaded multilevel inverter Department of Electrical Engineering, Qatar University, Doha, Qatar. His
based on symmetric-asymmetric DC sources with reduced number of com- research interests include step-up power electronics converters (dc/ac and
ponents,’’ IET Power Electron., vol. 10, no. 12, pp. 1468–1478, Oct. 2017. dc/dc), and multilevel inverter topologies and their control.

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 M. D. Siddique et al.: New Single Phase Single Switched-Capacitor-Based Nine-Level Boost Inverter Topology

SAAD MEKHILEF (M’01–SM’12) received the MOHAMMAD MERAJ (S’17) received the bach-
B.Eng. degree in electrical engineering from the elor’s degree in electrical and electronics engineer-
University of Setif, Setif, Algeria, in 1995, and ing from Osmania University, Hyderabad, India,
the master’s degree in engineering science and the and the master’s degree in machine drives and
Ph.D. degree in electrical engineering from the power electronics from the Electrical Engineering
University of Malaya, Kuala Lumpur, Malaysia, Department, IIT Kharagpur, India, in 2012 and
in 1998 and 2003, respectively. He is currently 2014, respectively. He is currently pursuing the
a Professor and the Director with the Power Ph.D. degree in electrical engineering from Qatar
Electronics and Renewable Energy Research University, Qatar. He worked (Summer Internship)
Laboratory, Department of Electrical Engineering, as a R&D Design Engineer at Philips Electronics
University of Malaya, where he also the Dean of Faculty of Engineering, Ltd., India, from May 2013 to July 2013. He has received the Best Research
University of Malaya. He is also a Distinguished Adjunct Professor with Paper Award at the IEEE SIGMA 2018. He has received the Best Graduation
the School of Software and Electrical Engineering, Faculty of Science, Project Energy Efficiency Award from Kahramaa (organized by Tarsheed)
Engineering and Technology, Swinburne University of Technology, Victoria, and presented by Prime Minister of Qatar. His research interests include
Australia. He has authored or coauthored of more than 400 publications advanced, maximum solar power extraction, wind power generation etc.
in international journals and conference proceedings. His current research He is also working on advanced electrical machines and drives for all electric
interests include power converter topologies, control of power converters, transportation
renewable energy, and energy efficiency.
ATIF IQBAL received the B.Sc. (Hons.) and M.Sc.
Engineering (power system & drives) degrees
from Aligarh Muslim University (AMU), Aligarh,
India, in 1991 and 1996, respectively, and the
Ph.D. degree from Liverpool John Moores Uni-
versity, Liverpool, U.K., in 2006. He is currently
NORAISYAH MOHAMED SHAH (M’19) an Associate Professor of electrical engineering
received the B.Eng. degree from the University with Qatar University, and a Former Full Profes-
of Malaya, in 1999, the M.Eng. degree from Oita sor of electrical engineering with Aligarh Mus-
University, Japan, in 2003, and the Ph.D. degree lim University (AMU), Aligarh, India. He has
from George Mason University, Fairfax, VA, USA, been employed as a Lecturer with the Department of Electrical Engineer-
in 2014. She is currently a Senior Lecturer with the ing, AMU, Aligarh, since 1991, where he served as Full Professor, until
Department of Electrical Engineering, University August 2016. He has authored/coauthored more than 300 research articles
of Malaya. Her current research interests include and one book and three chapters in two other books. He has supervised
signal processing and renewable energy. several large R&D projects. He has published widely in International Jour-
nals and Conferences his research findings related to power electronics and
renewable energy sources. His principal area of research interest is mod-
eling and simulation of power electronic converters, control of multiphase
motor drives and renewable energy sources, solar photovoltaic systems and
metaheuristic algorithms. He is also a Fellow of IET (U.K.) and Fellow
of IE (India). He was a recipient of Outstanding Faculty Merit Award AY,
from 2014 to 2015, and the Research Excellence Award at Qatar University,
Doha, Qatar, the Maulana Tufail Ahmad Gold Medal for standing first at
JAGABAR SATHIK MOHAMED ALI (M’15–
B.Sc. Engg. Exams, in 1991 from AMU. He has received the Best Research
SM’19) was born in Thanjavur, India, in 1979.
Papers Awards at the IEEE ICIT-2013, IET-SEISCON-2013, and SIGMA
He received the B.E. degree in electronics and
2018. He is also an Associate Editor the IEEE TRANSACTIONS ON INDUSTRY
communication engineering from Madurai Kama-
APPLICATION and the Editor-in-Chief of the Journal of Electrical Engineering,
rajar University, Madurai, India, in 2002, and
(i’manager).
the M.E. and Ph.D. degrees from the Faculty of
Electrical Engineering, Anna University, Chennai,
India, in 2004 and 2016, respectively. He is cur- MOHAMMED A. AL-HITMI was born in Qatar,
rently an Associate Professor with the Department in 1968. He received the B.Sc. degree in electrical
of Electrical and Electronics Engineering, SRM engineering from Qatar University, Doha, Qatar,
Institute of Science and Technology (formerly SRM University), Chennai, in 1992, and the M.Sc. and Ph.D. degrees in con-
India. He is also a consultant of various power electronics companies for trol engineering from The University of Sheffield,
design of power electronics converters. He has authored more than 20 arti- Sheffield, U.K., in 1994 and 2002, respectively.
cles publications in international journals and conference proceedings. His He is currently working as an Assistant Professor
research interests include multilevel inverters, gridconnected inverters, and with the Department of Electrical Engineering,
transformer-less grid-connected inverters, power electronics dc/dc converters Qatar University. His current research interests
and its applications in then renewable energy systems, multilevel inverters, include control systems theory, neural networks,
grid-connected inverters, power electronics converters, and its applications fuzzy control, and electric drive systems.
in renewable energy systems.

174188 VOLUME 7, 2019