Raptor AT: Motherboard Installation Guide
Raptor AT: Motherboard Installation Guide
Motherboard
Installation Guide
Table of Contents
Notice ...................................................... IV
Introduction .......................................... V
Chapter 1 Pre-Configuration ......1
Step 1 Setting the Jumpers 3
Jumper Locations ............................................................. 4
CMOS Reset....................................................................... 5
Disk-on-Chip Selection..................................................... 5
Flash BIOS Write Protect ................................................. 5
Clock Speed Selection ..................................................... 6
Watchdog Timer Selection............................................... 6
On-board Ethernet ............................................................ 7
ATX Power Supply Enhancements ................................. 7
Appendix A Technical
Specifications ..........39
Chipsets ........................................................................... 39
System Memory .............................................................. 39
Bios .................................................................................. 39
Embedded I/O .................................................................. 40
Industrial Devices ........................................................... 41
Miscellaneous ................................................................. 41
Memory Map .................................................................... 43
DMA Channels................................................................. 43
I/O Map ............................................................................. 44
On-board Devices ........................................................... 45
PCI Configuration Space Map........................................ 45
Interrupts ......................................................................... 46
PCI Interrupt Routing Map ............................................. 46
SMBUS ............................................................................. 47
Connectors Pin-out......................................................... 47
II
Appendix E On-Board
Ethernet .................67
III
Notice
The company reserves the right to revise this publication or to change
its contents without notice. Information contained herein is for
reference only and does not constitute a commitment on the part of the
manufacturer or any subsequent vendor. They are in no way
responsible for any loss or damage resulting from the use (or misuse) of
this publication.
Brand and product names mentioned in this publication may or may not
be copyrights and/or registered trademarks of their respective
companies. They are mentioned for identification purposes only and are
not intended as an endorsement of that product or its manufacturer.
Third Edition.
August, 2001
IV
Introduction
Thank you for your purchase of the Raptor AT industrial embedded
motherboard. The Raptor AT design was based on the Intel 440BX
chipset providing the ideal platform to industrial applications. The
Raptor AT design is based on the Intel Celeron and PIII processor.
Chapter 3 - Upgrading
Appendix C - Disk-on-Chip
Appendix E - Ethernet
VI
Warranty
Raptor AT - An Overview
The Raptor AT represents the ultimate in industrial embedded
motherboard technology. No other system board available today
provides such impressive list of features:
CPU Support
• 66 and 100MHz.
Memory
On-Board I/O
VII
ROM BIOS
On-Board Ethernet
VIII
Chapter 1 Pre-Configuration
This chapter provides all the necessary information for installing the
Raptor AT into a standard PC chassis. Topics discussed include:
installing the CPU (if necessary), DRAM installation, jumper settings
for CPU and standard I/O.
Handling Precautions
The Raptor AT has been designed to be as rugged as possible but it can
be damaged if dropped, jarred sharply or struck. Damage may also
occur by using excessive force in performing certain installation
procedures such as forcing the system board into the chassis or placing
too much torque on a mounting screw.
Static Warning
Jumper Types
Jumpers are small copper pins attached to the system board. Covering
two pins with a shunt closes the connection between them. The Raptor
AT examines these jumpers to determine specific configuration
information. There are three different categories of jumpers on the
Raptor AT.
A. Two pin jumpers are used for binary selections such as enable,
disable. Instructions for this type of jumper are open, for no shunt over
the pins or closed, when the shunt covers the pins.
How to identify pin number 1 on Figure 1-1: Looking to the solder side
(The board side without components) of the PCB (Printed Circuit
Board), pin number 1 will have a squared pad J. Other pins will have
a circular pad Q. They are numbered sequentially.
Jumper Locations
Use the diagram below and the tables on the following pages to locate
and set the on-board configuration jumpers.
CMOS Reset
Disk-on-Chip Selection
Flash
Enabled Disabled
Write-protect
JP2 1-2* 2-3
*Manufacturer's Settings.
The Raptor AT has a CPU automatic speed selector device. The jumper
JP11 allows selection for this option.
On-board Ethernet
The Raptor AT has a built-in 10/100 Ethernet. The jumper JP12 either
disables (2-3) or enables (1-2) this feature. For more information please
refer to Appendix E.
Ethernet
Enabled Disabled
Selection
JP12 1-2* 2-3
* Manufacturer's Settings.
The Raptor AT has a Power on mode selection. The jumper JP4 selects
the power on mode.
Power on upon
Power on Power on
PWR_SW signal
mode immediately
(Button press)
JP4 1-2* 2-3
* Manufacturer's Settings.
• DRAM (DIMMs)
• CPU
• Disk-on-chip
CPU Installation
Fan Heatsink
An active fan heatsink can be employed as a mechanism for cooling the
Intel processors. This is the acceptable solution for most chassis.
Adequate clearance must be provided around the fan heatsink to ensure
unimpeded air flow for proper cooling.
Disk-on-Chip installation
Installing Cables
The Raptor AT gets power either from the power ATX connector J7 or
the power AT connector J41.
10
Connect the floppy cable (not included) to the system board. Then
connect remaining ends of the ribbon cable to the appropriate
peripherals. Connect the Ethernet cable (included). Connect the mouse
(included) and the parallel/2 serial cable (included). Finally, connect
the IDE cable (not included) to the system. Then connect remaining
ends of the ribbon cable to the appropriate peripherals. This concludes
the hardware installation of your Raptor AT system. Now it is a good
time to re-check all of the cable connections to make sure they are
correct.
11
12
Index of Connectors
Connector Description
J1 Power LED/Keylock
J2 Speaker
J3 CPU Fan
J4 Sys. Fan
J5 HDD LED
J6 Power Switch
J7 ATX Power
J8 Wake On LAN
J9 Keyboard
J10 PS/2 Mouse
J12 FDD - Floppy
J13 LPT - Parallel
J14 USB (2x)
J16 Primary IDE
J17 Secondary IDE
J18 ISA Slot 1
J19 ISA Slot 2
J20 PCI Connector 1
J21 PCI Connector 2
J22 PCI Connector 3
J23 PCI Connector 4
J25 Infra Red
J31 Ethernet Header
J33 RESET
J35 ISA Slot 3
J36 COM 1
J37 COM 2
J38 ISA Slot 4
J41 AT Power
13
14
The BIOS Setup has a built-in keyboard driver that uses simple
keystroke combinations:
Keystroke Function
<Tab> Move to the next window or field.
,,, Move to the next field to the right, left, above, or below.
<Enter> Select in the current field.
+ Increments a value.
- Decrements a value.
<Esc> Closes the current operation and return to previous level.
<PgUp> Returns to the previous page.
<PgDn> Advances to the next page.
<Home> Returns to the beginning of the text.
<End> Advances to the end of the text.
<Alt> <H> Access a help window.
<Alt> <Spacebar> Exit WINBIOS Setup.
Alphabetic keys A to Z are used in the Virtual Keyboard, and are not case-
sensitive.
Numeric keys 0 to 9 are used in the Virtual Keyboard and Numeric Keypad.
15
Standard Setup
Date/Time
Floppy Drive A, B
16
Quick Boot
17
This option selects usage right from the floppy drive. The setting
is either Read/Write (default) or Read-Only.
This option selects usage right from the hard disk. The setting is
either Read/Write (default) or Read-Only.
18
Set this option to Off to turn the Num Lock key off when the
computer is booted so you can use the arrow keys on both the
numeric keypad and the keyboard.
Typematic Rate
System Keyboard
19
Password Check
BOOT to OS/2
20
C000,16K Shadow
C400,16K Shadow
C800,16K Shadow
CC00,16K Shadow
D000,16K Shadow
D400,16K Shadow
D800, 16K Shadow
DC00,16K Shadow
21
SERR#
PERR#
WSC# Handshake
The options are Disabled, 32, 64 (default), 96, 128, 160, 192 and
224.
The options are Disabled, 32 (default), 64, 96, 128, 160, 192 and
224.
22
N/A.
The settings for the option are: Auto (default) (uses SPD) and
Enabled (BIOS test).
The settings for the option are: 15.6 (default), 31.2, 62.4, 124.8,
7.8 and External.
Memory Hole
23
The settings for this option are: All, Miss (default) and Miss/All.
The settings for this option are: Enabled and Disabled (default).
The settings for this option are: Enabled and Disabled (default).
Gated Clock
The settings for this option are: Enabled (default) and Disabled.
The settings for this option are: 4, 8, 16, 32, 64 (default), 128
and 256.
N/A.
PIIX4 SERR#
The settings for this option are: Enabled and Disabled (default).
The settings for this option are: Enabled (default) and Disabled.
24
The settings for this option are: Enabled (default) and Disabled.
The settings for this option are: Enabled (default) and Disabled.
The settings for these options are: Normal ISA (default), PC/PCI
and distributed.
The settings for this option are: Strong (default), Medium and
Auto.
Manufacture Setting
The settings for this option are: Mode 0 (default), Mode 1, Mode
2, Mode 3 and Mode 4.
25
This option specifies the power state that the green PC-
compliant video monitor enters when AMIBIOS places it in a
power saving state after the specified period of display inactivity
has expired. The settings are Off, Standby and Suspend. The
default setting is Suspend.
This option specifies the power management state that the video
subsystem enters after the specified period of display inactivity
has expired. The settings are Disabled, Standby and Suspend.
The default setting is Suspend.
This option specifies the power management state that the hard
disk drive enters after the specified period of display inactivity
has expired. The settings are Disabled, Standby and Suspend.
The default setting is Suspend.
26
The settings for this option are: Sleep, Stop Clock and Deep
Sleep. The default setting is Sleep.
Standby Timeout
Suspend Timeout
This option specifies the speed at which the system clock runs in
the Standby Mode power saving state. The settings are
expressed as a percentage between the normal CPU clock speed
and the CPU clock speed when the computer is in the power-
conserving state. The settings are 0-12.5%, 12.5-25%, 25-
37.5%, 37.5-50%, 50-62.5%, 62.5-75% and 75-87.5%. The
Optimal and Fail-Safe default setting is 50-62.5%.
Display Activity
Device 6 (Serial 1)
Device 7 (Serial2)
Device 8 (Parallel)
Device 5 (Floppy)
27
LAN Wake-Up
The settings for this option are: Disabled (default) and Enabled.
This option sets latency of all PCI devices on the PCI bus. The
settings are in units equal to PCI clocks. The settings are 32, 64,
28
This option specifies the PCI interrupt used by the primary IDE
channel on the off-board PCI IDE controller. The settings are:
Disabled, INTA, INTB, INTC, INTD and Hardwired. The
Optimal and Fail-Safe default setting is Disabled.
29
These options specify the IRQ priority for PCI devices installed
in the PCI expansion slots. The settings are Auto, (IRQ) 3, 4, 5,
7, 9, 10, 11, 12 and 14. The Optimal and Fail-Safe default
setting is Auto.
DMA Channel 0
DMA Channel 1
DMA Channel 3
DMA Channel 5
DMA Channel 6
DMA Channel 7
These options allow you to specify the bus type used by each
DMA channel. The setting is either PNP or ISA/EISA. The
optimal and fail-safe default setting is PNP.
IRQ3
IRQ4
IRQ5
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
These options specify the bus that the specified IRQ line is used
on. These options allow you to reserve IRQs for legacy ISA
adapter cards. These options determine if AMIBIOS should
remove an IRQ from the pool of available IRQs passed to
30
This option specifies the size of the memory area reserved for
legacy ISA adapter cards. The settings are Disabled, 16K, 32K
and 64K. The Optimal and Fail-Safe default setting is Disabled.
Peripheral Setup
Onboard FDC
31
This option specifies the base I/O port address of serial port 1.
The settings are Auto (AMIBIOS automatically determines the
correct base I/O port address), Disabled, 3F8h, 2F8h, 3E8h and
2E8h. The Optimal and Fail-Safe default setting is Auto.
This option specifies the base I/O port address of serial port 2.
The settings are Auto (AMIBIOS automatically determines the
correct base I/O port address), Disabled, 3F8h, 2F8h, 3E8h and
2E8h. The Optimal and Fail-Safe default setting is Auto.
Receiver/Transmitter Polarity
This option specifies the base I/O port address of the parallel
port on the motherboard. The settings are Auto, Disabled, 378h,
278h and 3BCh. The Optimal default setting is Auto.
This option specifies the parallel port mode. The settings are:
normal, ECP (default) and EPP.
32
EPP Version
This option specifies the IRQ always used by the parallel port.
When the port is set to a fixed address the settings are (IRQ) 5
and (IRQ) 7 (default), otherwise it is set to Auto.
This option is only available if the setting for the Parallel Port
Mode option is ECP. This option sets the DMA channel used by
the parallel port. When the port is set to a fixed address the
settings are DMA Channel 0, 1 and 3 (default), otherwise it is
set to Auto.
33
CPU Fan
Secondary Fan
The current fan speed is shown (only available with the optional
hardware monitor).
Onboard IDE
This option specifies the IDE channel used by the onboard IDE
controller. The settings are Disabled, Primary, Secondary and
Both (default).
Choose this option to let AMIBIOS find the IDE hard disk drive
parameters for all IDE drives connected to the primary and
secondary IDE channels installed in the system. AMIBIOS
automatically configures the drive parameters after it has
detected these parameters.
34
N/A.
You can load the optimal default settings for the AMIBIOS by
selecting the Optimal option. The Optimal default settings are
best-case values that should optimize system performance. If
CMOS is corrupted, the Optimal settings are loaded
automatically.
35
36
Chapter 3 Upgrading
37
38
Appendix A Technical
Specifications
Chipsets
Core Logic
Peripheral I/O
System Memory
Memory Capacity
Memory Type
Bios
System BIOS
Embedded I/O
IDE
Floppy
Serial Ports
USB Interfaces
Parallel Port
Mouse Port
40
On-board Ethernet
Industrial Devices
Watchdog Timer
POST Code
Power Management
Miscellaneous
CMOS/Battery
41
CPU Socket
Form Factor
PCB Construction
Manufacturing Process
Reliability
42
Memory Map
Address Address
Range Range Size Description
Decimal Hexadecimal
0F0000-
960K-1M 64 KB Upper BIOS
0FFFFF
0E0000-
896K-960K 64 KB Lower BIOS
0EFFFF
Expansion
0C0000-
768K-896K 128 KB Card BIOS
0DFFFF
and Buffer
Standard
0A0000- PCI/ISA
640K-768K 128 KB
0BFFFF Video
Memory
Ext.
080000-
512K-640K 128 KB Conventional
09FFFF
memory
000000- Conventional
0K- 512K 512 KB
07FFFF memory
DMA Channels
43
I/O Map
44
On-board Devices
DISK ON CHIP 1
Memory address selectable between:
D000(default), D400, D800, DC00.
DISK ON CHIP 2
Memory address selectable between:
D000, D400(default), D800, DC00.
Interrupts
PIIX4
IDSEL PIRQA PIRQB PIRQC PIRQD
Signal
PCI Slot 1 AD26 INTC INTD INTA INTB
PCI Slot 2 AD27 INTB INTC INTD INTA
PCI Slot 3 AD29 INTA INTB INTC INTD
PCI Slot 4 AD31 INTD INTA INTB INTC
Ethernet AD25 INTA
USB - INTD
46
SMBUS
Connectors Pin-out
How to identify pin number 1: Looking to the solder side (The board
side without components) of the PCB (Printed Circuit Board), pin
number 1 will have a squared pad J. Other pins will have a circular
pad Q.
47
48
49
Connector Description
Infra Red
J25 1)Rx 2)Tx 3)GND 4)NC 5)Key 6)Vcc
HDD LED
J5 1)Anode 2)Cathode
CPU FAN
J3 1)Sense 2)+12V 3)GND
SYS FAN
J4 1)Sense 2)+12V 3)GND
Speaker
J2 1)+5V 2)NC 3)NC 4)Signal
Wake On LAN
J8 1)5V Standby 2)GND 3)WOL Signal
50
When updating your BIOS, make sure you have a disk with the correct
BIOS file (its size should be 256K).
Please never turn the power off while reprogramming a FLASH BIOS.
Do not forget to move Jumper JP2 back to 1-2 after turning off.
Flash
Enabled Disabled
Write-protect
JP2 1-2* 2-3
*Manufacturer's Settings.
51
Beeps Description
1 Insert diskette in floppy A:
The AMIBOOT.ROM file was not found
2
in the root directory of floppy drive A:
3 Base memory error
4 Flash program successful
5 Floppy read error
Keyboard controller BAT command
6
failed
7 No FLASH EPROM detected
8 Floppy controller failure
9 Boot Block BIOS checksum error
10 Flash erase error
11 Flash program error
12 AMIBOOT.ROM file size error
52
Appendix C Disk-On-Chip
The Raptor AT offers two on-board flash disks as optional devices. The
Disk-On-Chip is a single chip flash disk device in a standard 32-pin
DIP socket.
Jumper JP7 selects the memory addresses to be used for the Disk-On-
Chip. Possible addresses are listed below.
53
54
Appendix D On-Board
Industrial Devices
The Raptor AT features two industrial devices: A watchdog timer that
will reset the system is case of failure according to a pre-set time-out,
and a Post Code display that will help you on troubleshooting.
Watchdog Timer
Hardware Reset
Software Reset
The software has to access the watchdog timer at least every time-out
to prevent the board from resetting. This allows a very tight control of
the motherboards operation, but involves writing software for the time-
out control. For using software control, you need to know the watchdog
address, the enable bit and the strobe bit. For example, if you set the
watchdog timer to address 310h, you have to output a 0 at bit 1 of 310h
to enable the watchdog, and then toggle bit 0 of 310h to strobe it. If the
strobe signal takes longer than the time-out the board will reset.
55
56
Checkpoint
Description
Code
The NMI is disabled. Power on delay is starting. Next,
D0h
the initialization code checksum will be verified.
Initializing the DMA controller, performing the
D1h keyboard controller BAT test, starting memory refresh,
and entering 4 GB flat mode next.
D3h Starting memory sizing next.
Returning to real mode. Executing any OEM patches
D4h
and setting the stack next.
Passing control to the uncompressed code in shadow
D5h RAM at E000:0000h.The initialization code is copied to
segment 0 and control will be transferred to segment 0.
Control is in segment 0. Next, checking if <Ctrl>
<Home> was pressed and verifying the system BIOS
checksum.
57
Checkpoint
Description
Code
The onboard floppy controller if available is initialized.
E0h
Next, beginning the base 512 KB memory test.
E1h Initializing the interrupt vector table next.
E2h Initializing the DMA and Interrupt controllers next.
Enabling the floppy drive controller and Timer IRQs.
E6h
Enabling internal cache memory.
EDh Initializing the floppy drive.
Looking for a floppy diskette in drive A:. Reading the
EEh
first sector of the diskette.
A read error occurred while reading the floppy drive in
EFh
drive A:.
Next, searching for the AMIBOOT.ROM file in the root
F0h
directory.
F1h The AMIBOOT.ROM file is not in the root directory.
Next, reading and analyzing the floppy diskette FAT to
F2h
find the clusters occupied by the AMIBOOT.ROM file.
Next, reading the AMIBOOT.ROM file, cluster by
F3h
cluster.
F4h The AMIBOOT.ROM file is not the correct size.
F5h Next, disabling internal cache memory.
FBh Next, detecting the type of flash ROM.
FCh Next, erasing the flash ROM.
FDh Next, programming the flash ROM.
Flash ROM programming was successful. Next,
FFh
restarting the system BIOS.
58
Checkpoint
Description
Code
The NMI is disabled. Next, checking for a soft reset or a
03h
power on condition.
The BIOS stack has been built. Next, disabling cache
05h
memory.
06h Uncompressing the POST code next.
07h Next, initializing the CPU and the CPU data area.
08h The CMOS checksum calculation is done next.
The CMOS checksum calculation is done. Initializing
0Ah
the CMOS status register for date and time next.
The CMOS status register is initialized. Next,
0Bh performing any required initialization before the
keyboard BAT command is issued.
The keyboard controller input buffer is free. Next,
0Ch
issuing the BAT command to the keyboard controller.
The keyboard controller BAT command result has been
0Eh verified. Next, performing any necessary initialization
after the keyboard controller BAT command test.
The initialization after the keyboard controller BAT
0Fh command test is done. The keyboard command byte is
written next.
The keyboard controller command byte is written. Next,
10h issuing the Pin 23 and 24 blocking and unblocking
command.
Next, checking if <End or <Ins> keys were pressed
during power on.
11h Initializing CMOS RAM if the Initialize CMOS RAM in
every boot AMIBIOS POST option was set in AMIBCP
or the <End> key was pressed.
Next, disabling DMA controllers 1 and 2 and interrupt
12h
controllers 1 and 2.
The video display has been disabled. Port B has been
13h
initialized. Next, initializing the chipset.
14h The 8254 timer test will begin next.
The 8254 timer test is over. Starting the memory refresh
19h
test next.
59
Checkpoint
Description
Code
The memory refresh line is toggling. Checking the 15
1Ah
second on/off time next.
Reading the 8042 input port and disabling the
MEGAKEY Green PC feature next. Making the BIOS
23h
code segment writable and performing any necessary
configuration before initializing the interrupt vectors.
The configuration required before interrupt vector
24h initialization has completed. Interrupt vector
initialization is about to begin.
Interrupt vector initialization is done. Clearing the
25h
password if the POST DIAG switch is on.
Any initialization before setting video mode will be
27h
done next.
Initialization before setting the video mode is complete.
28h Configuring the monochrome mode and color mode
settings next.
Bus initialization system, static, output devices will be
2Ah done next, if present. See Table D-7 for additional
information.
Passing control to the video ROM to perform any
2Bh
required configuration before the video ROM test.
All necessary processing before passing control to the
2Ch video ROM is done. Looking for the video ROM next
and passing control to it.
The video ROM has returned control to BIOS POST.
2Dh Performing any required processing after the video
ROM had control.
Completed post-video ROM test processing. If the
2Eh EGA/VGA controller is not found, performing the
display memory read/write test next.
The EGA/VGA controller was not found. The display
2Fh
memory read/write test is about to begin.
The display memory read/write test passed. Look for
30h
retrace checking next.
The display memory read/write test or retrace checking
31h failed. Performing the alternate display memory
read/write test next.
The alternate display memory read/write test passed.
32h
Looking for alternate display retrace checking next.
Video display checking is over. Setting the display
34h
mode next.
60
Checkpoint
Description
Code
The display mode is set. Displaying the power on
37h
message next.
Initializing the bus input, IPL, general devices next, if
38h
present. See Table D-7 for additional information.
Displaying bus initialization error messages. See Table
39h
D-7 for additional information.
The new cursor position has been read and saved.
3Ah
Displaying the Hit <DEL> message next.
The Hit <DEL> message is displayed. The protected
3Bh
mode memory test is about to start.
40h Preparing the descriptor tables next.
The descriptor tables are prepared. Entering protected
42h
mode for the memory test next.
Entered protected mode. Enabling interrupts for
43h
diagnostics mode next.
Interrupts enabled if the diagnostics switch is on.
44h Initializing data to check memory wraparound at 0:0
next.
Data initialized. Checking for memory wraparound at
45h
0:0 and finding the total system memory size next.
The memory wraparound test is done. Memory size
46h calculation has been done. Writing patterns to test
memory next.
The memory pattern has been written to extended
47h memory. Writing patterns to the base 640 KB memory
next.
Patterns written in base memory. Determining the
48h
amount of memory below 1 MB next.
The amount of memory below 1 MB has been found and
49h verified. Determining the amount of memory above 1
MB memory next.
The amount of memory above 1 MB has been found and
verified. Checking for a soft reset and clearing the
4Bh
memory below 1 MB for the soft reset next. If this is a
power on situation, going to checkpoint 4Eh next.
The memory below 1 MB has been cleared via a soft
4Ch
reset. Clearing the memory above 1 MB next.
The memory above 1 MB has been cleared via a soft
4Dh reset. Saving the memory size next. Going to checkpoint
52h next.
61
Checkpoint
Description
Code
The memory test started, but not as the result of a soft
4Eh
reset. Displaying the first 64 KB memory size next.
The memory size display has started. The display is
4Fh updated during the memory test. Performing the
sequential and random memory test next.
The memory below 1 MB has been tested and
50h initialized. Adjusting the displayed memory size for
relocation and shadowing next.
The memory size display was adjusted for relocation
51h
and shadowing. Testing the memory above 1 MB next.
The memory above 1 MB has been tested and
52h
initialized. Saving the memory size information next.
The memory size information and the CPU registers are
53h
saved. Entering real mode next.
Shutdown was successful. The CPU is in real mode.
54h
Disabling the Gate A20 line, parity, and the NMI next.
The A20 address line, parity, and the NMI are disabled.
57h Adjusting the memory size depending on relocation and
shadowing next.
The memory size was adjusted for relocation and
58h
shadowing. Clearing the Hit <DEL> message next.
The Hit <DEL> message is cleared. The <WAIT...>
59h message is displayed. Starting the DMA and interrupt
controller test next.
The DMA page register test passed. Performing the
60h
DMA Controller 1 base register test next.
The DMA controller 1 base register test passed.
62h
Performing the DMA controller 2 base register test next.
The DMA controller 2 base register test passed.
65h
Programming DMA controllers 1 and 2 next.
Completed programming DMA controllers 1 and 2.
66h
Initializing the 8259 interrupt controller next.
67h Completed 8259 interrupt controller initialization.
7Fh Extended NMI source enabling is in progress.
The keyboard test has started. Clearing the output buffer
80h and checking for stuck keys. Issuing the keyboard reset
command next.
A keyboard reset error or stuck key was found. Issuing
81h
the keyboard controller interface test command next.
62
Checkpoint
Description
Code
The keyboard controller interface test completed.
82h Writing the command byte and initializing the circular
buffer next.
The command byte was written and global data
83h initialization has completed. Checking for a locked key
next.
Locked key checking is over. Checking for a memory
84h
size mismatch with CMOS RAM data next.
The memory size check is done. Displaying a soft error
85h and checking for a password or bypassing WINBIOS
Setup next.
The password was checked. Performing any required
86h
programming before WINBIOS Setup next.
The programming before WINBIOS Setup has
completed. Uncompressing the WINBIOS Setup code
87h
and executing the AMIBIOS Setup or WINBIOS Setup
utility next.
Returned from WINBIOS Setup and cleared the screen.
88h Performing any necessary programming after WINBIOS
Setup next.
The programming after WINBIOS Setup has completed.
89h
Displaying the power on screen message next.
The first screen message has been displayed. The
<WAIT...> message is displayed. Performing the PS/2
8Bh
mouse check and extended BIOS data area allocation
check next.
8Ch Programming the WINBIOS Setup options next.
The WINBIOS Setup options are programmed.
8Dh
Resetting the hard diskcontroller next.
The hard disk controller has been reset. Configuring the
8Fh
floppy drivecontroller next.
The floppy drive controller has been configured.
91h
Configuring the hard disk drive controller next.
Initializing the bus option ROMs from C800 next. See
95h
Table D-7 for additional information.
Initializing before passing control to the adaptor ROM
96h
at C800.
Initialization before the C800 adaptor ROM gains
97h
control has completed. The adaptor ROM check is next.
63
Checkpoint
Description
Code
The adaptor ROM had control and has now returned
98h control to BIOS POST. Performing any required
processing after the option ROM returned control.
Any initialization required after the option ROM test has
99h completed. Configuring the timer data area and printer
base address next.
Set the timer and printer base addresses. Setting the RS-
9Ah
232 base address next.
Returned after setting the RS-232 base address.
9Bh Performing any required initialization before the
Coprocessor test next.
Required initialization before the Coprocessor test is
9Ch
over. Initializing the Coprocessor next.
Coprocessor initialized. Performing any required
9Dh
initialization after the Coprocessor test next.
Initialization after the Coprocessor test is complete.
Checking the extended keyboard, keyboard ID, and
9Eh
Num Lock key next. Issuing the keyboard ID command
next.
A2h Displaying any soft errors next.
The soft error display has completed. Setting the
A3h
keyboard typematic rate next.
The keyboard typematic rate is set. Programming the
A4h
memory wait states next.
Memory wait state programming is over. Clearing the
A5h
screen and enabling parity and the NMI next.
NMI and parity enabled. Performing any initialization
A7h required before passing control to the adaptor ROM at
E000 next.
Initialization before passing control to the adaptor ROM
A8h at E000h completed. Passing control to the adaptor
ROM at E000h next.
Returned from adaptor ROM at E000h control.
A9h Performing any initialization required after the E000
option ROM had control next.
Initialization after E000 option ROM control has
AAh
completed. Displaying the system configuration next.
Uncompressing the DMI data and executing DMI POST
ABh
initialization next.
B0h The system configuration is displayed.
B1h Copying any code to specific areas.
64
Checkpoint
Description
Code
Code copying to specific areas is done. Passing control
00h
to INT 19h boot loader next.
Checkpoint
Description
Code
Initializing the different bus system, static, and output
2Ah
devices, if present.
Initialized bus input, IPL, and general devices, if
38h
present.
39h Displaying bus initialization error messages, if any.
Initializing bus adaptor ROMs from C8000h through
95h
D8000h.
These are word checkpoints. The low byte of checkpoint is the system
BIOS checkpoint where control is passed to the different bus routines.
The high byte of checkpoint indicates that the routine is being executed
in different buses. This information will not be shown on POST code
display because this device is 8-bit only. However, it can be seen in any
equipment connected to I/O port address 0080h.
65
High Byte The high byte of these checkpoints includes the following
information:
Bits Description
0000 Function 0. Disable all devices on the bus.
0001 Function 1. Initialize static devices on the bus.
0010 Function 2. Initialize output devices on the bus.
0011 Function 3. Initialize input devices on the bus.
Bits 7-4
0100 Function 4. Initialize IPL devices on the bus.
0101 Function 5. Initiate general devices on the bus.
0110 Function 6. Initialize error reporting on the bus.
0111 Function 7. Initialize add-on ROMs for all buses.
Specify the bus
66
It can operate in either full duplex or half duplex mode. In full duplex
mode it adheres to the IEEE 802.3x Flow Control specification. Half
duplex performance is enhanced by a proprietary collision reduction
mechanism.
Ethernet
Enabled Disabled
Selection
JP12 1-2* 2-3
*Manufacturer's Settings.
67
68