IARJSET ISSN (Online) 2393-8021

ISSN (Print) 2394-1588

International Advanced Research Journal in Science, Engineering and Technology

ISO 3297:2007 Certified
Vol. 3, Issue 7, July 2016

Design and Implementation of 4-2 Compressor

Design with New Xor-Xnor
A. Chandrakala1, A. Sreeramulu2, L. Srinivas3
M.Tech (VLSI), PG Student1
Associate Professor2
Govt. Lecturer, DTE3

Abstract: In this paper, a low-power high speed 4:2 compressor circuit is proposed for fast digital arithmetic integrated
circuits. The 4:2 compressor has been widely employed for multiplier realizations. Based on a new exclusive OR
(XOR) and exclusive NOR (XNOR) module, a 4:2 compressor circuit has been designed. Proposed circuit shows
power consumption is very less. Power consumption and delay of proposed 4-2 compressor circuit have been compared
with earlier reported circuits and proposed circuit is proven to have the minimum power consumption and the lowest
delay. Simulations have been performed by using verilog HDL.

Keywords: Full-Adder (FA), XOR-XNOR

I. INTRODUCTION

Multipliers are one of the most significant blocks in utilizing this property to design disentangled, yet inexact
computer arithmetic and are generally used in different circuits working at higher execution and/or lower power
digital signal processors. There is growing demands for utilization contrasted and exact (definite) logic circuits.
high speed multipliers in different applications of Expansion and multiplication are broadly utilized
computing systems, such as computer graphics, scientific operations as a part of computerized mathematic; for
calculation, image processing and so on. Speed of expansion adders and proposed a few new measurements
multiplier determines how fast the processors will run and for assessing rough and probabilistic adders as for brought
designers are now more focused on high speed with low together figures of legitimacy for outline appraisal for
power consumption. The multiplier architecture consists of estimated processing applications. For every data to a
a partial product generation stage, partial product circuit, the Error Distance(ED) is characterized as the
reduction stage and the final addition stage. The partial mathematic separation between a mistaken yield and the
product reduction stage is responsible for a significant right one. The Mean Error Distance (MED) and
portion of the total multiplication delay, power and area. normalized error distance (NED) are proposed by
Therefore in order to accumulate partial products, considering the averaging impact of various inputs and the
compressors usually implement this stage because they standardization of multiple-bit adders. The NED is almost
contribute to the reduction of the partial products and also invariant with the measure of an execution and is
contribute to reduce the critical path which is important to accordingly valuable in the unwavering quality evaluation
maintain the circuit’s performance. of a particular configuration. The tradeoff in the middle of
Most computerized mathematic applications are executed accuracy and force has additionally been quantitatively
utilizing digital logic circuits, in this manner working with assessed in.
a high degree of reliability and precision. In any case,
numerous applications, for example, in multimedia and II. COMPRESSOR
image processing can endure mistakes and imprecision in
calculation and still produce important and helpful results. One of the major speed enhancement techniques used in
Exact and precise models and algorithm are not generally modern digital circuits is the ability to add numbers with
suitable or productive for use in these applications. The minimal carry propagation. The basic idea is that three
paradigm of inaccurate calculation depends on relaxing numbers can be reduced to 2, in a 3:2 compressor, by
completely precise and totally deterministic building doing the addition while keeping the carries and the sum
modules when for instance, planning energy efficient separate.
system.
This permits uncertain calculation to divert the current This means that all of the columns can be added in parallel
design procedure of computerized circuits and systems by without relying on the result of the previous column,
exploiting a reduction in multifaceted nature and expense creating a two output "adder" with a time delay that is
with conceivably a potential increment in execution and independent of the size of its inputs. The sum and carry
force productivity. In exact (or vague) figuring depends on can be recombined in a normal addition to form the correct

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 IARJSET ISSN (Online) 2393-8021
ISSN (Print) 2394-1588

International Advanced Research Journal in Science, Engineering and Technology

ISO 3297:2007 Certified
Vol. 3, Issue 7, July 2016

result. This process may seem more complicated and manner. It is only the final recombination of the final carry
pointless, but the power of this technique is that any and sum that requires a carry propagating addition. 3:2
amount, number of additions can be added together in this compressor is also known as full adder. It adds three one
manner. It is only the final recombination of the final carry
bit binary numbers, a sum and a carry. The full adder is
and sum that requires a carry propagating addition. 3:2 usually a component in a cascade of adders. The carry
compressors is also known as full adder. input for the full adder circuit is from the carry output
from the cascade circuit. Carry output from full adder is
It adds three one bit binary numbers, a sum and a carry. fed to another full adder. The characteristics of the 4:2
The full adder is usually a component in a cascade of compressors are:
adders. The carry input for the full adder circuit is from
the carry output from the cascade circuit. Carry output  The outputs represent the sum of the five inputs, so it is
from full adder is fed to another full adder. really a 5 bit adder as shown in Fig.2.
 Both carries are of equal weighting (i.e. add "1" to the
III. 4-2 COMPRESSOR next column)
 To avoid carry propagation, the value of Cout depends
A compressor is a device which is mostly used in only on A, B, C and D. It is independent of Cin.
multipliers to reduce the operands while adding terms of  The Cout signal forms the input to the Cin of a 4:2 of
partial products. A typical M-N compressor takes M the next column.
equally weighted input bits and produces N-bit binary
number. The simplest and the most widely used The common implementation of a 4-2 compressor is
compressor is the 3-2 compressor which is also known as accomplished by utilizing two full-adder (FA) To add
a full adder. It has Three inputs to be summed up and binary numbers cells.4:2 compressor is composed of two
provides two outputs. Similarly, a 4-2 compressor can also serially connected full adders. With minimal carry
be built from two Cascaded 3-2 compressor circuits. The propagation we use compressor adder instead of other
conventional implementation of a 4-2 compressor is adder. Compressor is a digital modern circuit which is
composed of two serially connected full adders, as shown used for high speed with minimum gates requires
in fig.1. Different structures of 4-2 compressors are designing technique. This compressor becomes the
reported in literature and these are governing by the basic essential tool for fast multiplication adding technique on
equation as Follows: fast processor and lesser area.

A compressor is a device which is mostly used in

multipliers to reduce the operands while adding terms of
partial products. A typical M-N compressor takes M
equally weighted input bits and produces N-bit binary
number. The simplest and the most widely used
compressor is the 3-2 compressor which is also known as
a full adder. It has Three inputs to be summed up and
provides two outputs. Similarly, a 4-2 compressor can also
be built from two Cascaded 3-2 compressor circuits. The
conventional implementation of a 4-2 compressor is
composed of two serially connected full adders, as shown
in fig.1. Different structures of 4-2 compressors are
reported in literature and these are governing by the basic
equation as Follows:
Fig 1 Block Diagram Of 4-2 compressor

One of the major speed enhancement techniques used in

modern digital circuits is the ability to add numbers with
minimal carry propagation. The basic idea is that three The common implementation of a 4-2 compressor is
numbers can be reduced to 2, in a 3:2 compressor, by accomplished by utilizing two full-adder (FA) cells (Fig.2)
doing the addition while keeping the carries and the sum [8]. Different designs have been proposed in the literature
separate. This means that all of the columns can be added for 4-2 compressor. The optimized design of an exact4-2
in parallel without relying on the result of the previous compressor based on the so-called XOR-XNOR gates ;
column, creating a two output "adder" with a time delay a XOR-XNOR gate simultaneously generates the XOR
that is independent of the size of its inputs. The sum and and XNOR output signals. The design of consists of three
carry can be recombined in a normal addition to form the XORXNOR (denoted by XOR*) gates, one XOR and two
correct result. This process may seem more complicated 2-1 MUX es. The critical path of this design has a delay of
and pointless, but the power of this technique is that any 3Δ, where Δ is the unitary delay through any gate in the
amount, number of additions can beaded together in this design.

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International Advanced Research Journal in Science, Engineering and Technology

ISO 3297:2007 Certified
Vol. 3, Issue 7, July 2016

Sum, Carry bits. Any bit that does not belong to these
adders are bypassed to next stage and carry is propagated
to one-bit higher order column of next stage. Wallace
accumulates as many bits as possible into adders [10]. At
each stage, this process is continued until the stage height
is reduced to 2 rows. The Wallace tree 8x8 multiplier
along with its reduction stage .

V. SIMULATION RESULTS

Fig.2. 4-2 compressor xor –xnor module

4:2 compressors are capable of adding 4 bits and one

carry, in turn producing a 3 bit output. The 4-2 compressor
has 4 inputs X1, X2, X3 and X4 and 2 outputs Sum and
Carry along with a Carry-in (Cin) and a Carry-out (Cout).
Fig 3 Synthasis Report
The input Cin is the output from the previous lower
significant compressor. The Cout is the output to the
compressor in the next significant stage. The critical path
is smaller in comparison with an equivalent circuit to add
5 bits using full adders. However, like in the case of 3-2
compressor, the fact that both the output and its
complement are available at every stage is neglected. Thus
replacing some XOR blocks with multiplexer’s results in a
significant improvement in delay as shown in Fig.4. Also
the MUX block at the SUM output gets the select bit
before the inputs arrive and this minimizes the delay to a
considerable extent.
Fig 4 Schematic RTL
IV. MULTIPLICATION

In this section, the impact of using the proposed

compressors for multiplication is investigated. A fast
(exact) multiplier is usually composed of three parts (or
modules) .

 Partial product generation

 A Carry Save Adder (CSA) tree to reduce the partial
products’ matrix to an addition of only two operands
 A Carry Propagation Adder (CPA) for the final
computation of the binary result Fig 5 Schematic of 4:2 compressor using xor-xnor and
mux
In the design of a multiplier, the second module plays a
pivotal role in terms of delay, power consumption and REFERENCES
circuit complexity. Compressors have been widely used
[9, 10] to speed up the CSA tree and decrease its power [1] Sanjeev Kumar, Manoj Kumar ―4-2 Compressor design with New
XOR-XNOR Module‖, 4th International Conference on Advanced
dissipation, so to achieve fast and low-power operation. Computing and Communication technologies, pp. 106-111, 2014.
The use of approximate compressors in the CSA tree of a [2] Z. Wang, G. A. Jullien, and W. C. Miller, ―A new design
multiplier results in an approximate multiplier. technique for column compression multipliers,‖ IEEE Trans.
Computers, vol.44, pp. 962-970. Aug 1995.
[3] N. Weste, K. Eshranghian, Principles of CMOS VLSI Design: A
A. Wallace Tree Multiplier System Perspective, 1993.
Wallace Tree multiplier accumulates partial products [4] R. Zimmermann and W. Fichtner, ―Low-power logic styles:
column-wise into three and two bits and gives them to CMOS versus pass-transistor logic,‖ IEEE Journal of Solid–State
Full- Adders and Half Adders respectively to reduce as Circuits, vol.32, pp.1079-1090, July 1997.

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 IARJSET ISSN (Online) 2393-8021
ISSN (Print) 2394-1588

International Advanced Research Journal in Science, Engineering and Technology

ISO 3297:2007 Certified
Vol. 3, Issue 7, July 2016

[5] M. Zhang, J. Gu, and C. H. Chang, ―A novel hybrid pass logic

with static CMOS output drive full-adder cell,‖ in Proc. IEEE Int.
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[6] M. Shams, T. K. Darwish, and M. A. Bayoumi, ―Performance
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[7] S.F. Hsiao, M.R. Jiang, J.S. Yeh, ―Design of high low power 3-2
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[8] A. Weinberger, ―4:2 Carry-Save Adder Module‖, IBM Technical
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[9] S. Veeramachaneni, K. M. Krishna, L. Avinash, S. R. Puppala, and
M. Srinivas, ―Novel architectures for high-speed and low-power
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[10]. Design and Analysis of Approximate Compressors for
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[11]. 4-2 Compressor Design with New XOR-XNOR Module.

BIOGRAPHIES

Sri. A. Sreeramulu Qualification:

received his B.Tech degree in
Electronics & Communications
Engineering from Mother Theresa
College of Engineering & Technology.
He then received his M.Tech Embedded
System from Vekananda Institute Of
Technology &Science., karimnagar. currently he is
working as an Associate Professor in Department of ECE
at Jyothishmathi Institute of Technology and Science,
Nustulapoor, Karimnagar (Telangana, India).

A. Chandrkala Qualification: received

her B.Tech degree in Electronics &
Communications Engineering from Sri
sai jyothi College Of Engineering. She
Pursing M.Tech VLSI at Jyothishmathi
Institute of Technology and Science,
Nustulapoor, Karimnagar (Telangana, India).

L. Srinivas Qualification: received his

B.E degree in Electronics &
Communications Engineering from
Usmaniya University. He is working as
a Lecturer Dept of Technical Education
Telangana.

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